Merge pull request #89 from theunkn0wn1/feature/crc32

F4 CRC peripheral

data/registers/crc_v1.yaml

@@ -0,0 +1,21 @@
+---
+block/CRC:
+  description: Cyclic Redundancy Check calculation unit
+  items:
+    - name: DR
+      description: Data register
+      byte_offset: 0
+    - name: IDR
+      description: Independent Data register
+      byte_offset: 4
+    - name: CR
+      description: Control register
+      byte_offset: 8
+      fieldset: CR
+fieldset/CR:
+  description: Control register
+  fields:
+    - name: RESET
+      description: RESET bit
+      bit_offset: 0
+      bit_size: 1

data/registers/crc_v2.yaml

@@ -0,0 +1,86 @@
+---
+block/CRC:
+  description: Cyclic Redundancy Check calculation unit
+  items:
+    - name: DR
+      description: Data register
+      byte_offset: 0
+    - name: DR16
+      description: Data register - half-word sized
+      byte_offset: 0
+      bit_size: 16
+    - name: DR8
+      description: Data register - byte sized
+      byte_offset: 0
+      bit_size: 8
+    - name: IDR
+      description: Independent Data register
+      byte_offset: 4
+    - name: CR
+      description: Control register
+      byte_offset: 8
+      fieldset: CR
+    - name: INIT
+      description: Initial CRC value
+      byte_offset: 16
+fieldset/CR:
+  description: Control register
+  fields:
+    - name: RESET
+      description: RESET bit
+      bit_offset: 0
+      bit_size: 1
+    - name: POLYSIZE
+      description: Polynomial size
+      bit_offset: 3
+      bit_size: 2
+      enum: POLYSIZE
+    - name: REV_IN
+      description: Reverse input data
+      bit_offset: 5
+      bit_size: 2
+      enum: REV_IN
+    - name: REV_OUT
+      description: Reverse output data
+      bit_offset: 7
+      bit_size: 1
+      enum: REV_OUT
+enum/POLYSIZE:
+  bit_size: 2
+  variants:
+    - name: Polysize32
+      description: 32-bit polynomial
+      value: 0
+    - name: Polysize16
+      description: 16-bit polynomial
+      value: 1
+    - name: Polysize8
+      description: 8-bit polynomial
+      value: 2
+    - name: Polysize7
+      description: 7-bit polynomial
+      value: 3
+enum/REV_IN:
+  bit_size: 2
+  variants:
+    - name: Normal
+      description: Bit order not affected
+      value: 0
+    - name: Byte
+      description: Bit reversal done by byte
+      value: 1
+    - name: HalfWord
+      description: Bit reversal done by half-word
+      value: 2
+    - name: Word
+      description: Bit reversal done by word
+      value: 3
+enum/REV_OUT:
+  bit_size: 1
+  variants:
+    - name: Normal
+      description: Bit order not affected
+      value: 0
+    - name: Reversed
+      description: Bit reversed output
+      value: 1

data/registers/crc_v3.yaml

@@ -0,0 +1,89 @@
+---
+block/CRC:
+  description: Cyclic Redundancy Check calculation unit
+  items:
+    - name: DR
+      description: Data register
+      byte_offset: 0
+    - name: DR16
+      description: Data register - half-word sized
+      byte_offset: 0
+      bit_size: 16
+    - name: DR8
+      description: Data register - byte sized
+      byte_offset: 0
+      bit_size: 8
+    - name: IDR
+      description: Independent Data register
+      byte_offset: 4
+    - name: CR
+      description: Control register
+      byte_offset: 8
+      fieldset: CR
+    - name: INIT
+      description: Initial CRC value
+      byte_offset: 16
+    - name: POL
+      description: CRC polynomial
+      byte_offset: 20
+fieldset/CR:
+  description: Control register
+  fields:
+    - name: RESET
+      description: RESET bit
+      bit_offset: 0
+      bit_size: 1
+    - name: POLYSIZE
+      description: Polynomial size
+      bit_offset: 3
+      bit_size: 2
+      enum: POLYSIZE
+    - name: REV_IN
+      description: Reverse input data
+      bit_offset: 5
+      bit_size: 2
+      enum: REV_IN
+    - name: REV_OUT
+      description: Reverse output data
+      bit_offset: 7
+      bit_size: 1
+      enum: REV_OUT
+enum/POLYSIZE:
+  bit_size: 2
+  variants:
+    - name: Polysize32
+      description: 32-bit polynomial
+      value: 0
+    - name: Polysize16
+      description: 16-bit polynomial
+      value: 1
+    - name: Polysize8
+      description: 8-bit polynomial
+      value: 2
+    - name: Polysize7
+      description: 7-bit polynomial
+      value: 3
+enum/REV_IN:
+  bit_size: 2
+  variants:
+    - name: Normal
+      description: Bit order not affected
+      value: 0
+    - name: Byte
+      description: Bit reversal done by byte
+      value: 1
+    - name: HalfWord
+      description: Bit reversal done by half-word
+      value: 2
+    - name: Word
+      description: Bit reversal done by word
+      value: 3
+enum/REV_OUT:
+  bit_size: 1
+  variants:
+    - name: Normal
+      description: Bit order not affected
+      value: 0
+    - name: Reversed
+      description: Bit reversed output
+      value: 1

parse.py

@@ -298,7 +298,7 @@ FAKE_PERIPHERALS = [
     'FREERTOS',
     'PDM2PCM',
     'FATFS',
-    'CRC',
+    # 'CRC',
     'LIBJPEG',
     'MBEDTLS',
     'LWIP',
@@ -429,6 +429,16 @@ perimap = [
     ('.*:DMA', 'bdma_v1/DMA'),
 
     ('.*:CAN:bxcan1_v1_1.*', 'can_bxcan/CAN'),
+    # stm32F4 CRC peripheral
+    # ("STM32F4*:CRC:CRC:crc_f4")
+    # v1: F1, F2, F4, L1
+    # v2, adds INIT reg: F0
+    # v3, adds POL reg: F3, F7, G0, G4, H7, L0, L4, L5, WB, WL
+    ('.*:CRC:integtest1_v1_0', 'crc_v1/CRC'),
+    ('STM32L[04].*:CRC:integtest1_v2_0', 'crc_v3/CRC'),
+    ('.*:CRC:integtest1_v2_0', 'crc_v2/CRC'),
+    ('.*:CRC:integtest1_v2_2', 'crc_v3/CRC'),
+
 ]
 
 # Device address overrides, in case of missing from headers