From a8a8b88661a8b41c17e38a2ff0e2c3146ad8ecd7 Mon Sep 17 00:00:00 2001 From: Joshua Salzedo Date: Fri, 24 Sep 2021 16:59:18 -0700 Subject: [PATCH 1/4] add CRC32 peripheral for the F4 family --- data/registers/crc_f4.yaml | 45 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 data/registers/crc_f4.yaml diff --git a/data/registers/crc_f4.yaml b/data/registers/crc_f4.yaml new file mode 100644 index 0000000..146d161 --- /dev/null +++ b/data/registers/crc_f4.yaml @@ -0,0 +1,45 @@ +block/CRC: + description: Cryptographic processor + items: + - byte_offset: 0 + description: Data register + fieldset: DR + name: DR + - byte_offset: 4 + description: Independent Data register + fieldset: IDR + name: IDR + - access: Write + byte_offset: 8 + description: Control register + fieldset: CR + name: CR +enum/RESETW: + bit_size: 1 + variants: + - description: Resets the CRC calculation unit and sets the data register to 0xFFFF + FFFF + name: Reset + value: 1 +fieldset/CR: + description: Control register + fields: + - bit_offset: 0 + bit_size: 1 + description: Control regidter + enum_write: RESETW + name: RESET +fieldset/DR: + description: Data register + fields: + - bit_offset: 0 + bit_size: 32 + description: Data Register + name: DR +fieldset/IDR: + description: Independent Data register + fields: + - bit_offset: 0 + bit_size: 8 + description: Independent Data register + name: IDR From 24dabf68e54a754989f424d5031c3d9decd2e9a8 Mon Sep 17 00:00:00 2001 From: Joshua Salzedo Date: Sun, 26 Sep 2021 14:58:47 -0700 Subject: [PATCH 2/4] Add three distinct versions of CRC - remove F4 specific version --- data/registers/crc_f4.yaml | 45 ----------- data/registers/crc_v1.yaml | 45 +++++++++++ data/registers/crc_v2.yaml | 139 ++++++++++++++++++++++++++++++++++ data/registers/crc_v3.yaml | 151 +++++++++++++++++++++++++++++++++++++ 4 files changed, 335 insertions(+), 45 deletions(-) delete mode 100644 data/registers/crc_f4.yaml create mode 100644 data/registers/crc_v1.yaml create mode 100644 data/registers/crc_v2.yaml create mode 100644 data/registers/crc_v3.yaml diff --git a/data/registers/crc_f4.yaml b/data/registers/crc_f4.yaml deleted file mode 100644 index 146d161..0000000 --- a/data/registers/crc_f4.yaml +++ /dev/null @@ -1,45 +0,0 @@ -block/CRC: - description: Cryptographic processor - items: - - byte_offset: 0 - description: Data register - fieldset: DR - name: DR - - byte_offset: 4 - description: Independent Data register - fieldset: IDR - name: IDR - - access: Write - byte_offset: 8 - description: Control register - fieldset: CR - name: CR -enum/RESETW: - bit_size: 1 - variants: - - description: Resets the CRC calculation unit and sets the data register to 0xFFFF - FFFF - name: Reset - value: 1 -fieldset/CR: - description: Control register - fields: - - bit_offset: 0 - bit_size: 1 - description: Control regidter - enum_write: RESETW - name: RESET -fieldset/DR: - description: Data register - fields: - - bit_offset: 0 - bit_size: 32 - description: Data Register - name: DR -fieldset/IDR: - description: Independent Data register - fields: - - bit_offset: 0 - bit_size: 8 - description: Independent Data register - name: IDR diff --git a/data/registers/crc_v1.yaml b/data/registers/crc_v1.yaml new file mode 100644 index 0000000..2586515 --- /dev/null +++ b/data/registers/crc_v1.yaml @@ -0,0 +1,45 @@ +--- +block/CRC: + description: Cryptographic processor + items: + - name: DR + description: Data register + byte_offset: 0 + fieldset: DR + - name: IDR + description: Independent Data register + byte_offset: 4 + fieldset: IDR + - name: CR + description: Control register + byte_offset: 8 + access: Write + fieldset: CR +fieldset/CR: + description: Control register + fields: + - name: RESET + description: Control regidter + bit_offset: 0 + bit_size: 1 + enum_write: RESETW +fieldset/DR: + description: Data register + fields: + - name: DR + description: Data Register + bit_offset: 0 + bit_size: 32 +fieldset/IDR: + description: Independent Data register + fields: + - name: IDR + description: Independent Data register + bit_offset: 0 + bit_size: 8 +enum/RESETW: + bit_size: 1 + variants: + - name: Reset + description: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF + value: 1 diff --git a/data/registers/crc_v2.yaml b/data/registers/crc_v2.yaml new file mode 100644 index 0000000..337b43c --- /dev/null +++ b/data/registers/crc_v2.yaml @@ -0,0 +1,139 @@ +--- +block/CRC: + description: cyclic redundancy check calculation unit + items: + - name: DR + description: Data register + byte_offset: 0 + fieldset: DR + - name: DR16 + description: Data register - half-word sized + byte_offset: 0 + bit_size: 16 + fieldset: DR16 + - name: DR8 + description: Data register - byte sized + byte_offset: 0 + bit_size: 8 + fieldset: DR8 + - name: IDR + description: Independent data register + byte_offset: 4 + fieldset: IDR + - name: CR + description: Control register + byte_offset: 8 + fieldset: CR + - name: INIT + description: Initial CRC value + byte_offset: 16 + fieldset: INIT +fieldset/CR: + description: Control register + fields: + - name: RESET + description: reset bit + bit_offset: 0 + bit_size: 1 + enum_write: RESETW + - name: POLYSIZE + description: Polynomial size + bit_offset: 3 + bit_size: 2 + enum: POLYSIZE + - name: REV_IN + description: Reverse input data + bit_offset: 5 + bit_size: 2 + enum: REV_IN + - name: REV_OUT + description: Reverse output data + bit_offset: 7 + bit_size: 1 + enum: REV_OUT +fieldset/DR: + description: Data register + fields: + - name: DR + description: Data register bits + bit_offset: 0 + bit_size: 32 +fieldset/DR16: + description: Data register - half-word sized + fields: + - name: DR + description: Data register bits + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +fieldset/DR8: + description: Data register - byte sized + fields: + - name: DR + description: Data register bits + bit_offset: 0 + bit_size: 8 + array: + len: 1 + stride: 0 +fieldset/IDR: + description: Independent data register + fields: + - name: IDR + description: General-purpose 8-bit data register bits + bit_offset: 0 + bit_size: 8 +fieldset/INIT: + description: Initial CRC value + fields: + - name: INIT + description: Programmable initial CRC value + bit_offset: 0 + bit_size: 32 +enum/POLYSIZE: + bit_size: 2 + variants: + - name: Polysize32 + description: 32-bit polynomial + value: 0 + - name: Polysize16 + description: 16-bit polynomial + value: 1 + - name: Polysize8 + description: 8-bit polynomial + value: 2 + - name: Polysize7 + description: 7-bit polynomial + value: 3 +enum/RESETW: + bit_size: 1 + variants: + - name: Reset + description: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF + value: 1 +enum/REV_IN: + bit_size: 2 + variants: + - name: Normal + description: Bit order not affected + value: 0 + - name: Byte + description: Bit reversal done by byte + value: 1 + - name: HalfWord + description: Bit reversal done by half-word + value: 2 + - name: Word + description: Bit reversal done by word + value: 3 +enum/REV_OUT: + bit_size: 1 + variants: + - name: Normal + description: Bit order not affected + value: 0 + - name: Reversed + description: Bit reversed output + value: 1 diff --git a/data/registers/crc_v3.yaml b/data/registers/crc_v3.yaml new file mode 100644 index 0000000..0eba325 --- /dev/null +++ b/data/registers/crc_v3.yaml @@ -0,0 +1,151 @@ +--- +block/CRC: + description: Cryptographic processor + items: + - name: DR + description: Data register + byte_offset: 0 + fieldset: DR + - name: DR16 + description: Data register - half-word sized + byte_offset: 0 + bit_size: 16 + fieldset: DR16 + - name: DR8 + description: Data register - byte sized + byte_offset: 0 + bit_size: 8 + fieldset: DR8 + - name: IDR + description: Independent Data register + byte_offset: 4 + fieldset: IDR + - name: CR + description: Control register + byte_offset: 8 + access: Write + fieldset: CR + - name: INIT + description: Initial CRC value + byte_offset: 16 + fieldset: INIT + - name: POL + description: CRC polynomial + byte_offset: 20 + fieldset: POL +fieldset/CR: + description: Control register + fields: + - name: RESET + description: RESET bit + bit_offset: 0 + bit_size: 1 + enum_write: RESETW + - name: POLYSIZE + description: Polynomial size + bit_offset: 3 + bit_size: 2 + enum: POLYSIZE + - name: REV_IN + description: Reverse input data + bit_offset: 5 + bit_size: 2 + enum: REV_IN + - name: REV_OUT + description: Reverse output data + bit_offset: 7 + bit_size: 1 + enum: REV_OUT +fieldset/DR: + description: Data register + fields: + - name: DR + description: Data Register + bit_offset: 0 + bit_size: 32 +fieldset/DR16: + description: Data register - half-word sized + fields: + - name: DR + description: Data register bits + bit_offset: 0 + bit_size: 16 + array: + len: 1 + stride: 0 +fieldset/DR8: + description: Data register - byte sized + fields: + - name: DR + description: Data register bits + bit_offset: 0 + bit_size: 8 + array: + len: 1 + stride: 0 +fieldset/IDR: + description: Independent Data register + fields: + - name: IDR + description: Independent Data register + bit_offset: 0 + bit_size: 8 +fieldset/INIT: + description: Initial CRC value + fields: + - name: INIT + description: Programmable initial CRC value + bit_offset: 0 + bit_size: 32 +fieldset/POL: + description: CRC polynomial + fields: + - name: POL + description: Programmable polynomial + bit_offset: 0 + bit_size: 32 +enum/POLYSIZE: + bit_size: 2 + variants: + - name: Polysize32 + description: 32-bit polynomial + value: 0 + - name: Polysize16 + description: 16-bit polynomial + value: 1 + - name: Polysize8 + description: 8-bit polynomial + value: 2 + - name: Polysize7 + description: 7-bit polynomial + value: 3 +enum/RESETW: + bit_size: 1 + variants: + - name: Reset + description: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF + value: 1 +enum/REV_IN: + bit_size: 2 + variants: + - name: Normal + description: Bit order not affected + value: 0 + - name: Byte + description: Bit reversal done by byte + value: 1 + - name: HalfWord + description: Bit reversal done by half-word + value: 2 + - name: Word + description: Bit reversal done by word + value: 3 +enum/REV_OUT: + bit_size: 1 + variants: + - name: Normal + description: Bit order not affected + value: 0 + - name: Reversed + description: Bit reversed output + value: 1 From fb4d8b7033b0d5b293ceb847e3ebc32db494fef9 Mon Sep 17 00:00:00 2001 From: Joshua Salzedo Date: Sun, 26 Sep 2021 15:09:45 -0700 Subject: [PATCH 3/4] Add CRC rules to parse.py --- parse.py | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/parse.py b/parse.py index 2292bc9..eb981df 100755 --- a/parse.py +++ b/parse.py @@ -298,7 +298,7 @@ FAKE_PERIPHERALS = [ 'FREERTOS', 'PDM2PCM', 'FATFS', - 'CRC', + # 'CRC', 'LIBJPEG', 'MBEDTLS', 'LWIP', @@ -429,6 +429,16 @@ perimap = [ ('.*:DMA', 'bdma_v1/DMA'), ('.*:CAN:bxcan1_v1_1.*', 'can_bxcan/CAN'), + # stm32F4 CRC peripheral + # ("STM32F4*:CRC:CRC:crc_f4") + # v1: F1, F2, F4, L1 + # v2, adds INIT reg: F0 + # v3, adds POL reg: F3, F7, G0, G4, H7, L0, L4, L5, WB, WL + ('.*:CRC:integtest1_v1_0', 'crc_v1/CRC'), + ('STM32L[04].*:CRC:integtest1_v2_0', 'crc_v3/CRC'), + ('.*:CRC:integtest1_v2_0', 'crc_v2/CRC'), + ('.*:CRC:integtest1_v2_2', 'crc_v3/CRC'), + ] # Device address overrides, in case of missing from headers From f6ce6dc36b0555366144caae086891fc5029cf2c Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 27 Sep 2021 00:26:04 +0200 Subject: [PATCH 4/4] CRC register cleanup --- data/registers/crc_v1.yaml | 28 ++--------------- data/registers/crc_v2.yaml | 59 ++--------------------------------- data/registers/crc_v3.yaml | 64 +------------------------------------- 3 files changed, 6 insertions(+), 145 deletions(-) diff --git a/data/registers/crc_v1.yaml b/data/registers/crc_v1.yaml index 2586515..0c9e3d9 100644 --- a/data/registers/crc_v1.yaml +++ b/data/registers/crc_v1.yaml @@ -1,45 +1,21 @@ --- block/CRC: - description: Cryptographic processor + description: Cyclic Redundancy Check calculation unit items: - name: DR description: Data register byte_offset: 0 - fieldset: DR - name: IDR description: Independent Data register byte_offset: 4 - fieldset: IDR - name: CR description: Control register byte_offset: 8 - access: Write fieldset: CR fieldset/CR: description: Control register fields: - name: RESET - description: Control regidter + description: RESET bit bit_offset: 0 bit_size: 1 - enum_write: RESETW -fieldset/DR: - description: Data register - fields: - - name: DR - description: Data Register - bit_offset: 0 - bit_size: 32 -fieldset/IDR: - description: Independent Data register - fields: - - name: IDR - description: Independent Data register - bit_offset: 0 - bit_size: 8 -enum/RESETW: - bit_size: 1 - variants: - - name: Reset - description: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF - value: 1 diff --git a/data/registers/crc_v2.yaml b/data/registers/crc_v2.yaml index 337b43c..f6551d1 100644 --- a/data/registers/crc_v2.yaml +++ b/data/registers/crc_v2.yaml @@ -1,25 +1,21 @@ --- block/CRC: - description: cyclic redundancy check calculation unit + description: Cyclic Redundancy Check calculation unit items: - name: DR description: Data register byte_offset: 0 - fieldset: DR - name: DR16 description: Data register - half-word sized byte_offset: 0 bit_size: 16 - fieldset: DR16 - name: DR8 description: Data register - byte sized byte_offset: 0 bit_size: 8 - fieldset: DR8 - name: IDR - description: Independent data register + description: Independent Data register byte_offset: 4 - fieldset: IDR - name: CR description: Control register byte_offset: 8 @@ -27,15 +23,13 @@ block/CRC: - name: INIT description: Initial CRC value byte_offset: 16 - fieldset: INIT fieldset/CR: description: Control register fields: - name: RESET - description: reset bit + description: RESET bit bit_offset: 0 bit_size: 1 - enum_write: RESETW - name: POLYSIZE description: Polynomial size bit_offset: 3 @@ -51,47 +45,6 @@ fieldset/CR: bit_offset: 7 bit_size: 1 enum: REV_OUT -fieldset/DR: - description: Data register - fields: - - name: DR - description: Data register bits - bit_offset: 0 - bit_size: 32 -fieldset/DR16: - description: Data register - half-word sized - fields: - - name: DR - description: Data register bits - bit_offset: 0 - bit_size: 16 - array: - len: 1 - stride: 0 -fieldset/DR8: - description: Data register - byte sized - fields: - - name: DR - description: Data register bits - bit_offset: 0 - bit_size: 8 - array: - len: 1 - stride: 0 -fieldset/IDR: - description: Independent data register - fields: - - name: IDR - description: General-purpose 8-bit data register bits - bit_offset: 0 - bit_size: 8 -fieldset/INIT: - description: Initial CRC value - fields: - - name: INIT - description: Programmable initial CRC value - bit_offset: 0 - bit_size: 32 enum/POLYSIZE: bit_size: 2 variants: @@ -107,12 +60,6 @@ enum/POLYSIZE: - name: Polysize7 description: 7-bit polynomial value: 3 -enum/RESETW: - bit_size: 1 - variants: - - name: Reset - description: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF - value: 1 enum/REV_IN: bit_size: 2 variants: diff --git a/data/registers/crc_v3.yaml b/data/registers/crc_v3.yaml index 0eba325..da8c544 100644 --- a/data/registers/crc_v3.yaml +++ b/data/registers/crc_v3.yaml @@ -1,38 +1,31 @@ --- block/CRC: - description: Cryptographic processor + description: Cyclic Redundancy Check calculation unit items: - name: DR description: Data register byte_offset: 0 - fieldset: DR - name: DR16 description: Data register - half-word sized byte_offset: 0 bit_size: 16 - fieldset: DR16 - name: DR8 description: Data register - byte sized byte_offset: 0 bit_size: 8 - fieldset: DR8 - name: IDR description: Independent Data register byte_offset: 4 - fieldset: IDR - name: CR description: Control register byte_offset: 8 - access: Write fieldset: CR - name: INIT description: Initial CRC value byte_offset: 16 - fieldset: INIT - name: POL description: CRC polynomial byte_offset: 20 - fieldset: POL fieldset/CR: description: Control register fields: @@ -40,7 +33,6 @@ fieldset/CR: description: RESET bit bit_offset: 0 bit_size: 1 - enum_write: RESETW - name: POLYSIZE description: Polynomial size bit_offset: 3 @@ -56,54 +48,6 @@ fieldset/CR: bit_offset: 7 bit_size: 1 enum: REV_OUT -fieldset/DR: - description: Data register - fields: - - name: DR - description: Data Register - bit_offset: 0 - bit_size: 32 -fieldset/DR16: - description: Data register - half-word sized - fields: - - name: DR - description: Data register bits - bit_offset: 0 - bit_size: 16 - array: - len: 1 - stride: 0 -fieldset/DR8: - description: Data register - byte sized - fields: - - name: DR - description: Data register bits - bit_offset: 0 - bit_size: 8 - array: - len: 1 - stride: 0 -fieldset/IDR: - description: Independent Data register - fields: - - name: IDR - description: Independent Data register - bit_offset: 0 - bit_size: 8 -fieldset/INIT: - description: Initial CRC value - fields: - - name: INIT - description: Programmable initial CRC value - bit_offset: 0 - bit_size: 32 -fieldset/POL: - description: CRC polynomial - fields: - - name: POL - description: Programmable polynomial - bit_offset: 0 - bit_size: 32 enum/POLYSIZE: bit_size: 2 variants: @@ -119,12 +63,6 @@ enum/POLYSIZE: - name: Polysize7 description: 7-bit polynomial value: 3 -enum/RESETW: - bit_size: 1 - variants: - - name: Reset - description: Resets the CRC calculation unit and sets the data register to 0xFFFF FFFF - value: 1 enum/REV_IN: bit_size: 2 variants: