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u5/rcc: fix inconsistent DCMI bit names

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This commit is contained in:
Dario Nieuwenhuis 2022-02-05 03:02:57 +01:00
parent c1c3d8b354
commit f79e304d07
1 changed files with 3 additions and 3 deletions
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6
data/registers/rcc_u5.yaml
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@ -402,7 +402,7 @@ fieldset/AHB2ENR1:
description: "ADC1 clock enable\r Set and cleared by software."
bit_offset: 10
bit_size: 1
- name: DCMI_PSSIEN
- name: DCMIEN
description: "DCMI and PSSI clock enable\r Set and cleared by software."
bit_offset: 12
bit_size: 1
@ -516,7 +516,7 @@ fieldset/AHB2RSTR1:
description: "ADC1 reset\r Set and cleared by software."
bit_offset: 10
bit_size: 1
- name: DCMI_PSSIRST
- name: DCMIRST
description: "DCMI and PSSI reset\r Set and cleared by software."
bit_offset: 12
bit_size: 1
@ -622,7 +622,7 @@ fieldset/AHB2SMENR1:
description: "ADC1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 10
bit_size: 1
- name: DCMI_PSSISMEN
- name: DCMISMEN
description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software."
bit_offset: 12
bit_size: 1