diff --git a/data/registers/rcc_u5.yaml b/data/registers/rcc_u5.yaml
index acdf0a3..f6a8b21 100644
--- a/data/registers/rcc_u5.yaml
+++ b/data/registers/rcc_u5.yaml
@@ -402,7 +402,7 @@ fieldset/AHB2ENR1:
       description: "ADC1 clock enable\r Set and cleared by software."
       bit_offset: 10
       bit_size: 1
-    - name: DCMI_PSSIEN
+    - name: DCMIEN
       description: "DCMI and PSSI clock enable\r Set and cleared by software."
       bit_offset: 12
       bit_size: 1
@@ -516,7 +516,7 @@ fieldset/AHB2RSTR1:
       description: "ADC1 reset\r Set and cleared by software."
       bit_offset: 10
       bit_size: 1
-    - name: DCMI_PSSIRST
+    - name: DCMIRST
       description: "DCMI and PSSI reset\r Set and cleared by software."
       bit_offset: 12
       bit_size: 1
@@ -622,7 +622,7 @@ fieldset/AHB2SMENR1:
       description: "ADC1 clocks enable during Sleep and Stop modes\r Set and cleared by software."
       bit_offset: 10
       bit_size: 1
-    - name: DCMI_PSSISMEN
+    - name: DCMISMEN
       description: "DCMI and PSSI clocks enable during Sleep and Stop modes\r Set and cleared by software."
       bit_offset: 12
       bit_size: 1