fdcan: fix register block definitions; separate version for H7
the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to have no bearing on the actual registers used. Thus chips.rs should make no distinction between v1_0 and v1_1. the previous YAML seems to have been generated from a G4 SVD, but this series' SVDs consistently have several errata. I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5 chips. the H7 series has a totally different FDCAN, so I've added a separate YAML for it.
This commit is contained in:
Torin Cooper-Bennun
parent
f6d1ffc1a2
commit
f65fd694e1
@ -1,893 +0,0 @@
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block/FDCAN:
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description: FDCAN
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items:
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- name: CREL
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description: FDCAN Core Release Register
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byte_offset: 0
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access: Read
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fieldset: CREL
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- name: ENDN
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description: FDCAN Core Release Register
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byte_offset: 4
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access: Read
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fieldset: ENDN
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- name: DBTP
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description: This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
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byte_offset: 12
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fieldset: DBTP
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- name: TEST
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description: Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
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byte_offset: 16
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fieldset: TEST
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- name: RWD
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description: The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
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byte_offset: 20
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fieldset: RWD
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- name: CCCR
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description: For details about setting and resetting of single bits see Software initialization.
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byte_offset: 24
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fieldset: CCCR
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- name: NBTP
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description: FDCAN_NBTP
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byte_offset: 28
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fieldset: NBTP
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- name: TSCC
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description: FDCAN Timestamp Counter Configuration Register
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byte_offset: 32
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fieldset: TSCC
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- name: TSCV
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description: FDCAN Timestamp Counter Value Register
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byte_offset: 36
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fieldset: TSCV
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- name: TOCC
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description: FDCAN Timeout Counter Configuration Register
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byte_offset: 40
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fieldset: TOCC
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- name: TOCV
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description: FDCAN Timeout Counter Value Register
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byte_offset: 44
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fieldset: TOCV
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- name: ECR
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description: FDCAN Error Counter Register
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byte_offset: 64
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access: Read
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fieldset: ECR
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- name: PSR
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description: FDCAN Protocol Status Register
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byte_offset: 68
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fieldset: PSR
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- name: TDCR
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description: FDCAN Transmitter Delay Compensation Register
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byte_offset: 72
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fieldset: TDCR
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- name: IR
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description: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
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byte_offset: 80
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fieldset: IR
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- name: IE
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description: The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.
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byte_offset: 84
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fieldset: IE
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- name: ILS
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description: The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
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byte_offset: 88
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fieldset: ILS
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- name: ILE
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description: Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
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byte_offset: 92
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fieldset: ILE
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- name: RXGFC
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description: 'Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.'
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byte_offset: 128
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fieldset: RXGFC
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- name: XIDAM
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description: FDCAN Extended ID and Mask Register
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byte_offset: 132
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fieldset: XIDAM
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- name: HPMS
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description: This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
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byte_offset: 136
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access: Read
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fieldset: HPMS
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- name: RXFS
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description: FDCAN Rx FIFO X Status Register
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array:
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offsets:
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- 0
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- 8
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byte_offset: 144
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access: Read
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fieldset: RXFS
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- name: RXFA
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description: CAN Rx FIFO 0 Acknowledge Register
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array:
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offsets:
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- 0
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- 8
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byte_offset: 148
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fieldset: RXFA
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- name: TXBC
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description: FDCAN Tx Buffer Configuration Register
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byte_offset: 192
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fieldset: TXBC
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- name: TXFQS
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description: The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).
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byte_offset: 196
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access: Read
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fieldset: TXFQS
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- name: TXBRP
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description: FDCAN Tx Buffer Request Pending Register
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byte_offset: 200
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access: Read
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fieldset: TXBRP
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- name: TXBAR
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description: FDCAN Tx Buffer Add Request Register
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byte_offset: 204
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fieldset: TXBAR
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- name: TXBCR
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description: FDCAN Tx Buffer Cancellation Request Register
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byte_offset: 208
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fieldset: TXBCR
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- name: TXBTO
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description: FDCAN Tx Buffer Transmission Occurred Register
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byte_offset: 212
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access: Read
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fieldset: TXBTO
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- name: TXBCF
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description: FDCAN Tx Buffer Cancellation Finished Register
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byte_offset: 216
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access: Read
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fieldset: TXBCF
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- name: TXBTIE
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description: FDCAN Tx Buffer Transmission Interrupt Enable Register
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byte_offset: 220
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fieldset: TXBTIE
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- name: TXBCIE
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description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
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byte_offset: 224
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fieldset: TXBCIE
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- name: TXEFS
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description: FDCAN Tx Event FIFO Status Register
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byte_offset: 228
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access: Read
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fieldset: TXEFS
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- name: TXEFA
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description: FDCAN Tx Event FIFO Acknowledge Register
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byte_offset: 232
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fieldset: TXEFA
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- name: CKDIV
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description: FDCAN CFG clock divider register
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byte_offset: 256
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fieldset: CKDIV
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fieldset/CCCR:
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description: For details about setting and resetting of single bits see Software initialization.
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fields:
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- name: INIT
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description: INIT
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bit_offset: 0
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bit_size: 1
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- name: CCE
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description: CCE
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bit_offset: 1
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bit_size: 1
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- name: ASM
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description: ASM
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bit_offset: 2
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bit_size: 1
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- name: CSA
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description: CSA
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bit_offset: 3
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bit_size: 1
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- name: CSR
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description: CSR
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bit_offset: 4
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bit_size: 1
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- name: MON
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description: MON
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bit_offset: 5
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bit_size: 1
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- name: DAR
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description: DAR
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bit_offset: 6
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bit_size: 1
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- name: TEST
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description: TEST
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bit_offset: 7
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bit_size: 1
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- name: FDOE
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description: FDOE
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bit_offset: 8
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bit_size: 1
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- name: BRSE
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description: BRSE
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bit_offset: 9
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bit_size: 1
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- name: PXHD
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description: PXHD
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bit_offset: 12
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bit_size: 1
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- name: EFBI
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description: EFBI
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bit_offset: 13
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bit_size: 1
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- name: TXP
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description: TXP
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bit_offset: 14
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bit_size: 1
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- name: NISO
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description: NISO
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bit_offset: 15
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bit_size: 1
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fieldset/CKDIV:
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description: FDCAN CFG clock divider register
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fields:
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- name: PDIV
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description: input clock divider. the APB clock could be divided prior to be used by the CAN sub
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bit_offset: 0
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bit_size: 4
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fieldset/CREL:
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description: FDCAN Core Release Register
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fields:
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- name: DAY
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description: DAY
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bit_offset: 0
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bit_size: 8
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- name: MON
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description: MON
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bit_offset: 8
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bit_size: 8
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- name: YEAR
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description: YEAR
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bit_offset: 16
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bit_size: 4
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- name: SUBSTEP
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description: SUBSTEP
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bit_offset: 20
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bit_size: 4
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- name: STEP
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description: STEP
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bit_offset: 24
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bit_size: 4
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- name: REL
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description: REL
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bit_offset: 28
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bit_size: 4
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fieldset/DBTP:
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description: This register is only writable if bits CCCR.CCE and CCCR.INIT are set. The CAN bit time may be programed in the range of 4 to 25 time quanta. The CAN time quantum may be programmed in the range of 1 to 1024 FDCAN clock periods. tq = (DBRP + 1) FDCAN clock period. DTSEG1 is the sum of Prop_Seg and Phase_Seg1. DTSEG2 is Phase_Seg2. Therefore the length of the bit time is (programmed values) [DTSEG1 + DTSEG2 + 3] tq or (functional values) [Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2] tq. The Information Processing Time (IPT) is zero, meaning the data for the next bit is available at the first clock edge after the sample point.
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fields:
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- name: DSJW
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description: DSJW
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bit_offset: 0
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bit_size: 4
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- name: DTSEG2
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description: DTSEG2
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bit_offset: 4
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bit_size: 4
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- name: DTSEG1
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description: DTSEG1
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bit_offset: 8
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bit_size: 5
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- name: DBRP
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description: DBRP
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bit_offset: 16
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bit_size: 5
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- name: TDC
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description: TDC
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bit_offset: 23
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bit_size: 1
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fieldset/ECR:
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description: FDCAN Error Counter Register
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fields:
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- name: TEC
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description: TEC
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bit_offset: 0
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bit_size: 8
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- name: REC
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description: TREC
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bit_offset: 8
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bit_size: 7
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- name: RP
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description: RP
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bit_offset: 15
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bit_size: 1
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- name: CEL
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description: CEL
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bit_offset: 16
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bit_size: 8
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fieldset/ENDN:
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description: FDCAN Core Release Register
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fields:
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- name: ETV
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description: ETV
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bit_offset: 0
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bit_size: 32
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fieldset/HPMS:
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description: This register is updated every time a Message ID filter element configured to generate a priority event match. This can be used to monitor the status of incoming high priority messages and to enable fast access to these messages.
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fields:
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- name: BIDX
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description: BIDX
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bit_offset: 0
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bit_size: 6
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- name: MSI
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description: MSI
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bit_offset: 6
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bit_size: 2
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- name: FIDX
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description: FIDX
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bit_offset: 8
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bit_size: 7
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- name: FLST
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description: FLST
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bit_offset: 15
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bit_size: 1
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fieldset/IE:
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description: The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.
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fields:
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- name: RFNE
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description: Rx FIFO X new message enable
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bit_offset: 0
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bit_size: 1
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array:
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offsets:
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- 0
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- 3
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- name: RFFE
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description: Rx FIFO X full enable
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bit_offset: 1
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bit_size: 1
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array:
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offsets:
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- 0
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- 3
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- name: RFLE
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description: Rx FIFO X message lost enable
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bit_offset: 2
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bit_size: 1
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array:
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offsets:
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- 0
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- 3
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- name: HPME
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description: High-priority message enable
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bit_offset: 6
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bit_size: 1
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- name: TCE
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description: Transmission completed enable
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bit_offset: 7
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bit_size: 1
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- name: TCFE
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description: Transmission cancellation finished enable
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bit_offset: 8
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bit_size: 1
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- name: TFEE
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description: Tx FIFO empty enable
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bit_offset: 9
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bit_size: 1
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- name: TEFNE
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description: Tx even FIFO new entry enable
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bit_offset: 10
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bit_size: 1
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- name: TEFFE
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description: Tx event FIFO full enable
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bit_offset: 11
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bit_size: 1
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- name: TEFLE
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description: Tx event FIFO element lost enable
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bit_offset: 12
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bit_size: 1
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- name: TSWE
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description: Timestamp wraparound enable
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bit_offset: 13
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bit_size: 1
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- name: MRAFE
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description: Message RAM access failure enable
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|
||||||
bit_offset: 14
|
|
||||||
bit_size: 1
|
|
||||||
- name: TOOE
|
|
||||||
description: Timeout occurred enable
|
|
||||||
bit_offset: 15
|
|
||||||
bit_size: 1
|
|
||||||
- name: ELOE
|
|
||||||
description: Error logging overflow enable
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 1
|
|
||||||
- name: EPE
|
|
||||||
description: Error passive enable
|
|
||||||
bit_offset: 17
|
|
||||||
bit_size: 1
|
|
||||||
- name: EWE
|
|
||||||
description: Warning status enable
|
|
||||||
bit_offset: 18
|
|
||||||
bit_size: 1
|
|
||||||
- name: BOE
|
|
||||||
description: Bus_off status enable
|
|
||||||
bit_offset: 19
|
|
||||||
bit_size: 1
|
|
||||||
- name: WDIE
|
|
||||||
description: Watchdog interrupt enable
|
|
||||||
bit_offset: 20
|
|
||||||
bit_size: 1
|
|
||||||
- name: PEAE
|
|
||||||
description: Protocol error in arbitration phase enable
|
|
||||||
bit_offset: 21
|
|
||||||
bit_size: 1
|
|
||||||
- name: PEDE
|
|
||||||
description: Protocol error in data phase enable
|
|
||||||
bit_offset: 22
|
|
||||||
bit_size: 1
|
|
||||||
- name: ARAE
|
|
||||||
description: Access to reserved address enable
|
|
||||||
bit_offset: 23
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/ILE:
|
|
||||||
description: Each of the two interrupt lines to the CPU can be enabled/disabled separately by programming bits EINT0 and EINT1.
|
|
||||||
fields:
|
|
||||||
- name: EINT0
|
|
||||||
description: EINT0
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 1
|
|
||||||
- name: EINT1
|
|
||||||
description: EINT1
|
|
||||||
bit_offset: 1
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/ILS:
|
|
||||||
description: The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1].
|
|
||||||
fields:
|
|
||||||
- name: RXFIFO
|
|
||||||
description: RX FIFO bit grouping the following interruption
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 1
|
|
||||||
array:
|
|
||||||
len: 2
|
|
||||||
stride: 1
|
|
||||||
- name: SMSG
|
|
||||||
description: Status message bit grouping the following interruption
|
|
||||||
bit_offset: 2
|
|
||||||
bit_size: 1
|
|
||||||
- name: TFERR
|
|
||||||
description: TX FIFO error grouping the following interruption
|
|
||||||
bit_offset: 3
|
|
||||||
bit_size: 1
|
|
||||||
- name: MISC
|
|
||||||
description: Interrupt regrouping the following interruption
|
|
||||||
bit_offset: 4
|
|
||||||
bit_size: 1
|
|
||||||
- name: BERR
|
|
||||||
description: Bit and line error grouping the following interruption
|
|
||||||
bit_offset: 5
|
|
||||||
bit_size: 1
|
|
||||||
- name: PERR
|
|
||||||
description: Protocol error grouping the following interruption
|
|
||||||
bit_offset: 6
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/IR:
|
|
||||||
description: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
|
|
||||||
fields:
|
|
||||||
- name: RFN
|
|
||||||
description: Rx FIFO X new message
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 1
|
|
||||||
array:
|
|
||||||
offsets:
|
|
||||||
- 0
|
|
||||||
- 3
|
|
||||||
- name: RFF
|
|
||||||
description: Rx FIFO X full
|
|
||||||
bit_offset: 1
|
|
||||||
bit_size: 1
|
|
||||||
array:
|
|
||||||
offsets:
|
|
||||||
- 0
|
|
||||||
- 3
|
|
||||||
- name: RFL
|
|
||||||
description: Rx FIFO X message lost
|
|
||||||
bit_offset: 2
|
|
||||||
bit_size: 1
|
|
||||||
array:
|
|
||||||
offsets:
|
|
||||||
- 0
|
|
||||||
- 3
|
|
||||||
- name: HPM
|
|
||||||
description: High-priority message
|
|
||||||
bit_offset: 6
|
|
||||||
bit_size: 1
|
|
||||||
- name: TC
|
|
||||||
description: Transmission completed
|
|
||||||
bit_offset: 7
|
|
||||||
bit_size: 1
|
|
||||||
- name: TCF
|
|
||||||
description: Transmission cancellation finished
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 1
|
|
||||||
- name: TFE
|
|
||||||
description: Tx FIFO empty
|
|
||||||
bit_offset: 9
|
|
||||||
bit_size: 1
|
|
||||||
- name: TEFN
|
|
||||||
description: Tx even FIFO new entry
|
|
||||||
bit_offset: 10
|
|
||||||
bit_size: 1
|
|
||||||
- name: TEFF
|
|
||||||
description: Tx event FIFO full
|
|
||||||
bit_offset: 11
|
|
||||||
bit_size: 1
|
|
||||||
- name: TEFL
|
|
||||||
description: Tx event FIFO element lost
|
|
||||||
bit_offset: 12
|
|
||||||
bit_size: 1
|
|
||||||
- name: TSW
|
|
||||||
description: Timestamp wraparound
|
|
||||||
bit_offset: 13
|
|
||||||
bit_size: 1
|
|
||||||
- name: MRAF
|
|
||||||
description: Message RAM access failure
|
|
||||||
bit_offset: 14
|
|
||||||
bit_size: 1
|
|
||||||
- name: TOO
|
|
||||||
description: Timeout occurred
|
|
||||||
bit_offset: 15
|
|
||||||
bit_size: 1
|
|
||||||
- name: ELO
|
|
||||||
description: Error logging overflow
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 1
|
|
||||||
- name: EP
|
|
||||||
description: Error passive
|
|
||||||
bit_offset: 17
|
|
||||||
bit_size: 1
|
|
||||||
- name: EW
|
|
||||||
description: Warning status
|
|
||||||
bit_offset: 18
|
|
||||||
bit_size: 1
|
|
||||||
- name: BO
|
|
||||||
description: Bus_off status
|
|
||||||
bit_offset: 19
|
|
||||||
bit_size: 1
|
|
||||||
- name: WDI
|
|
||||||
description: Watchdog interrupt
|
|
||||||
bit_offset: 20
|
|
||||||
bit_size: 1
|
|
||||||
- name: PEA
|
|
||||||
description: Protocol error in arbitration phase
|
|
||||||
bit_offset: 21
|
|
||||||
bit_size: 1
|
|
||||||
- name: PED
|
|
||||||
description: Protocol error in data phase
|
|
||||||
bit_offset: 22
|
|
||||||
bit_size: 1
|
|
||||||
- name: ARA
|
|
||||||
description: Access to reserved address
|
|
||||||
bit_offset: 23
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/NBTP:
|
|
||||||
description: FDCAN_NBTP
|
|
||||||
fields:
|
|
||||||
- name: NTSEG2
|
|
||||||
description: TSEG2
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 7
|
|
||||||
- name: NTSEG1
|
|
||||||
description: NTSEG1
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 8
|
|
||||||
- name: NBRP
|
|
||||||
description: NBRP
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 9
|
|
||||||
- name: NSJW
|
|
||||||
description: NSJW
|
|
||||||
bit_offset: 25
|
|
||||||
bit_size: 7
|
|
||||||
fieldset/PSR:
|
|
||||||
description: FDCAN Protocol Status Register
|
|
||||||
fields:
|
|
||||||
- name: LEC
|
|
||||||
description: LEC
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
- name: ACT
|
|
||||||
description: ACT
|
|
||||||
bit_offset: 3
|
|
||||||
bit_size: 2
|
|
||||||
- name: EP
|
|
||||||
description: EP
|
|
||||||
bit_offset: 5
|
|
||||||
bit_size: 1
|
|
||||||
- name: EW
|
|
||||||
description: EW
|
|
||||||
bit_offset: 6
|
|
||||||
bit_size: 1
|
|
||||||
- name: BO
|
|
||||||
description: BO
|
|
||||||
bit_offset: 7
|
|
||||||
bit_size: 1
|
|
||||||
- name: DLEC
|
|
||||||
description: DLEC
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 3
|
|
||||||
- name: RESI
|
|
||||||
description: RESI
|
|
||||||
bit_offset: 11
|
|
||||||
bit_size: 1
|
|
||||||
- name: RBRS
|
|
||||||
description: RBRS
|
|
||||||
bit_offset: 12
|
|
||||||
bit_size: 1
|
|
||||||
- name: REDL
|
|
||||||
description: REDL
|
|
||||||
bit_offset: 13
|
|
||||||
bit_size: 1
|
|
||||||
- name: PXE
|
|
||||||
description: PXE
|
|
||||||
bit_offset: 14
|
|
||||||
bit_size: 1
|
|
||||||
- name: TDCV
|
|
||||||
description: TDCV
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 7
|
|
||||||
fieldset/RWD:
|
|
||||||
description: The RAM Watchdog monitors the READY output of the Message RAM. A Message RAM access starts the Message RAM Watchdog Counter with the value configured by the RWD[WDC] bits. The counter is reloaded with RWD[WDC] bits when the Message RAM signals successful completion by activating its READY output. In case there is no response from the Message RAM until the counter has counted down to 0, the counter stops and interrupt flag IR[WDI] bit is set. The RAM Watchdog Counter is clocked by the fdcan_pclk clock.
|
|
||||||
fields:
|
|
||||||
- name: WDC
|
|
||||||
description: WDC
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 8
|
|
||||||
- name: WDV
|
|
||||||
description: WDV
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 8
|
|
||||||
fieldset/RXFA:
|
|
||||||
description: CAN Rx FIFO X Acknowledge Register
|
|
||||||
fields:
|
|
||||||
- name: FAI
|
|
||||||
description: FAI
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 6
|
|
||||||
fieldset/RXFS:
|
|
||||||
description: FDCAN Rx FIFO X Status Register
|
|
||||||
fields:
|
|
||||||
- name: FFL
|
|
||||||
description: FFL
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 7
|
|
||||||
- name: FGI
|
|
||||||
description: FGI
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 6
|
|
||||||
- name: FPI
|
|
||||||
description: FPI
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 6
|
|
||||||
- name: FF
|
|
||||||
description: FF
|
|
||||||
bit_offset: 24
|
|
||||||
bit_size: 1
|
|
||||||
- name: RFL
|
|
||||||
description: RFL
|
|
||||||
bit_offset: 25
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/RXGFC:
|
|
||||||
description: 'Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path.'
|
|
||||||
fields:
|
|
||||||
- name: RRFE
|
|
||||||
description: RRFE
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 1
|
|
||||||
- name: RRFS
|
|
||||||
description: RRFS
|
|
||||||
bit_offset: 1
|
|
||||||
bit_size: 1
|
|
||||||
- name: ANFE
|
|
||||||
description: ANFE
|
|
||||||
bit_offset: 2
|
|
||||||
bit_size: 2
|
|
||||||
- name: ANFS
|
|
||||||
description: ANFS
|
|
||||||
bit_offset: 4
|
|
||||||
bit_size: 2
|
|
||||||
- name: F1OM
|
|
||||||
description: FIFO 1 operation mode
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 1
|
|
||||||
- name: F0OM
|
|
||||||
description: FIFO 0 operation mode
|
|
||||||
bit_offset: 9
|
|
||||||
bit_size: 1
|
|
||||||
- name: LSS
|
|
||||||
description: List size standard
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 5
|
|
||||||
- name: LSE
|
|
||||||
description: List size extended
|
|
||||||
bit_offset: 24
|
|
||||||
bit_size: 4
|
|
||||||
fieldset/TDCR:
|
|
||||||
description: FDCAN Transmitter Delay Compensation Register
|
|
||||||
fields:
|
|
||||||
- name: TDCF
|
|
||||||
description: TDCF
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 7
|
|
||||||
- name: TDCO
|
|
||||||
description: TDCO
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 7
|
|
||||||
fieldset/TEST:
|
|
||||||
description: Write access to the Test Register has to be enabled by setting bit CCCR[TEST] to 1 . All Test Register functions are set to their reset values when bit CCCR[TEST] is reset. Loop Back mode and software control of Tx pin FDCANx_TX are hardware test modes. Programming TX differently from 00 may disturb the message transfer on the CAN bus.
|
|
||||||
fields:
|
|
||||||
- name: LBCK
|
|
||||||
description: LBCK
|
|
||||||
bit_offset: 4
|
|
||||||
bit_size: 1
|
|
||||||
- name: TX
|
|
||||||
description: TX
|
|
||||||
bit_offset: 5
|
|
||||||
bit_size: 2
|
|
||||||
- name: RX
|
|
||||||
description: RX
|
|
||||||
bit_offset: 7
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/TOCC:
|
|
||||||
description: FDCAN Timeout Counter Configuration Register
|
|
||||||
fields:
|
|
||||||
- name: ETOC
|
|
||||||
description: ETOC
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 1
|
|
||||||
- name: TOS
|
|
||||||
description: TOS
|
|
||||||
bit_offset: 1
|
|
||||||
bit_size: 2
|
|
||||||
- name: TOP
|
|
||||||
description: TOP
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 16
|
|
||||||
fieldset/TOCV:
|
|
||||||
description: FDCAN Timeout Counter Value Register
|
|
||||||
fields:
|
|
||||||
- name: TOC
|
|
||||||
description: TOC
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 16
|
|
||||||
fieldset/TSCC:
|
|
||||||
description: FDCAN Timestamp Counter Configuration Register
|
|
||||||
fields:
|
|
||||||
- name: TSS
|
|
||||||
description: TSS
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 2
|
|
||||||
- name: TCP
|
|
||||||
description: TCP
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 4
|
|
||||||
fieldset/TSCV:
|
|
||||||
description: FDCAN Timestamp Counter Value Register
|
|
||||||
fields:
|
|
||||||
- name: TSC
|
|
||||||
description: TSC
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 16
|
|
||||||
fieldset/TXBAR:
|
|
||||||
description: FDCAN Tx Buffer Add Request Register
|
|
||||||
fields:
|
|
||||||
- name: AR
|
|
||||||
description: AR
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
fieldset/TXBC:
|
|
||||||
description: FDCAN Tx Buffer Configuration Register
|
|
||||||
fields:
|
|
||||||
- name: TBSA
|
|
||||||
description: TBSA
|
|
||||||
bit_offset: 2
|
|
||||||
bit_size: 14
|
|
||||||
- name: NDTB
|
|
||||||
description: NDTB
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 6
|
|
||||||
- name: TFQS
|
|
||||||
description: TFQS
|
|
||||||
bit_offset: 24
|
|
||||||
bit_size: 6
|
|
||||||
- name: TFQM
|
|
||||||
description: TFQM
|
|
||||||
bit_offset: 30
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/TXBCF:
|
|
||||||
description: FDCAN Tx Buffer Cancellation Finished Register
|
|
||||||
fields:
|
|
||||||
- name: CF
|
|
||||||
description: CF
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
fieldset/TXBCIE:
|
|
||||||
description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
|
|
||||||
fields:
|
|
||||||
- name: CFIE
|
|
||||||
description: CFIE
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
fieldset/TXBCR:
|
|
||||||
description: FDCAN Tx Buffer Cancellation Request Register
|
|
||||||
fields:
|
|
||||||
- name: CR
|
|
||||||
description: CR
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
fieldset/TXBRP:
|
|
||||||
description: FDCAN Tx Buffer Request Pending Register
|
|
||||||
fields:
|
|
||||||
- name: TRP
|
|
||||||
description: TRP
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
fieldset/TXBTIE:
|
|
||||||
description: FDCAN Tx Buffer Transmission Interrupt Enable Register
|
|
||||||
fields:
|
|
||||||
- name: TIE
|
|
||||||
description: TIE
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
fieldset/TXBTO:
|
|
||||||
description: FDCAN Tx Buffer Transmission Occurred Register
|
|
||||||
fields:
|
|
||||||
- name: TO
|
|
||||||
description: TO
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
fieldset/TXEFA:
|
|
||||||
description: FDCAN Tx Event FIFO Acknowledge Register
|
|
||||||
fields:
|
|
||||||
- name: EFAI
|
|
||||||
description: EFAI
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 5
|
|
||||||
fieldset/TXEFS:
|
|
||||||
description: FDCAN Tx Event FIFO Status Register
|
|
||||||
fields:
|
|
||||||
- name: EFFL
|
|
||||||
description: EFFL
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
- name: EFGI
|
|
||||||
description: EFGI
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 2
|
|
||||||
- name: EFPI
|
|
||||||
description: EFPI
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 2
|
|
||||||
- name: EFF
|
|
||||||
description: EFF
|
|
||||||
bit_offset: 24
|
|
||||||
bit_size: 1
|
|
||||||
- name: TEFL
|
|
||||||
description: TEFL
|
|
||||||
bit_offset: 25
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/TXFQS:
|
|
||||||
description: The Tx FIFO/Queue status is related to the pending Tx requests listed in register TXBRP. Therefore the effect of Add/Cancellation requests may be delayed due to a running Tx scan (TXBRP not yet updated).
|
|
||||||
fields:
|
|
||||||
- name: TFFL
|
|
||||||
description: TFFL
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 3
|
|
||||||
- name: TFGI
|
|
||||||
description: TFGI
|
|
||||||
bit_offset: 8
|
|
||||||
bit_size: 2
|
|
||||||
- name: TFQPI
|
|
||||||
description: TFQPI
|
|
||||||
bit_offset: 16
|
|
||||||
bit_size: 2
|
|
||||||
- name: TFQF
|
|
||||||
description: TFQF
|
|
||||||
bit_offset: 21
|
|
||||||
bit_size: 1
|
|
||||||
fieldset/XIDAM:
|
|
||||||
description: FDCAN Extended ID and Mask Register
|
|
||||||
fields:
|
|
||||||
- name: EIDM
|
|
||||||
description: EIDM
|
|
||||||
bit_offset: 0
|
|
||||||
bit_size: 29
|
|
||||||
1741
data/registers/can_fdcan_h7.yaml
Normal file
1741
data/registers/can_fdcan_h7.yaml
Normal file
File diff suppressed because it is too large
Load Diff
1054
data/registers/can_fdcan_v1.yaml
Normal file
1054
data/registers/can_fdcan_v1.yaml
Normal file
File diff suppressed because it is too large
Load Diff
@ -457,7 +457,8 @@ impl PeriMatcher {
|
|||||||
("STM32H7.*:DMA.*", ("dma", "v1", "DMA")),
|
("STM32H7.*:DMA.*", ("dma", "v1", "DMA")),
|
||||||
(".*:DMA.*", ("bdma", "v1", "DMA")),
|
(".*:DMA.*", ("bdma", "v1", "DMA")),
|
||||||
(".*:CAN:bxcan1_v1_1.*", ("can", "bxcan", "CAN")),
|
(".*:CAN:bxcan1_v1_1.*", ("can", "bxcan", "CAN")),
|
||||||
(".*:FDCAN:fdcan1_v1_0.*", ("can", "fdcan", "FDCAN")),
|
("STM32H7.*:FDCAN:fdcan1_v1_[01].*", ("can", "fdcan_h7", "FDCAN")),
|
||||||
|
(".*:FDCAN:fdcan1_v1_[01].*", ("can", "fdcan_v1", "FDCAN")),
|
||||||
// # stm32F4 CRC peripheral
|
// # stm32F4 CRC peripheral
|
||||||
// # ("STM32F4*:CRC:CRC:crc_f4")
|
// # ("STM32F4*:CRC:CRC:crc_f4")
|
||||||
// # v1: F1, F2, F4, L1
|
// # v1: F1, F2, F4, L1
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user