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stm32-data/data/registers/can_fdcan_h7.yaml
Torin Cooper-Bennun f65fd694e1 fdcan: fix register block definitions; separate version for H7 
the Cube XMLs refer to "fdcan_v1_0" and "fdcan_v1_1" but these seem to
have no bearing on the actual registers used. Thus chips.rs should make
no distinction between v1_0 and v1_1.

the previous YAML seems to have been generated from a G4 SVD, but this
series' SVDs consistently have several errata.

I have therefore replaced can_fdcan.yaml with can_fdcan_v1.yaml, built
from an H5 SVD which appears to match the RMs of G0, G4, H5 and L5
chips.

the H7 series has a totally different FDCAN, so I've added a separate
YAML for it.
2023-11-21 10:45:51 +00:00

1742 lines
40 KiB
YAML
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block/FDCAN:
description: Controller area network with flexible data rate (FD)
items:
- name: CREL
description: FDCAN Core Release Register
byte_offset: 0
fieldset: CREL
- name: ENDN
description: FDCAN Core Release Register
byte_offset: 4
fieldset: ENDN
- name: DBTP
description: FDCAN Data Bit Timing and Prescaler Register
byte_offset: 12
fieldset: DBTP
- name: TEST
description: FDCAN Test Register
byte_offset: 16
fieldset: TEST
- name: RWD
description: FDCAN RAM Watchdog Register
byte_offset: 20
fieldset: RWD
- name: CCCR
description: FDCAN CC Control Register
byte_offset: 24
fieldset: CCCR
- name: NBTP
description: FDCAN Nominal Bit Timing and Prescaler Register
byte_offset: 28
fieldset: NBTP
- name: TSCC
description: FDCAN Timestamp Counter Configuration Register
byte_offset: 32
fieldset: TSCC
- name: TSCV
description: FDCAN Timestamp Counter Value Register
byte_offset: 36
fieldset: TSCV
- name: TOCC
description: FDCAN Timeout Counter Configuration Register
byte_offset: 40
fieldset: TOCC
- name: TOCV
description: FDCAN Timeout Counter Value Register
byte_offset: 44
fieldset: TOCV
- name: ECR
description: FDCAN Error Counter Register
byte_offset: 64
fieldset: ECR
- name: PSR
description: FDCAN Protocol Status Register
byte_offset: 68
fieldset: PSR
- name: TDCR
description: FDCAN Transmitter Delay Compensation Register
byte_offset: 72
fieldset: TDCR
- name: IR
description: FDCAN Interrupt Register
byte_offset: 80
fieldset: IR
- name: IE
description: FDCAN Interrupt Enable Register
byte_offset: 84
fieldset: IE
- name: ILS
description: FDCAN Interrupt Line Select Register
byte_offset: 88
fieldset: ILS
- name: ILE
description: FDCAN Interrupt Line Enable Register
byte_offset: 92
fieldset: ILE
- name: GFC
description: FDCAN Global Filter Configuration Register
byte_offset: 128
fieldset: GFC
- name: SIDFC
description: FDCAN Standard ID Filter Configuration Register
byte_offset: 132
fieldset: SIDFC
- name: XIDFC
description: FDCAN Extended ID Filter Configuration Register
byte_offset: 136
fieldset: XIDFC
- name: XIDAM
description: FDCAN Extended ID and Mask Register
byte_offset: 144
fieldset: XIDAM
- name: HPMS
description: FDCAN High Priority Message Status Register
byte_offset: 148
fieldset: HPMS
- name: NDAT1
description: FDCAN New Data 1 Register
byte_offset: 152
fieldset: NDAT1
- name: NDAT2
description: FDCAN New Data 2 Register
byte_offset: 156
fieldset: NDAT2
- name: RXFC
description: FDCAN Rx FIFO X Configuration Register
array:
offsets:
- 0
- 16
byte_offset: 160
fieldset: RXFC
- name: RXFS
description: FDCAN Rx FIFO X Status Register
array:
offsets:
- 0
- 16
byte_offset: 164
fieldset: RXFS
- name: RXFA
description: CAN Rx FIFO X Acknowledge Register
array:
offsets:
- 0
- 16
byte_offset: 168
fieldset: RXFA
- name: RXBC
description: FDCAN Rx Buffer Configuration Register
byte_offset: 172
fieldset: RXBC
- name: RXESC
description: FDCAN Rx Buffer Element Size Configuration Register
byte_offset: 188
fieldset: RXESC
- name: TXBC
description: FDCAN Tx Buffer Configuration Register
byte_offset: 192
fieldset: TXBC
- name: TXFQS
description: FDCAN Tx FIFO/Queue Status Register
byte_offset: 196
fieldset: TXFQS
- name: TXESC
description: FDCAN Tx Buffer Element Size Configuration Register
byte_offset: 200
fieldset: TXESC
- name: TXBRP
description: FDCAN Tx Buffer Request Pending Register
byte_offset: 204
fieldset: TXBRP
- name: TXBAR
description: FDCAN Tx Buffer Add Request Register
byte_offset: 208
fieldset: TXBAR
- name: TXBCR
description: FDCAN Tx Buffer Cancellation Request Register
byte_offset: 212
fieldset: TXBCR
- name: TXBTO
description: FDCAN Tx Buffer Transmission Occurred Register
byte_offset: 216
fieldset: TXBTO
- name: TXBCF
description: FDCAN Tx Buffer Cancellation Finished Register
byte_offset: 220
fieldset: TXBCF
- name: TXBTIE
description: FDCAN Tx Buffer Transmission Interrupt Enable Register
byte_offset: 224
fieldset: TXBTIE
- name: TXBCIE
description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
byte_offset: 228
fieldset: TXBCIE
- name: TXEFC
description: FDCAN Tx Event FIFO Configuration Register
byte_offset: 240
fieldset: TXEFC
- name: TXEFS
description: FDCAN Tx Event FIFO Status Register
byte_offset: 244
fieldset: TXEFS
- name: TXEFA
description: FDCAN Tx Event FIFO Acknowledge Register
byte_offset: 248
fieldset: TXEFA
- name: TTTMC
description: FDCAN TT Trigger Memory Configuration Register
byte_offset: 256
fieldset: TTTMC
- name: TTRMC
description: FDCAN TT Reference Message Configuration Register
byte_offset: 260
fieldset: TTRMC
- name: TTOCF
description: FDCAN TT Operation Configuration Register
byte_offset: 264
fieldset: TTOCF
- name: TTMLM
description: FDCAN TT Matrix Limits Register
byte_offset: 268
fieldset: TTMLM
- name: TURCF
description: FDCAN TUR Configuration Register
byte_offset: 272
fieldset: TURCF
- name: TTOCN
description: FDCAN TT Operation Control Register
byte_offset: 276
fieldset: TTOCN
- name: TTGTP
description: FDCAN TT Global Time Preset Register
byte_offset: 280
fieldset: TTGTP
- name: TTTMK
description: FDCAN TT Time Mark Register
byte_offset: 284
fieldset: TTTMK
- name: TTIR
description: FDCAN TT Interrupt Register
byte_offset: 288
fieldset: TTIR
- name: TTIE
description: FDCAN TT Interrupt Enable Register
byte_offset: 292
fieldset: TTIE
- name: TTILS
description: FDCAN TT Interrupt Line Select Register
byte_offset: 296
fieldset: TTILS
- name: TTOST
description: FDCAN TT Operation Status Register
byte_offset: 300
fieldset: TTOST
- name: TURNA
description: FDCAN TUR Numerator Actual Register
byte_offset: 304
fieldset: TURNA
- name: TTLGT
description: FDCAN TT Local and Global Time Register
byte_offset: 308
fieldset: TTLGT
- name: TTCTC
description: FDCAN TT Cycle Time and Count Register
byte_offset: 312
fieldset: TTCTC
- name: TTCPT
description: FDCAN TT Capture Time Register
byte_offset: 316
fieldset: TTCPT
- name: TTCSM
description: FDCAN TT Cycle Sync Mark Register
byte_offset: 320
fieldset: TTCSM
- name: TTTS
description: FDCAN TT Trigger Select Register
byte_offset: 768
fieldset: TTTS
fieldset/CCCR:
description: FDCAN CC Control Register
fields:
- name: INIT
description: Initialization
bit_offset: 0
bit_size: 1
- name: CCE
description: Configuration Change Enable
bit_offset: 1
bit_size: 1
- name: ASM
description: ASM Restricted Operation Mode
bit_offset: 2
bit_size: 1
- name: CSA
description: Clock Stop Acknowledge
bit_offset: 3
bit_size: 1
- name: CSR
description: Clock Stop Request
bit_offset: 4
bit_size: 1
- name: MON
description: Bus Monitoring Mode
bit_offset: 5
bit_size: 1
- name: DAR
description: Disable Automatic Retransmission
bit_offset: 6
bit_size: 1
- name: TEST
description: Test Mode Enable
bit_offset: 7
bit_size: 1
- name: FDOE
description: FD Operation Enable
bit_offset: 8
bit_size: 1
- name: BSE
description: FDCAN Bit Rate Switching
bit_offset: 9
bit_size: 1
- name: PXHD
description: Protocol Exception Handling Disable
bit_offset: 12
bit_size: 1
- name: EFBI
description: Edge Filtering during Bus Integration
bit_offset: 13
bit_size: 1
- name: TXP
description: TXP
bit_offset: 14
bit_size: 1
- name: NISO
description: Non ISO Operation
bit_offset: 15
bit_size: 1
fieldset/CREL:
description: FDCAN Core Release Register
fields:
- name: DAY
description: Timestamp Day
bit_offset: 0
bit_size: 8
- name: MON
description: Timestamp Month
bit_offset: 8
bit_size: 8
- name: YEAR
description: Timestamp Year
bit_offset: 16
bit_size: 4
- name: SUBSTEP
description: Sub-step of Core release
bit_offset: 20
bit_size: 4
- name: STEP
description: Step of Core release
bit_offset: 24
bit_size: 4
- name: REL
description: Core release
bit_offset: 28
bit_size: 4
fieldset/DBTP:
description: FDCAN Data Bit Timing and Prescaler Register
fields:
- name: DSJW
description: Synchronization Jump Width
bit_offset: 0
bit_size: 4
- name: DTSEG2
description: Data time segment after sample point
bit_offset: 4
bit_size: 4
- name: DTSEG1
description: Data time segment after sample point
bit_offset: 8
bit_size: 5
- name: DBRP
description: Data BIt Rate Prescaler
bit_offset: 16
bit_size: 5
- name: TDC
description: Transceiver Delay Compensation
bit_offset: 23
bit_size: 1
fieldset/ECR:
description: FDCAN Error Counter Register
fields:
- name: TEC
description: Transmit Error Counter
bit_offset: 0
bit_size: 8
- name: REC
description: Receive Error Counter
bit_offset: 8
bit_size: 7
- name: RP
description: Receive Error Passive
bit_offset: 15
bit_size: 1
- name: CEL
description: AN Error Logging
bit_offset: 16
bit_size: 8
fieldset/ENDN:
description: FDCAN Core Release Register
fields:
- name: ETV
description: Endiannes Test Value
bit_offset: 0
bit_size: 32
fieldset/GFC:
description: FDCAN Global Filter Configuration Register
fields:
- name: RRFE
description: Reject Remote Frames Extended
bit_offset: 0
bit_size: 1
- name: RRFS
description: Reject Remote Frames Standard
bit_offset: 1
bit_size: 1
- name: ANFE
description: Accept Non-matching Frames Extended
bit_offset: 2
bit_size: 2
- name: ANFS
description: Accept Non-matching Frames Standard
bit_offset: 4
bit_size: 2
fieldset/HPMS:
description: FDCAN High Priority Message Status Register
fields:
- name: BIDX
description: Buffer Index
bit_offset: 0
bit_size: 6
- name: MSI
description: Message Storage Indicator
bit_offset: 6
bit_size: 2
- name: FIDX
description: Filter Index
bit_offset: 8
bit_size: 7
- name: FLST
description: Filter List
bit_offset: 15
bit_size: 1
fieldset/IE:
description: FDCAN Interrupt Enable Register
fields:
- name: RFNE
description: Rx FIFO X New Message Enable
bit_offset: 0
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFWE
description: Rx FIFO X Watermark Reached Enable
bit_offset: 1
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFFE
description: Rx FIFO X Full Enable
bit_offset: 2
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFLE
description: Rx FIFO X Message Lost Enable
bit_offset: 3
bit_size: 1
array:
offsets:
- 0
- 4
- name: HPME
description: High Priority Message Enable
bit_offset: 8
bit_size: 1
- name: TCE
description: Transmission Completed Enable
bit_offset: 9
bit_size: 1
- name: TCFE
description: Transmission Cancellation Finished Enable
bit_offset: 10
bit_size: 1
- name: TEFE
description: Tx FIFO Empty Enable
bit_offset: 11
bit_size: 1
- name: TEFNE
description: Tx Event FIFO New Entry Enable
bit_offset: 12
bit_size: 1
- name: TEFWE
description: Tx Event FIFO Watermark Reached Enable
bit_offset: 13
bit_size: 1
- name: TEFFE
description: Tx Event FIFO Full Enable
bit_offset: 14
bit_size: 1
- name: TEFLE
description: Tx Event FIFO Element Lost Enable
bit_offset: 15
bit_size: 1
- name: TSWE
description: Timestamp Wraparound Enable
bit_offset: 16
bit_size: 1
- name: MRAFE
description: Message RAM Access Failure Enable
bit_offset: 17
bit_size: 1
- name: TOOE
description: Timeout Occurred Enable
bit_offset: 18
bit_size: 1
- name: DRXE
description: Message stored to Dedicated Rx Buffer Enable
bit_offset: 19
bit_size: 1
- name: BECE
description: Bit Error Corrected Interrupt Enable
bit_offset: 20
bit_size: 1
- name: BEUE
description: Bit Error Uncorrected Interrupt Enable
bit_offset: 21
bit_size: 1
- name: ELOE
description: Error Logging Overflow Enable
bit_offset: 22
bit_size: 1
- name: EPE
description: Error Passive Enable
bit_offset: 23
bit_size: 1
- name: EWE
description: Warning Status Enable
bit_offset: 24
bit_size: 1
- name: BOE
description: Bus_Off Status Enable
bit_offset: 25
bit_size: 1
- name: WDIE
description: Watchdog Interrupt Enable
bit_offset: 26
bit_size: 1
- name: PEAE
description: Protocol Error in Arbitration Phase Enable
bit_offset: 27
bit_size: 1
- name: PEDE
description: Protocol Error in Data Phase Enable
bit_offset: 28
bit_size: 1
- name: ARAE
description: Access to Reserved Address Enable
bit_offset: 29
bit_size: 1
fieldset/ILE:
description: FDCAN Interrupt Line Enable Register
fields:
- name: EINT0
description: Enable Interrupt Line 0
bit_offset: 0
bit_size: 1
- name: EINT1
description: Enable Interrupt Line 1
bit_offset: 1
bit_size: 1
fieldset/ILS:
description: FDCAN Interrupt Line Select Register
fields:
- name: RFNL
description: Rx FIFO X New Message Interrupt Line
bit_offset: 0
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFWL
description: Rx FIFO X Watermark Reached Interrupt Line
bit_offset: 1
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFFL
description: Rx FIFO X Full Interrupt Line
bit_offset: 2
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFLL
description: Rx FIFO X Message Lost Interrupt Line
bit_offset: 3
bit_size: 1
array:
offsets:
- 0
- 4
- name: HPML
description: High Priority Message Interrupt Line
bit_offset: 8
bit_size: 1
- name: TCL
description: Transmission Completed Interrupt Line
bit_offset: 9
bit_size: 1
- name: TCFL
description: Transmission Cancellation Finished Interrupt Line
bit_offset: 10
bit_size: 1
- name: TEFL
description: Tx FIFO Empty Interrupt Line
bit_offset: 11
bit_size: 1
- name: TEFNL
description: Tx Event FIFO New Entry Interrupt Line
bit_offset: 12
bit_size: 1
- name: TEFWL
description: Tx Event FIFO Watermark Reached Interrupt Line
bit_offset: 13
bit_size: 1
- name: TEFFL
description: Tx Event FIFO Full Interrupt Line
bit_offset: 14
bit_size: 1
- name: TEFLL
description: Tx Event FIFO Element Lost Interrupt Line
bit_offset: 15
bit_size: 1
- name: TSWL
description: Timestamp Wraparound Interrupt Line
bit_offset: 16
bit_size: 1
- name: MRAFL
description: Message RAM Access Failure Interrupt Line
bit_offset: 17
bit_size: 1
- name: TOOL
description: Timeout Occurred Interrupt Line
bit_offset: 18
bit_size: 1
- name: DRXL
description: Message stored to Dedicated Rx Buffer Interrupt Line
bit_offset: 19
bit_size: 1
- name: BECL
description: Bit Error Corrected Interrupt Line
bit_offset: 20
bit_size: 1
- name: BEUL
description: Bit Error Uncorrected Interrupt Line
bit_offset: 21
bit_size: 1
- name: ELOL
description: Error Logging Overflow Interrupt Line
bit_offset: 22
bit_size: 1
- name: EPL
description: Error Passive Interrupt Line
bit_offset: 23
bit_size: 1
- name: EWL
description: Warning Status Interrupt Line
bit_offset: 24
bit_size: 1
- name: BOL
description: Bus_Off Status
bit_offset: 25
bit_size: 1
- name: WDIL
description: Watchdog Interrupt Line
bit_offset: 26
bit_size: 1
- name: PEAL
description: Protocol Error in Arbitration Phase Line
bit_offset: 27
bit_size: 1
- name: PEDL
description: Protocol Error in Data Phase Line
bit_offset: 28
bit_size: 1
- name: ARAL
description: Access to Reserved Address Line
bit_offset: 29
bit_size: 1
fieldset/IR:
description: FDCAN Interrupt Register
fields:
- name: RFN
description: Rx FIFO X New Message
bit_offset: 0
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFW
description: Rx FIFO X Watermark Reached
bit_offset: 1
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFF
description: Rx FIFO X Full
bit_offset: 2
bit_size: 1
array:
offsets:
- 0
- 4
- name: RFL
description: Rx FIFO X Message Lost
bit_offset: 3
bit_size: 1
array:
offsets:
- 0
- 4
- name: HPM
description: High Priority Message
bit_offset: 8
bit_size: 1
- name: TC
description: Transmission Completed
bit_offset: 9
bit_size: 1
- name: TCF
description: Transmission Cancellation Finished
bit_offset: 10
bit_size: 1
- name: TEF
description: Tx FIFO Empty
bit_offset: 11
bit_size: 1
- name: TEFN
description: Tx Event FIFO New Entry
bit_offset: 12
bit_size: 1
- name: TEFW
description: Tx Event FIFO Watermark Reached
bit_offset: 13
bit_size: 1
- name: TEFF
description: Tx Event FIFO Full
bit_offset: 14
bit_size: 1
- name: TEFL
description: Tx Event FIFO Element Lost
bit_offset: 15
bit_size: 1
- name: TSW
description: Timestamp Wraparound
bit_offset: 16
bit_size: 1
- name: MRAF
description: Message RAM Access Failure
bit_offset: 17
bit_size: 1
- name: TOO
description: Timeout Occurred
bit_offset: 18
bit_size: 1
- name: DRX
description: Message stored to Dedicated Rx Buffer
bit_offset: 19
bit_size: 1
- name: ELO
description: Error Logging Overflow
bit_offset: 22
bit_size: 1
- name: EP
description: Error Passive
bit_offset: 23
bit_size: 1
- name: EW
description: Warning Status
bit_offset: 24
bit_size: 1
- name: BO
description: Bus_Off Status
bit_offset: 25
bit_size: 1
- name: WDI
description: Watchdog Interrupt
bit_offset: 26
bit_size: 1
- name: PEA
description: Protocol Error in Arbitration Phase (Nominal Bit Time is used)
bit_offset: 27
bit_size: 1
- name: PED
description: Protocol Error in Data Phase (Data Bit Time is used)
bit_offset: 28
bit_size: 1
- name: ARA
description: Access to Reserved Address
bit_offset: 29
bit_size: 1
fieldset/NBTP:
description: FDCAN Nominal Bit Timing and Prescaler Register
fields:
- name: NTSEG2
description: Nominal Time segment after sample point
bit_offset: 0
bit_size: 7
- name: NTSEG1
description: Nominal Time segment before sample point
bit_offset: 8
bit_size: 8
- name: NBRP
description: Bit Rate Prescaler
bit_offset: 16
bit_size: 9
- name: NSJW
description: 'NSJW: Nominal (Re)Synchronization Jump Width.'
bit_offset: 25
bit_size: 7
fieldset/NDAT1:
description: FDCAN New Data 1 Register
fields:
- name: ND
description: New data (buffers 0 - 31)
bit_offset: 0
bit_size: 32
fieldset/NDAT2:
description: FDCAN New Data 2 Register
fields:
- name: ND
description: New data (buffers 32 - 63)
bit_offset: 0
bit_size: 32
fieldset/PSR:
description: FDCAN Protocol Status Register
fields:
- name: LEC
description: Last Error Code
bit_offset: 0
bit_size: 3
- name: ACT
description: Activity
bit_offset: 3
bit_size: 2
- name: EP
description: Error Passive
bit_offset: 5
bit_size: 1
- name: EW
description: Warning Status
bit_offset: 6
bit_size: 1
- name: BO
description: Bus_Off Status
bit_offset: 7
bit_size: 1
- name: DLEC
description: Data Last Error Code
bit_offset: 8
bit_size: 3
- name: RESI
description: ESI flag of last received FDCAN Message
bit_offset: 11
bit_size: 1
- name: RBRS
description: BRS flag of last received FDCAN Message
bit_offset: 12
bit_size: 1
- name: REDL
description: Received FDCAN Message
bit_offset: 13
bit_size: 1
- name: PXE
description: Protocol Exception Event
bit_offset: 14
bit_size: 1
- name: TDCV
description: Transmitter Delay Compensation Value
bit_offset: 16
bit_size: 7
fieldset/RWD:
description: FDCAN RAM Watchdog Register
fields:
- name: WDC
description: Watchdog configuration
bit_offset: 0
bit_size: 8
- name: WDV
description: Watchdog value
bit_offset: 8
bit_size: 8
fieldset/RXBC:
description: FDCAN Rx Buffer Configuration Register
fields:
- name: RBSA
description: Rx Buffer Start Address
bit_offset: 2
bit_size: 14
fieldset/RXESC:
description: FDCAN Rx Buffer Element Size Configuration Register
fields:
- name: FDS
description: Rx FIFO X Data Field Size
bit_offset: 0
bit_size: 3
array:
offsets:
- 0
- 4
- name: RBDS
description: Rx Buffer Data Field Size
bit_offset: 8
bit_size: 3
fieldset/RXFA:
description: CAN Rx FIFO X Acknowledge Register
fields:
- name: FAI
description: Rx FIFO X Acknowledge Index
bit_offset: 0
bit_size: 6
fieldset/RXFC:
description: FDCAN Rx FIFO X Configuration Register
fields:
- name: FSA
description: Rx FIFO X Start Address
bit_offset: 2
bit_size: 14
- name: FS
description: Rx FIFO X Size
bit_offset: 16
bit_size: 7
- name: FWM
description: FIFO X Watermark
bit_offset: 24
bit_size: 7
- name: FOM
description: FIFO X operation mode
bit_offset: 31
bit_size: 1
fieldset/RXFS:
description: FDCAN Rx FIFO X Status Register
fields:
# FIXME: RX FIFO 1 Status Register contains a DMS (debug message status) field
# (bits 31:30); how do we accommodate this? do we have to do away with the
# array def for these regs?
- name: FFL
description: Rx FIFO X Fill Level
bit_offset: 0
bit_size: 7
- name: FGI
description: Rx FIFO X Get Index
bit_offset: 8
bit_size: 6
- name: FPI
description: Rx FIFO X Put Index
bit_offset: 16
bit_size: 6
- name: FF
description: Rx FIFO X Full
bit_offset: 24
bit_size: 1
- name: RFL
description: Rx FIFO X Message Lost
bit_offset: 25
bit_size: 1
fieldset/SIDFC:
description: FDCAN Standard ID Filter Configuration Register
fields:
- name: FLSSA
description: Filter List Standard Start Address
bit_offset: 2
bit_size: 14
- name: LSS
description: List Size Standard
bit_offset: 16
bit_size: 8
fieldset/TDCR:
description: FDCAN Transmitter Delay Compensation Register
fields:
- name: TDCF
description: Transmitter Delay Compensation Filter Window Length
bit_offset: 0
bit_size: 7
- name: TDCO
description: Transmitter Delay Compensation Offset
bit_offset: 8
bit_size: 7
fieldset/TEST:
description: FDCAN Test Register
fields:
- name: LBCK
description: Loop Back mode
bit_offset: 4
bit_size: 1
- name: TX
description: Loop Back mode
bit_offset: 5
bit_size: 2
- name: RX
description: Control of Transmit Pin
bit_offset: 7
bit_size: 1
fieldset/TOCC:
description: FDCAN Timeout Counter Configuration Register
fields:
- name: ETOC
description: Enable Timeout Counter
bit_offset: 0
bit_size: 1
- name: TOS
description: Timeout Select
bit_offset: 1
bit_size: 2
- name: TOP
description: Timeout Period
bit_offset: 16
bit_size: 16
fieldset/TOCV:
description: FDCAN Timeout Counter Value Register
fields:
- name: TOC
description: Timeout Counter
bit_offset: 0
bit_size: 16
fieldset/TSCC:
description: FDCAN Timestamp Counter Configuration Register
fields:
- name: TSS
description: Timestamp Select
bit_offset: 0
bit_size: 2
- name: TCP
description: Timestamp Counter Prescaler
bit_offset: 16
bit_size: 4
fieldset/TSCV:
description: FDCAN Timestamp Counter Value Register
fields:
- name: TSC
description: Timestamp Counter
bit_offset: 0
bit_size: 16
fieldset/TTCPT:
description: FDCAN TT Capture Time Register
fields:
- name: CCV
description: Cycle Count Value
bit_offset: 0
bit_size: 6
- name: SWV
description: Stop Watch Value
bit_offset: 16
bit_size: 16
fieldset/TTCSM:
description: FDCAN TT Cycle Sync Mark Register
fields:
- name: CSM
description: Cycle Sync Mark
bit_offset: 0
bit_size: 16
fieldset/TTCTC:
description: FDCAN TT Cycle Time and Count Register
fields:
- name: CT
description: Cycle Time
bit_offset: 0
bit_size: 16
- name: CC
description: Cycle Count
bit_offset: 16
bit_size: 6
fieldset/TTGTP:
description: FDCAN TT Global Time Preset Register
fields:
- name: NCL
description: Time Preset
bit_offset: 0
bit_size: 16
- name: CTP
description: Cycle Time Target Phase
bit_offset: 16
bit_size: 16
fieldset/TTIE:
description: FDCAN TT Interrupt Enable Register
fields:
- name: SBCE
description: Start of Basic Cycle Interrupt Enable
bit_offset: 0
bit_size: 1
- name: SMCE
description: Start of Matrix Cycle Interrupt Enable
bit_offset: 1
bit_size: 1
- name: CSME
description: Change of Synchronization Mode Interrupt Enable
bit_offset: 2
bit_size: 1
- name: SOGE
description: Start of Gap Interrupt Enable
bit_offset: 3
bit_size: 1
- name: RTMIE
description: Register Time Mark Interrupt Enable
bit_offset: 4
bit_size: 1
- name: TTMIE
description: Trigger Time Mark Event Internal Interrupt Enable
bit_offset: 5
bit_size: 1
- name: SWEE
description: Stop Watch Event Interrupt Enable
bit_offset: 6
bit_size: 1
- name: GTWE
description: Global Time Wrap Interrupt Enable
bit_offset: 7
bit_size: 1
- name: GTDE
description: Global Time Discontinuity Interrupt Enable
bit_offset: 8
bit_size: 1
- name: GTEE
description: Global Time Error Interrupt Enable
bit_offset: 9
bit_size: 1
- name: TXUE
description: Tx Count Underflow Interrupt Enable
bit_offset: 10
bit_size: 1
- name: TXOE
description: Tx Count Overflow Interrupt Enable
bit_offset: 11
bit_size: 1
- name: SE1E
description: Scheduling Error 1 Interrupt Enable
bit_offset: 12
bit_size: 1
- name: SE2E
description: Scheduling Error 2 Interrupt Enable
bit_offset: 13
bit_size: 1
- name: ELCE
description: Change Error Level Interrupt Enable
bit_offset: 14
bit_size: 1
- name: IWTGE
description: Initialization Watch Trigger Interrupt Enable
bit_offset: 15
bit_size: 1
- name: WTE
description: Watch Trigger Interrupt Enable
bit_offset: 16
bit_size: 1
- name: AWE
description: Application Watchdog Interrupt Enable
bit_offset: 17
bit_size: 1
- name: CERE
description: Configuration Error Interrupt Enable
bit_offset: 18
bit_size: 1
fieldset/TTILS:
description: FDCAN TT Interrupt Line Select Register
fields:
- name: SBCL
description: Start of Basic Cycle Interrupt Line
bit_offset: 0
bit_size: 1
- name: SMCL
description: Start of Matrix Cycle Interrupt Line
bit_offset: 1
bit_size: 1
- name: CSML
description: Change of Synchronization Mode Interrupt Line
bit_offset: 2
bit_size: 1
- name: SOGL
description: Start of Gap Interrupt Line
bit_offset: 3
bit_size: 1
- name: RTMIL
description: Register Time Mark Interrupt Line
bit_offset: 4
bit_size: 1
- name: TTMIL
description: Trigger Time Mark Event Internal Interrupt Line
bit_offset: 5
bit_size: 1
- name: SWEL
description: Stop Watch Event Interrupt Line
bit_offset: 6
bit_size: 1
- name: GTWL
description: Global Time Wrap Interrupt Line
bit_offset: 7
bit_size: 1
- name: GTDL
description: Global Time Discontinuity Interrupt Line
bit_offset: 8
bit_size: 1
- name: GTEL
description: Global Time Error Interrupt Line
bit_offset: 9
bit_size: 1
- name: TXUL
description: Tx Count Underflow Interrupt Line
bit_offset: 10
bit_size: 1
- name: TXOL
description: Tx Count Overflow Interrupt Line
bit_offset: 11
bit_size: 1
- name: SE1L
description: Scheduling Error 1 Interrupt Line
bit_offset: 12
bit_size: 1
- name: SE2L
description: Scheduling Error 2 Interrupt Line
bit_offset: 13
bit_size: 1
- name: ELCL
description: Change Error Level Interrupt Line
bit_offset: 14
bit_size: 1
- name: IWTGL
description: Initialization Watch Trigger Interrupt Line
bit_offset: 15
bit_size: 1
- name: WTL
description: Watch Trigger Interrupt Line
bit_offset: 16
bit_size: 1
- name: AWL
description: Application Watchdog Interrupt Line
bit_offset: 17
bit_size: 1
- name: CERL
description: Configuration Error Interrupt Line
bit_offset: 18
bit_size: 1
fieldset/TTIR:
description: FDCAN TT Interrupt Register
fields:
- name: SBC
description: Start of Basic Cycle
bit_offset: 0
bit_size: 1
- name: SMC
description: Start of Matrix Cycle
bit_offset: 1
bit_size: 1
- name: CSM
description: Change of Synchronization Mode
bit_offset: 2
bit_size: 1
- name: SOG
description: Start of Gap
bit_offset: 3
bit_size: 1
- name: RTMI
description: Register Time Mark Interrupt
bit_offset: 4
bit_size: 1
- name: TTMI
description: Trigger Time Mark Event Internal
bit_offset: 5
bit_size: 1
- name: SWE
description: Stop Watch Event
bit_offset: 6
bit_size: 1
- name: GTW
description: Global Time Wrap
bit_offset: 7
bit_size: 1
- name: GTD
description: Global Time Discontinuity
bit_offset: 8
bit_size: 1
- name: GTE
description: Global Time Error
bit_offset: 9
bit_size: 1
- name: TXU
description: Tx Count Underflow
bit_offset: 10
bit_size: 1
- name: TXO
description: Tx Count Overflow
bit_offset: 11
bit_size: 1
- name: SE1
description: Scheduling Error 1
bit_offset: 12
bit_size: 1
- name: SE2
description: Scheduling Error 2
bit_offset: 13
bit_size: 1
- name: ELC
description: Error Level Changed
bit_offset: 14
bit_size: 1
- name: IWTG
description: Initialization Watch Trigger
bit_offset: 15
bit_size: 1
- name: WT
description: Watch Trigger
bit_offset: 16
bit_size: 1
- name: AW
description: Application Watchdog
bit_offset: 17
bit_size: 1
- name: CER
description: Configuration Error
bit_offset: 18
bit_size: 1
fieldset/TTLGT:
description: FDCAN TT Local and Global Time Register
fields:
- name: LT
description: Local Time
bit_offset: 0
bit_size: 16
- name: GT
description: Global Time
bit_offset: 16
bit_size: 16
fieldset/TTMLM:
description: FDCAN TT Matrix Limits Register
fields:
- name: CCM
description: Cycle Count Max
bit_offset: 0
bit_size: 6
- name: CSS
description: Cycle Start Synchronization
bit_offset: 6
bit_size: 2
- name: TXEW
description: Tx Enable Window
bit_offset: 8
bit_size: 4
- name: ENTT
description: Expected Number of Tx Triggers
bit_offset: 16
bit_size: 12
fieldset/TTOCF:
description: FDCAN TT Operation Configuration Register
fields:
- name: OM
description: Operation Mode
bit_offset: 0
bit_size: 2
- name: GEN
description: Gap Enable
bit_offset: 3
bit_size: 1
- name: TM
description: Time Master
bit_offset: 4
bit_size: 1
- name: LDSDL
description: LD of Synchronization Deviation Limit
bit_offset: 5
bit_size: 3
- name: IRTO
description: Initial Reference Trigger Offset
bit_offset: 8
bit_size: 7
- name: EECS
description: Enable External Clock Synchronization
bit_offset: 15
bit_size: 1
- name: AWL
description: Application Watchdog Limit
bit_offset: 16
bit_size: 8
- name: EGTF
description: Enable Global Time Filtering
bit_offset: 24
bit_size: 1
- name: ECC
description: Enable Clock Calibration
bit_offset: 25
bit_size: 1
- name: EVTP
description: Event Trigger Polarity
bit_offset: 26
bit_size: 1
fieldset/TTOCN:
description: FDCAN TT Operation Control Register
fields:
- name: SGT
description: Set Global time
bit_offset: 0
bit_size: 1
- name: ECS
description: External Clock Synchronization
bit_offset: 1
bit_size: 1
- name: SWP
description: Stop Watch Polarity
bit_offset: 2
bit_size: 1
- name: SWS
description: Stop Watch Source
bit_offset: 3
bit_size: 2
- name: RTIE
description: Register Time Mark Interrupt Pulse Enable
bit_offset: 5
bit_size: 1
- name: TMC
description: Register Time Mark Compare
bit_offset: 6
bit_size: 2
- name: TTIE
description: Trigger Time Mark Interrupt Pulse Enable
bit_offset: 8
bit_size: 1
- name: GCS
description: Gap Control Select
bit_offset: 9
bit_size: 1
- name: FGP
description: Finish Gap
bit_offset: 10
bit_size: 1
- name: TMG
description: Time Mark Gap
bit_offset: 11
bit_size: 1
- name: NIG
description: Next is Gap
bit_offset: 12
bit_size: 1
- name: ESCN
description: External Synchronization Control
bit_offset: 13
bit_size: 1
- name: LCKC
description: TT Operation Control Register Locked
bit_offset: 15
bit_size: 1
fieldset/TTOST:
description: FDCAN TT Operation Status Register
fields:
- name: EL
description: Error Level
bit_offset: 0
bit_size: 2
- name: MS
description: Master State
bit_offset: 2
bit_size: 2
- name: SYS
description: Synchronization State
bit_offset: 4
bit_size: 2
- name: QGTP
description: Quality of Global Time Phase
bit_offset: 6
bit_size: 1
- name: QCS
description: Quality of Clock Speed
bit_offset: 7
bit_size: 1
- name: RTO
description: Reference Trigger Offset
bit_offset: 8
bit_size: 8
- name: WGTD
description: Wait for Global Time Discontinuity
bit_offset: 22
bit_size: 1
- name: GFI
description: Gap Finished Indicator
bit_offset: 23
bit_size: 1
- name: TMP
description: Time Master Priority
bit_offset: 24
bit_size: 3
- name: GSI
description: Gap Started Indicator
bit_offset: 27
bit_size: 1
- name: WFE
description: Wait for Event
bit_offset: 28
bit_size: 1
- name: AWE
description: Application Watchdog Event
bit_offset: 29
bit_size: 1
- name: WECS
description: Wait for External Clock Synchronization
bit_offset: 30
bit_size: 1
- name: SPL
description: Schedule Phase Lock
bit_offset: 31
bit_size: 1
fieldset/TTRMC:
description: FDCAN TT Reference Message Configuration Register
fields:
- name: RID
description: Reference Identifier
bit_offset: 0
bit_size: 29
- name: XTD
description: Extended Identifier
bit_offset: 30
bit_size: 1
- name: RMPS
description: Reference Message Payload Select
bit_offset: 31
bit_size: 1
fieldset/TTTMC:
description: FDCAN TT Trigger Memory Configuration Register
fields:
- name: TMSA
description: Trigger Memory Start Address
bit_offset: 2
bit_size: 14
- name: TME
description: Trigger Memory Elements
bit_offset: 16
bit_size: 7
fieldset/TTTMK:
description: FDCAN TT Time Mark Register
fields:
- name: TM
description: Time Mark
bit_offset: 0
bit_size: 16
- name: TICC
description: Time Mark Cycle Code
bit_offset: 16
bit_size: 7
- name: LCKM
description: TT Time Mark Register Locked
bit_offset: 31
bit_size: 1
fieldset/TTTS:
description: FDCAN TT Trigger Select Register
fields:
- name: SWTDEL
description: Stop watch trigger input selection
bit_offset: 0
bit_size: 2
- name: EVTSEL
description: Event trigger input selection
bit_offset: 4
bit_size: 2
fieldset/TURCF:
description: FDCAN TUR Configuration Register
fields:
- name: NCL
description: Numerator Configuration Low
bit_offset: 0
bit_size: 16
- name: DC
description: Denominator Configuration
bit_offset: 16
bit_size: 14
- name: ELT
description: Enable Local Time
bit_offset: 31
bit_size: 1
fieldset/TURNA:
description: FDCAN TUR Numerator Actual Register
fields:
- name: NAV
description: Numerator Actual Value
bit_offset: 0
bit_size: 18
fieldset/TXBAR:
description: FDCAN Tx Buffer Add Request Register
fields:
- name: AR
description: Add Request
bit_offset: 0
bit_size: 32
fieldset/TXBC:
description: FDCAN Tx Buffer Configuration Register
fields:
- name: TBSA
description: Tx Buffers Start Address
bit_offset: 2
bit_size: 14
- name: NDTB
description: Number of Dedicated Transmit Buffers
bit_offset: 16
bit_size: 6
- name: TFQS
description: Transmit FIFO/Queue Size
bit_offset: 24
bit_size: 6
- name: TFQM
description: Tx FIFO/Queue Mode
bit_offset: 30
bit_size: 1
fieldset/TXBCF:
description: FDCAN Tx Buffer Cancellation Finished Register
fields:
- name: CF
description: Cancellation Finished
bit_offset: 0
bit_size: 32
fieldset/TXBCIE:
description: FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register
fields:
- name: CF
description: Cancellation Finished Interrupt Enable
bit_offset: 0
bit_size: 32
fieldset/TXBCR:
description: FDCAN Tx Buffer Cancellation Request Register
fields:
- name: CR
description: Cancellation Request
bit_offset: 0
bit_size: 32
fieldset/TXBRP:
description: FDCAN Tx Buffer Request Pending Register
fields:
- name: TRP
description: Transmission Request Pending
bit_offset: 0
bit_size: 32
fieldset/TXBTIE:
description: FDCAN Tx Buffer Transmission Interrupt Enable Register
fields:
- name: TIE
description: Transmission Interrupt Enable
bit_offset: 0
bit_size: 32
fieldset/TXBTO:
description: FDCAN Tx Buffer Transmission Occurred Register
fields:
- name: TO
description: Transmission Occurred
bit_offset: 0
bit_size: 32
fieldset/TXEFA:
description: FDCAN Tx Event FIFO Acknowledge Register
fields:
- name: EFAI
description: Event FIFO Acknowledge Index
bit_offset: 0
bit_size: 5
fieldset/TXEFC:
description: FDCAN Tx Event FIFO Configuration Register
fields:
- name: EFSA
description: Event FIFO Start Address
bit_offset: 2
bit_size: 14
- name: EFS
description: Event FIFO Size
bit_offset: 16
bit_size: 6
- name: EFWM
description: Event FIFO Watermark
bit_offset: 24
bit_size: 6
fieldset/TXEFS:
description: FDCAN Tx Event FIFO Status Register
fields:
- name: EFFL
description: Event FIFO Fill Level
bit_offset: 0
bit_size: 6
- name: EFGI
description: Event FIFO Get Index
bit_offset: 8
bit_size: 5
- name: EFPI
description: Event FIFO put index
bit_offset: 16
bit_size: 5
- name: EFF
description: Event FIFO Full
bit_offset: 24
bit_size: 1
- name: TEFL
description: Tx Event FIFO Element Lost
bit_offset: 25
bit_size: 1
fieldset/TXESC:
description: FDCAN Tx Buffer Element Size Configuration Register
fields:
- name: TBDS
description: Tx Buffer Data Field Size
bit_offset: 0
bit_size: 3
fieldset/TXFQS:
description: FDCAN Tx FIFO/Queue Status Register
fields:
- name: TFFL
description: Tx FIFO Free Level
bit_offset: 0
bit_size: 6
- name: TFGI
description: TFGI
bit_offset: 8
bit_size: 5
- name: TFQPI
description: Tx FIFO/Queue Put Index
bit_offset: 16
bit_size: 5
- name: TFQF
description: Tx FIFO/Queue Full
bit_offset: 21
bit_size: 1
fieldset/XIDAM:
description: FDCAN Extended ID and Mask Register
fields:
- name: EIDM
description: Extended ID Mask
bit_offset: 0
bit_size: 29
fieldset/XIDFC:
description: FDCAN Extended ID Filter Configuration Register
fields:
- name: FLESA
description: Filter List Standard Start Address
bit_offset: 2
bit_size: 14
- name: LSE
description: List Size Extended
bit_offset: 16
bit_size: 8
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