Add RCC support for STM32G0
This commit is contained in:
Ben Gamari
Dario Nieuwenhuis
parent
e735ea9769
commit
f5808de749
955
data/registers/rcc_g0.yaml
Normal file
955
data/registers/rcc_g0.yaml
Normal file
@ -0,0 +1,955 @@
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block/RCC:
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description: Reset and clock control
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items:
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- byte_offset: 0
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description: Clock control register
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fieldset: CR
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name: CR
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- byte_offset: 4
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description: Internal clock sources calibration register
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fieldset: ICSCR
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name: ICSCR
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- byte_offset: 8
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description: Clock configuration register
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fieldset: CFGR
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name: CFGR
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- byte_offset: 12
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description: PLL configuration register
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fieldset: PLLSYSCFGR
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name: PLLSYSCFGR
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- byte_offset: 24
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description: Clock interrupt enable register
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fieldset: CIER
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name: CIER
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- access: Read
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byte_offset: 28
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description: Clock interrupt flag register
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fieldset: CIFR
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name: CIFR
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- access: Write
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byte_offset: 32
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description: Clock interrupt clear register
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fieldset: CICR
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name: CICR
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- byte_offset: 36
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description: GPIO reset register
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fieldset: IOPRSTR
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name: IOPRSTR
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- byte_offset: 40
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description: AHB peripheral reset register
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fieldset: AHBRSTR
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name: AHBRSTR
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- byte_offset: 44
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description: APB peripheral reset register 1
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fieldset: APBRSTR1
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name: APBRSTR1
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- byte_offset: 48
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description: APB peripheral reset register 2
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fieldset: APBRSTR2
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name: APBRSTR2
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- byte_offset: 52
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description: GPIO clock enable register
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fieldset: IOPENR
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name: IOPENR
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- byte_offset: 56
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description: AHB peripheral clock enable register
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fieldset: AHBENR
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name: AHBENR
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- byte_offset: 60
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description: APB peripheral clock enable register 1
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fieldset: APBENR1
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name: APBENR1
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- byte_offset: 64
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description: APB peripheral clock enable register 2
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fieldset: APBENR2
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name: APBENR2
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- byte_offset: 68
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description: GPIO in Sleep mode clock enable register
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fieldset: IOPSMENR
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name: IOPSMENR
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- byte_offset: 72
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description: AHB peripheral clock enable in Sleep mode register
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fieldset: AHBSMENR
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name: AHBSMENR
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- byte_offset: 76
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description: APB peripheral clock enable in Sleep mode register 1
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fieldset: APBSMENR1
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name: APBSMENR1
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- byte_offset: 80
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description: APB peripheral clock enable in Sleep mode register 2
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fieldset: APBSMENR2
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name: APBSMENR2
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- byte_offset: 84
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description: Peripherals independent clock configuration register
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fieldset: CCIPR
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name: CCIPR
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- byte_offset: 92
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description: RTC domain control register
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fieldset: BDCR
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name: BDCR
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- byte_offset: 96
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description: Control/status register
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fieldset: CSR
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name: CSR
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fieldset/AHBENR:
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description: AHB peripheral clock enable register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA clock enable
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name: DMAEN
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- bit_offset: 8
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bit_size: 1
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description: Flash memory interface clock enable
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name: FLASHEN
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- bit_offset: 12
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bit_size: 1
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description: CRC clock enable
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name: CRCEN
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- bit_offset: 16
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bit_size: 1
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description: AES hardware accelerator
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name: AESEN
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- bit_offset: 18
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bit_size: 1
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description: Random number generator clock enable
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name: RNGEN
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fieldset/AHBRSTR:
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description: AHB peripheral reset register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA1 reset
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name: DMARST
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- bit_offset: 8
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bit_size: 1
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description: FLITF reset
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name: FLASHRST
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- bit_offset: 12
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bit_size: 1
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description: CRC reset
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name: CRCRST
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- bit_offset: 16
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bit_size: 1
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description: AES hardware accelerator reset
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name: AESRST
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- bit_offset: 18
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bit_size: 1
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description: Random number generator reset
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name: RNGRST
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fieldset/AHBSMENR:
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description: AHB peripheral clock enable in Sleep mode register
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fields:
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- bit_offset: 0
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bit_size: 1
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description: DMA clock enable during Sleep mode
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name: DMASMEN
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- bit_offset: 8
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bit_size: 1
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description: Flash memory interface clock enable during Sleep mode
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name: FLASHSMEN
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- bit_offset: 9
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bit_size: 1
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description: SRAM clock enable during Sleep mode
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name: SRAMSMEN
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- bit_offset: 12
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bit_size: 1
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description: CRC clock enable during Sleep mode
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name: CRCSMEN
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- bit_offset: 16
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bit_size: 1
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description: AES hardware accelerator clock enable during Sleep mode
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name: AESSMEN
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- bit_offset: 18
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bit_size: 1
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description: Random number generator clock enable during Sleep mode
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name: RNGSMEN
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fieldset/APBENR1:
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description: APB peripheral clock enable register 1
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fields:
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- bit_offset: 0
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bit_size: 1
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description: TIM2 timer clock enable
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name: TIM2EN
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- bit_offset: 1
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bit_size: 1
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description: TIM3 timer clock enable
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name: TIM3EN
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- bit_offset: 4
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bit_size: 1
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description: TIM6 timer clock enable
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name: TIM6EN
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- bit_offset: 5
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bit_size: 1
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description: TIM7 timer clock enable
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name: TIM7EN
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- bit_offset: 10
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bit_size: 1
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description: RTC APB clock enable
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name: RTCAPBEN
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- bit_offset: 11
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bit_size: 1
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description: WWDG clock enable
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name: WWDGEN
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- bit_offset: 14
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bit_size: 1
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description: SPI2 clock enable
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name: SPI2EN
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- bit_offset: 17
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bit_size: 1
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description: USART2 clock enable
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name: USART2EN
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- bit_offset: 18
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bit_size: 1
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description: USART3 clock enable
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name: USART3EN
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- bit_offset: 19
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bit_size: 1
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description: USART4 clock enable
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name: USART4EN
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- bit_offset: 20
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bit_size: 1
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description: LPUART1 clock enable
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name: LPUART1EN
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- bit_offset: 21
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bit_size: 1
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description: I2C1 clock enable
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name: I2C1EN
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- bit_offset: 22
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bit_size: 1
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description: I2C2 clock enable
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name: I2C2EN
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- bit_offset: 24
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bit_size: 1
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description: HDMI CEC clock enable
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name: CECEN
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- bit_offset: 25
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bit_size: 1
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description: UCPD1 clock enable
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name: UCPD1EN
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- bit_offset: 26
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bit_size: 1
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description: UCPD2 clock enable
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name: UCPD2EN
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- bit_offset: 27
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bit_size: 1
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description: Debug support clock enable
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name: DBGEN
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- bit_offset: 28
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bit_size: 1
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description: Power interface clock enable
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name: PWREN
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- bit_offset: 29
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bit_size: 1
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description: DAC1 interface clock enable
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name: DAC1EN
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- bit_offset: 30
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bit_size: 1
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description: LPTIM2 clock enable
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name: LPTIM2EN
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- bit_offset: 31
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bit_size: 1
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description: LPTIM1 clock enable
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name: LPTIM1EN
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fieldset/APBENR2:
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description: APB peripheral clock enable register 2
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fields:
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- bit_offset: 0
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bit_size: 1
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description: SYSCFG, COMP and VREFBUF clock enable
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name: SYSCFGEN
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- bit_offset: 11
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bit_size: 1
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description: TIM1 timer clock enable
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name: TIM1EN
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- bit_offset: 12
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bit_size: 1
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description: SPI1 clock enable
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name: SPI1EN
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- bit_offset: 14
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bit_size: 1
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description: USART1 clock enable
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name: USART1EN
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- bit_offset: 15
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bit_size: 1
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description: TIM14 timer clock enable
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name: TIM14EN
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- bit_offset: 16
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bit_size: 1
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description: TIM15 timer clock enable
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name: TIM15EN
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- bit_offset: 17
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bit_size: 1
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description: TIM16 timer clock enable
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name: TIM16EN
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- bit_offset: 18
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bit_size: 1
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description: TIM16 timer clock enable
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name: TIM17EN
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- bit_offset: 20
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bit_size: 1
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description: ADC clock enable
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name: ADCEN
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fieldset/APBRSTR1:
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description: APB peripheral reset register 1
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fields:
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- bit_offset: 0
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bit_size: 1
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description: TIM2 timer reset
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name: TIM2RST
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- bit_offset: 1
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bit_size: 1
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description: TIM3 timer reset
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name: TIM3RST
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- bit_offset: 4
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bit_size: 1
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description: TIM6 timer reset
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name: TIM6RST
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- bit_offset: 5
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bit_size: 1
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description: TIM7 timer reset
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name: TIM7RST
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- bit_offset: 14
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bit_size: 1
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description: SPI2 reset
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name: SPI2RST
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- bit_offset: 17
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bit_size: 1
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description: USART2 reset
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name: USART2RST
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- bit_offset: 18
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bit_size: 1
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description: USART3 reset
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name: USART3RST
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- bit_offset: 19
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bit_size: 1
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description: USART4 reset
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name: USART4RST
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- bit_offset: 20
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bit_size: 1
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description: LPUART1 reset
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name: LPUART1RST
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- bit_offset: 21
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bit_size: 1
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description: I2C1 reset
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name: I2C1RST
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- bit_offset: 22
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bit_size: 1
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description: I2C2 reset
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name: I2C2RST
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- bit_offset: 24
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bit_size: 1
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description: HDMI CEC reset
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name: CECRST
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- bit_offset: 25
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bit_size: 1
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description: UCPD1 reset
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name: UCPD1RST
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- bit_offset: 26
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bit_size: 1
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description: UCPD2 reset
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name: UCPD2RST
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- bit_offset: 27
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bit_size: 1
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description: Debug support reset
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name: DBGRST
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- bit_offset: 28
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bit_size: 1
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description: Power interface reset
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name: PWRRST
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- bit_offset: 29
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bit_size: 1
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description: DAC1 interface reset
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name: DAC1RST
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- bit_offset: 30
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bit_size: 1
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description: Low Power Timer 2 reset
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name: LPTIM2RST
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- bit_offset: 31
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bit_size: 1
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description: Low Power Timer 1 reset
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name: LPTIM1RST
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fieldset/APBRSTR2:
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description: APB peripheral reset register 2
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fields:
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- bit_offset: 0
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bit_size: 1
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description: SYSCFG, COMP and VREFBUF reset
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name: SYSCFGRST
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- bit_offset: 11
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bit_size: 1
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description: TIM1 timer reset
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name: TIM1RST
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- bit_offset: 12
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bit_size: 1
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description: SPI1 reset
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name: SPI1RST
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- bit_offset: 14
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bit_size: 1
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description: USART1 reset
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name: USART1RST
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- bit_offset: 15
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bit_size: 1
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description: TIM14 timer reset
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name: TIM14RST
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- bit_offset: 16
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bit_size: 1
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description: TIM15 timer reset
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name: TIM15RST
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- bit_offset: 17
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bit_size: 1
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description: TIM16 timer reset
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name: TIM16RST
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- bit_offset: 18
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bit_size: 1
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description: TIM17 timer reset
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name: TIM17RST
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- bit_offset: 20
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bit_size: 1
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description: ADC reset
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name: ADCRST
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fieldset/APBSMENR1:
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description: APB peripheral clock enable in Sleep mode register 1
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fields:
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- bit_offset: 0
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bit_size: 1
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description: TIM2 timer clock enable during Sleep mode
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name: TIM2SMEN
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- bit_offset: 1
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bit_size: 1
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description: TIM3 timer clock enable during Sleep mode
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name: TIM3SMEN
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- bit_offset: 4
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bit_size: 1
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description: TIM6 timer clock enable during Sleep mode
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||||||
|
name: TIM6SMEN
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM7 timer clock enable during Sleep mode
|
||||||
|
name: TIM7SMEN
|
||||||
|
- bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
description: RTC APB clock enable during Sleep mode
|
||||||
|
name: RTCAPBSMEN
|
||||||
|
- bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
description: WWDG clock enable during Sleep mode
|
||||||
|
name: WWDGSMEN
|
||||||
|
- bit_offset: 14
|
||||||
|
bit_size: 1
|
||||||
|
description: SPI2 clock enable during Sleep mode
|
||||||
|
name: SPI2SMEN
|
||||||
|
- bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
description: USART2 clock enable during Sleep mode
|
||||||
|
name: USART2SMEN
|
||||||
|
- bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
description: USART3 clock enable during Sleep mode
|
||||||
|
name: USART3SMEN
|
||||||
|
- bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
description: USART4 clock enable during Sleep mode
|
||||||
|
name: USART4SMEN
|
||||||
|
- bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
description: LPUART1 clock enable during Sleep mode
|
||||||
|
name: LPUART1SMEN
|
||||||
|
- bit_offset: 21
|
||||||
|
bit_size: 1
|
||||||
|
description: I2C1 clock enable during Sleep mode
|
||||||
|
name: I2C1SMEN
|
||||||
|
- bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
description: I2C2 clock enable during Sleep mode
|
||||||
|
name: I2C2SMEN
|
||||||
|
- bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
description: HDMI CEC clock enable during Sleep mode
|
||||||
|
name: CECSMEN
|
||||||
|
- bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
description: UCPD1 clock enable during Sleep mode
|
||||||
|
name: UCPD1SMEN
|
||||||
|
- bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
description: UCPD2 clock enable during Sleep mode
|
||||||
|
name: UCPD2SMEN
|
||||||
|
- bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
description: Debug support clock enable during Sleep mode
|
||||||
|
name: DBGSMEN
|
||||||
|
- bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
description: Power interface clock enable during Sleep mode
|
||||||
|
name: PWRSMEN
|
||||||
|
- bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
description: DAC1 interface clock enable during Sleep mode
|
||||||
|
name: DAC1SMEN
|
||||||
|
- bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
description: Low Power Timer 2 clock enable during Sleep mode
|
||||||
|
name: LPTIM2SMEN
|
||||||
|
- bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
description: Low Power Timer 1 clock enable during Sleep mode
|
||||||
|
name: LPTIM1SMEN
|
||||||
|
fieldset/APBSMENR2:
|
||||||
|
description: APB peripheral clock enable in Sleep mode register 2
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: SYSCFG, COMP and VREFBUF clock enable during Sleep mode
|
||||||
|
name: SYSCFGSMEN
|
||||||
|
- bit_offset: 11
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM1 timer clock enable during Sleep mode
|
||||||
|
name: TIM1SMEN
|
||||||
|
- bit_offset: 12
|
||||||
|
bit_size: 1
|
||||||
|
description: SPI1 clock enable during Sleep mode
|
||||||
|
name: SPI1SMEN
|
||||||
|
- bit_offset: 14
|
||||||
|
bit_size: 1
|
||||||
|
description: USART1 clock enable during Sleep mode
|
||||||
|
name: USART1SMEN
|
||||||
|
- bit_offset: 15
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM14 timer clock enable during Sleep mode
|
||||||
|
name: TIM14SMEN
|
||||||
|
- bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM15 timer clock enable during Sleep mode
|
||||||
|
name: TIM15SMEN
|
||||||
|
- bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM16 timer clock enable during Sleep mode
|
||||||
|
name: TIM16SMEN
|
||||||
|
- bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM16 timer clock enable during Sleep mode
|
||||||
|
name: TIM17SMEN
|
||||||
|
- bit_offset: 20
|
||||||
|
bit_size: 1
|
||||||
|
description: ADC clock enable during Sleep mode
|
||||||
|
name: ADCSMEN
|
||||||
|
fieldset/BDCR:
|
||||||
|
description: RTC domain control register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE oscillator enable
|
||||||
|
name: LSEON
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE oscillator ready
|
||||||
|
name: LSERDY
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE oscillator bypass
|
||||||
|
name: LSEBYP
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 2
|
||||||
|
description: LSE oscillator drive capability
|
||||||
|
name: LSEDRV
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: CSS on LSE enable
|
||||||
|
name: LSECSSON
|
||||||
|
- bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
description: CSS on LSE failure Detection
|
||||||
|
name: LSECSSD
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 2
|
||||||
|
description: RTC clock source selection
|
||||||
|
name: RTCSEL
|
||||||
|
- bit_offset: 15
|
||||||
|
bit_size: 1
|
||||||
|
description: RTC clock enable
|
||||||
|
name: RTCEN
|
||||||
|
- bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
description: RTC domain software reset
|
||||||
|
name: BDRST
|
||||||
|
- bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
description: Low-speed clock output (LSCO) enable
|
||||||
|
name: LSCOEN
|
||||||
|
- bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
description: Low-speed clock output selection
|
||||||
|
name: LSCOSEL
|
||||||
|
fieldset/CCIPR:
|
||||||
|
description: Peripherals independent clock configuration register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 2
|
||||||
|
description: USART1 clock source selection
|
||||||
|
name: USART1SEL
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 2
|
||||||
|
description: USART2 clock source selection
|
||||||
|
name: USART2SEL
|
||||||
|
- bit_offset: 6
|
||||||
|
bit_size: 1
|
||||||
|
description: HDMI CEC clock source selection
|
||||||
|
name: CECSEL
|
||||||
|
- bit_offset: 10
|
||||||
|
bit_size: 2
|
||||||
|
description: LPUART1 clock source selection
|
||||||
|
name: LPUART1SEL
|
||||||
|
- bit_offset: 12
|
||||||
|
bit_size: 2
|
||||||
|
description: I2C1 clock source selection
|
||||||
|
name: I2C1SEL
|
||||||
|
- bit_offset: 14
|
||||||
|
bit_size: 2
|
||||||
|
description: I2S1 clock source selection
|
||||||
|
name: I2S2SEL
|
||||||
|
- bit_offset: 18
|
||||||
|
bit_size: 2
|
||||||
|
description: LPTIM1 clock source selection
|
||||||
|
name: LPTIM1SEL
|
||||||
|
- bit_offset: 20
|
||||||
|
bit_size: 2
|
||||||
|
description: LPTIM2 clock source selection
|
||||||
|
name: LPTIM2SEL
|
||||||
|
- bit_offset: 22
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM1 clock source selection
|
||||||
|
name: TIM1SEL
|
||||||
|
- bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
description: TIM15 clock source selection
|
||||||
|
name: TIM15SEL
|
||||||
|
- bit_offset: 26
|
||||||
|
bit_size: 2
|
||||||
|
description: RNG clock source selection
|
||||||
|
name: RNGSEL
|
||||||
|
- bit_offset: 28
|
||||||
|
bit_size: 2
|
||||||
|
description: Division factor of RNG clock divider
|
||||||
|
name: RNGDIV
|
||||||
|
- bit_offset: 30
|
||||||
|
bit_size: 2
|
||||||
|
description: ADCs clock source selection
|
||||||
|
name: ADCSEL
|
||||||
|
fieldset/CFGR:
|
||||||
|
description: Clock configuration register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 3
|
||||||
|
description: System clock switch
|
||||||
|
name: SW
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 3
|
||||||
|
description: System clock switch status
|
||||||
|
name: SWS
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 4
|
||||||
|
description: AHB prescaler
|
||||||
|
name: HPRE
|
||||||
|
- bit_offset: 12
|
||||||
|
bit_size: 3
|
||||||
|
description: APB prescaler
|
||||||
|
name: PPRE
|
||||||
|
- bit_offset: 24
|
||||||
|
bit_size: 3
|
||||||
|
description: Microcontroller clock output
|
||||||
|
name: MCOSEL
|
||||||
|
- bit_offset: 28
|
||||||
|
bit_size: 3
|
||||||
|
description: Microcontroller clock output prescaler
|
||||||
|
name: MCOPRE
|
||||||
|
fieldset/CICR:
|
||||||
|
description: Clock interrupt clear register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: LSI ready interrupt clear
|
||||||
|
name: LSIRDYC
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE ready interrupt clear
|
||||||
|
name: LSERDYC
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: HSI ready interrupt clear
|
||||||
|
name: HSIRDYC
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
description: HSE ready interrupt clear
|
||||||
|
name: HSERDYC
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: PLL ready interrupt clear
|
||||||
|
name: PLLSYSRDYC
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
description: Clock security system interrupt clear
|
||||||
|
name: CSSC
|
||||||
|
- bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE Clock security system interrupt clear
|
||||||
|
name: LSECSSC
|
||||||
|
fieldset/CIER:
|
||||||
|
description: Clock interrupt enable register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: LSI ready interrupt enable
|
||||||
|
name: LSIRDYIE
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE ready interrupt enable
|
||||||
|
name: LSERDYIE
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: HSI ready interrupt enable
|
||||||
|
name: HSIRDYIE
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
description: HSE ready interrupt enable
|
||||||
|
name: HSERDYIE
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: PLL ready interrupt enable
|
||||||
|
name: PLLSYSRDYIE
|
||||||
|
fieldset/CIFR:
|
||||||
|
description: Clock interrupt flag register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: LSI ready interrupt flag
|
||||||
|
name: LSIRDYF
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE ready interrupt flag
|
||||||
|
name: LSERDYF
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: HSI ready interrupt flag
|
||||||
|
name: HSIRDYF
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 1
|
||||||
|
description: HSE ready interrupt flag
|
||||||
|
name: HSERDYF
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: PLL ready interrupt flag
|
||||||
|
name: PLLSYSRDYF
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
description: Clock security system interrupt flag
|
||||||
|
name: CSSF
|
||||||
|
- bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
description: LSE Clock security system interrupt flag
|
||||||
|
name: LSECSSF
|
||||||
|
fieldset/CR:
|
||||||
|
description: Clock control register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 1
|
||||||
|
description: HSI16 clock enable
|
||||||
|
name: HSION
|
||||||
|
- bit_offset: 9
|
||||||
|
bit_size: 1
|
||||||
|
description: HSI16 always enable for peripheral kernels
|
||||||
|
name: HSIKERON
|
||||||
|
- bit_offset: 10
|
||||||
|
bit_size: 1
|
||||||
|
description: HSI16 clock ready flag
|
||||||
|
name: HSIRDY
|
||||||
|
- bit_offset: 11
|
||||||
|
bit_size: 3
|
||||||
|
description: HSI16 clock division factor
|
||||||
|
name: HSIDIV
|
||||||
|
- bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
description: HSE clock enable
|
||||||
|
name: HSEON
|
||||||
|
- bit_offset: 17
|
||||||
|
bit_size: 1
|
||||||
|
description: HSE clock ready flag
|
||||||
|
name: HSERDY
|
||||||
|
- bit_offset: 18
|
||||||
|
bit_size: 1
|
||||||
|
description: HSE crystal oscillator bypass
|
||||||
|
name: HSEBYP
|
||||||
|
- bit_offset: 19
|
||||||
|
bit_size: 1
|
||||||
|
description: Clock security system enable
|
||||||
|
name: CSSON
|
||||||
|
- bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
description: PLL enable
|
||||||
|
name: PLLON
|
||||||
|
- bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
description: PLL clock ready flag
|
||||||
|
name: PLLRDY
|
||||||
|
fieldset/CSR:
|
||||||
|
description: Control/status register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: LSI oscillator enable
|
||||||
|
name: LSION
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: LSI oscillator ready
|
||||||
|
name: LSIRDY
|
||||||
|
- bit_offset: 23
|
||||||
|
bit_size: 1
|
||||||
|
description: Remove reset flags
|
||||||
|
name: RMVF
|
||||||
|
- bit_offset: 25
|
||||||
|
bit_size: 1
|
||||||
|
description: Option byte loader reset flag
|
||||||
|
name: OBLRSTF
|
||||||
|
- bit_offset: 26
|
||||||
|
bit_size: 1
|
||||||
|
description: Pin reset flag
|
||||||
|
name: PINRSTF
|
||||||
|
- bit_offset: 27
|
||||||
|
bit_size: 1
|
||||||
|
description: BOR or POR/PDR flag
|
||||||
|
name: PWRRSTF
|
||||||
|
- bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
description: Software reset flag
|
||||||
|
name: SFTRSTF
|
||||||
|
- bit_offset: 29
|
||||||
|
bit_size: 1
|
||||||
|
description: Independent window watchdog reset flag
|
||||||
|
name: IWDGRSTF
|
||||||
|
- bit_offset: 30
|
||||||
|
bit_size: 1
|
||||||
|
description: Window watchdog reset flag
|
||||||
|
name: WWDGRSTF
|
||||||
|
- bit_offset: 31
|
||||||
|
bit_size: 1
|
||||||
|
description: Low-power reset flag
|
||||||
|
name: LPWRRSTF
|
||||||
|
fieldset/ICSCR:
|
||||||
|
description: Internal clock sources calibration register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 8
|
||||||
|
description: HSI16 clock calibration
|
||||||
|
name: HSICAL
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 7
|
||||||
|
description: HSI16 clock trimming
|
||||||
|
name: HSITRIM
|
||||||
|
fieldset/IOPENR:
|
||||||
|
description: GPIO clock enable register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port A clock enable
|
||||||
|
name: IOPAEN
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port B clock enable
|
||||||
|
name: IOPBEN
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port C clock enable
|
||||||
|
name: IOPCEN
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port D clock enable
|
||||||
|
name: IOPDEN
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port F clock enable
|
||||||
|
name: IOPFEN
|
||||||
|
fieldset/IOPRSTR:
|
||||||
|
description: GPIO reset register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port A reset
|
||||||
|
name: IOPARST
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port B reset
|
||||||
|
name: IOPBRST
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port C reset
|
||||||
|
name: IOPCRST
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port D reset
|
||||||
|
name: IOPDRST
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port F reset
|
||||||
|
name: IOPFRST
|
||||||
|
fieldset/IOPSMENR:
|
||||||
|
description: GPIO in Sleep mode clock enable register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port A clock enable during Sleep mode
|
||||||
|
name: IOPASMEN
|
||||||
|
- bit_offset: 1
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port B clock enable during Sleep mode
|
||||||
|
name: IOPBSMEN
|
||||||
|
- bit_offset: 2
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port C clock enable during Sleep mode
|
||||||
|
name: IOPCSMEN
|
||||||
|
- bit_offset: 3
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port D clock enable during Sleep mode
|
||||||
|
name: IOPDSMEN
|
||||||
|
- bit_offset: 5
|
||||||
|
bit_size: 1
|
||||||
|
description: I/O port F clock enable during Sleep mode
|
||||||
|
name: IOPFSMEN
|
||||||
|
fieldset/PLLSYSCFGR:
|
||||||
|
description: PLL configuration register
|
||||||
|
fields:
|
||||||
|
- bit_offset: 0
|
||||||
|
bit_size: 2
|
||||||
|
description: PLL input clock source
|
||||||
|
name: PLLSRC
|
||||||
|
- bit_offset: 4
|
||||||
|
bit_size: 3
|
||||||
|
description: Division factor M of the PLL input clock divider
|
||||||
|
name: PLLM
|
||||||
|
- bit_offset: 8
|
||||||
|
bit_size: 7
|
||||||
|
description: PLL frequency multiplication factor N
|
||||||
|
name: PLLN
|
||||||
|
- bit_offset: 16
|
||||||
|
bit_size: 1
|
||||||
|
description: PLLPCLK clock output enable
|
||||||
|
name: PLLPEN
|
||||||
|
- bit_offset: 17
|
||||||
|
bit_size: 5
|
||||||
|
description: PLL VCO division factor P for PLLPCLK clock output
|
||||||
|
name: PLLP
|
||||||
|
- bit_offset: 24
|
||||||
|
bit_size: 1
|
||||||
|
description: PLLQCLK clock output enable
|
||||||
|
name: PLLQEN
|
||||||
|
- bit_offset: 25
|
||||||
|
bit_size: 3
|
||||||
|
description: PLL VCO division factor Q for PLLQCLK clock output
|
||||||
|
name: PLLQ
|
||||||
|
- bit_offset: 28
|
||||||
|
bit_size: 1
|
||||||
|
description: PLLRCLK clock output enable
|
||||||
|
name: PLLREN
|
||||||
|
- bit_offset: 29
|
||||||
|
bit_size: 3
|
||||||
|
description: PLL VCO division factor R for PLLRCLK clock output
|
||||||
|
name: PLLR
|
||||||
1
parse.py
1
parse.py
@ -357,6 +357,7 @@ perimap = [
|
|||||||
('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),
|
('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),
|
||||||
('STM32F0.*:RCC:.*', 'rcc_f0/RCC'),
|
('STM32F0.*:RCC:.*', 'rcc_f0/RCC'),
|
||||||
('STM32F1.*:RCC:.*', 'rcc_f1/RCC'),
|
('STM32F1.*:RCC:.*', 'rcc_f1/RCC'),
|
||||||
|
('STM32G0.*:RCC:.*', 'rcc_g0/RCC'),
|
||||||
('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
|
('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
|
||||||
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
|
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
|
||||||
('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
|
('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user