diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml
new file mode 100644
index 0000000..b8dc8e0
--- /dev/null
+++ b/data/registers/rcc_g0.yaml
@@ -0,0 +1,955 @@
+block/RCC:
+  description: Reset and clock control
+  items:
+  - byte_offset: 0
+    description: Clock control register
+    fieldset: CR
+    name: CR
+  - byte_offset: 4
+    description: Internal clock sources calibration register
+    fieldset: ICSCR
+    name: ICSCR
+  - byte_offset: 8
+    description: Clock configuration register
+    fieldset: CFGR
+    name: CFGR
+  - byte_offset: 12
+    description: PLL configuration register
+    fieldset: PLLSYSCFGR
+    name: PLLSYSCFGR
+  - byte_offset: 24
+    description: Clock interrupt enable register
+    fieldset: CIER
+    name: CIER
+  - access: Read
+    byte_offset: 28
+    description: Clock interrupt flag register
+    fieldset: CIFR
+    name: CIFR
+  - access: Write
+    byte_offset: 32
+    description: Clock interrupt clear register
+    fieldset: CICR
+    name: CICR
+  - byte_offset: 36
+    description: GPIO reset register
+    fieldset: IOPRSTR
+    name: IOPRSTR
+  - byte_offset: 40
+    description: AHB peripheral reset register
+    fieldset: AHBRSTR
+    name: AHBRSTR
+  - byte_offset: 44
+    description: APB peripheral reset register 1
+    fieldset: APBRSTR1
+    name: APBRSTR1
+  - byte_offset: 48
+    description: APB peripheral reset register 2
+    fieldset: APBRSTR2
+    name: APBRSTR2
+  - byte_offset: 52
+    description: GPIO clock enable register
+    fieldset: IOPENR
+    name: IOPENR
+  - byte_offset: 56
+    description: AHB peripheral clock enable register
+    fieldset: AHBENR
+    name: AHBENR
+  - byte_offset: 60
+    description: APB peripheral clock enable register 1
+    fieldset: APBENR1
+    name: APBENR1
+  - byte_offset: 64
+    description: APB peripheral clock enable register 2
+    fieldset: APBENR2
+    name: APBENR2
+  - byte_offset: 68
+    description: GPIO in Sleep mode clock enable register
+    fieldset: IOPSMENR
+    name: IOPSMENR
+  - byte_offset: 72
+    description: AHB peripheral clock enable in Sleep mode register
+    fieldset: AHBSMENR
+    name: AHBSMENR
+  - byte_offset: 76
+    description: APB peripheral clock enable in Sleep mode register 1
+    fieldset: APBSMENR1
+    name: APBSMENR1
+  - byte_offset: 80
+    description: APB peripheral clock enable in Sleep mode register 2
+    fieldset: APBSMENR2
+    name: APBSMENR2
+  - byte_offset: 84
+    description: Peripherals independent clock configuration register
+    fieldset: CCIPR
+    name: CCIPR
+  - byte_offset: 92
+    description: RTC domain control register
+    fieldset: BDCR
+    name: BDCR
+  - byte_offset: 96
+    description: Control/status register
+    fieldset: CSR
+    name: CSR
+fieldset/AHBENR:
+  description: AHB peripheral clock enable register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: DMA clock enable
+    name: DMAEN
+  - bit_offset: 8
+    bit_size: 1
+    description: Flash memory interface clock enable
+    name: FLASHEN
+  - bit_offset: 12
+    bit_size: 1
+    description: CRC clock enable
+    name: CRCEN
+  - bit_offset: 16
+    bit_size: 1
+    description: AES hardware accelerator
+    name: AESEN
+  - bit_offset: 18
+    bit_size: 1
+    description: Random number generator clock enable
+    name: RNGEN
+fieldset/AHBRSTR:
+  description: AHB peripheral reset register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: DMA1 reset
+    name: DMARST
+  - bit_offset: 8
+    bit_size: 1
+    description: FLITF reset
+    name: FLASHRST
+  - bit_offset: 12
+    bit_size: 1
+    description: CRC reset
+    name: CRCRST
+  - bit_offset: 16
+    bit_size: 1
+    description: AES hardware accelerator reset
+    name: AESRST
+  - bit_offset: 18
+    bit_size: 1
+    description: Random number generator reset
+    name: RNGRST
+fieldset/AHBSMENR:
+  description: AHB peripheral clock enable in Sleep mode register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: DMA clock enable during Sleep mode
+    name: DMASMEN
+  - bit_offset: 8
+    bit_size: 1
+    description: Flash memory interface clock enable during Sleep mode
+    name: FLASHSMEN
+  - bit_offset: 9
+    bit_size: 1
+    description: SRAM clock enable during Sleep mode
+    name: SRAMSMEN
+  - bit_offset: 12
+    bit_size: 1
+    description: CRC clock enable during Sleep mode
+    name: CRCSMEN
+  - bit_offset: 16
+    bit_size: 1
+    description: AES hardware accelerator clock enable during Sleep mode
+    name: AESSMEN
+  - bit_offset: 18
+    bit_size: 1
+    description: Random number generator clock enable during Sleep mode
+    name: RNGSMEN
+fieldset/APBENR1:
+  description: APB peripheral clock enable register 1
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: TIM2 timer clock enable
+    name: TIM2EN
+  - bit_offset: 1
+    bit_size: 1
+    description: TIM3 timer clock enable
+    name: TIM3EN
+  - bit_offset: 4
+    bit_size: 1
+    description: TIM6 timer clock enable
+    name: TIM6EN
+  - bit_offset: 5
+    bit_size: 1
+    description: TIM7 timer clock enable
+    name: TIM7EN
+  - bit_offset: 10
+    bit_size: 1
+    description: RTC APB clock enable
+    name: RTCAPBEN
+  - bit_offset: 11
+    bit_size: 1
+    description: WWDG clock enable
+    name: WWDGEN
+  - bit_offset: 14
+    bit_size: 1
+    description: SPI2 clock enable
+    name: SPI2EN
+  - bit_offset: 17
+    bit_size: 1
+    description: USART2 clock enable
+    name: USART2EN
+  - bit_offset: 18
+    bit_size: 1
+    description: USART3 clock enable
+    name: USART3EN
+  - bit_offset: 19
+    bit_size: 1
+    description: USART4 clock enable
+    name: USART4EN
+  - bit_offset: 20
+    bit_size: 1
+    description: LPUART1 clock enable
+    name: LPUART1EN
+  - bit_offset: 21
+    bit_size: 1
+    description: I2C1 clock enable
+    name: I2C1EN
+  - bit_offset: 22
+    bit_size: 1
+    description: I2C2 clock enable
+    name: I2C2EN
+  - bit_offset: 24
+    bit_size: 1
+    description: HDMI CEC clock enable
+    name: CECEN
+  - bit_offset: 25
+    bit_size: 1
+    description: UCPD1 clock enable
+    name: UCPD1EN
+  - bit_offset: 26
+    bit_size: 1
+    description: UCPD2 clock enable
+    name: UCPD2EN
+  - bit_offset: 27
+    bit_size: 1
+    description: Debug support clock enable
+    name: DBGEN
+  - bit_offset: 28
+    bit_size: 1
+    description: Power interface clock enable
+    name: PWREN
+  - bit_offset: 29
+    bit_size: 1
+    description: DAC1 interface clock enable
+    name: DAC1EN
+  - bit_offset: 30
+    bit_size: 1
+    description: LPTIM2 clock enable
+    name: LPTIM2EN
+  - bit_offset: 31
+    bit_size: 1
+    description: LPTIM1 clock enable
+    name: LPTIM1EN
+fieldset/APBENR2:
+  description: APB peripheral clock enable register 2
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: SYSCFG, COMP and VREFBUF clock enable
+    name: SYSCFGEN
+  - bit_offset: 11
+    bit_size: 1
+    description: TIM1 timer clock enable
+    name: TIM1EN
+  - bit_offset: 12
+    bit_size: 1
+    description: SPI1 clock enable
+    name: SPI1EN
+  - bit_offset: 14
+    bit_size: 1
+    description: USART1 clock enable
+    name: USART1EN
+  - bit_offset: 15
+    bit_size: 1
+    description: TIM14 timer clock enable
+    name: TIM14EN
+  - bit_offset: 16
+    bit_size: 1
+    description: TIM15 timer clock enable
+    name: TIM15EN
+  - bit_offset: 17
+    bit_size: 1
+    description: TIM16 timer clock enable
+    name: TIM16EN
+  - bit_offset: 18
+    bit_size: 1
+    description: TIM16 timer clock enable
+    name: TIM17EN
+  - bit_offset: 20
+    bit_size: 1
+    description: ADC clock enable
+    name: ADCEN
+fieldset/APBRSTR1:
+  description: APB peripheral reset register 1
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: TIM2 timer reset
+    name: TIM2RST
+  - bit_offset: 1
+    bit_size: 1
+    description: TIM3 timer reset
+    name: TIM3RST
+  - bit_offset: 4
+    bit_size: 1
+    description: TIM6 timer reset
+    name: TIM6RST
+  - bit_offset: 5
+    bit_size: 1
+    description: TIM7 timer reset
+    name: TIM7RST
+  - bit_offset: 14
+    bit_size: 1
+    description: SPI2 reset
+    name: SPI2RST
+  - bit_offset: 17
+    bit_size: 1
+    description: USART2 reset
+    name: USART2RST
+  - bit_offset: 18
+    bit_size: 1
+    description: USART3 reset
+    name: USART3RST
+  - bit_offset: 19
+    bit_size: 1
+    description: USART4 reset
+    name: USART4RST
+  - bit_offset: 20
+    bit_size: 1
+    description: LPUART1 reset
+    name: LPUART1RST
+  - bit_offset: 21
+    bit_size: 1
+    description: I2C1 reset
+    name: I2C1RST
+  - bit_offset: 22
+    bit_size: 1
+    description: I2C2 reset
+    name: I2C2RST
+  - bit_offset: 24
+    bit_size: 1
+    description: HDMI CEC reset
+    name: CECRST
+  - bit_offset: 25
+    bit_size: 1
+    description: UCPD1 reset
+    name: UCPD1RST
+  - bit_offset: 26
+    bit_size: 1
+    description: UCPD2 reset
+    name: UCPD2RST
+  - bit_offset: 27
+    bit_size: 1
+    description: Debug support reset
+    name: DBGRST
+  - bit_offset: 28
+    bit_size: 1
+    description: Power interface reset
+    name: PWRRST
+  - bit_offset: 29
+    bit_size: 1
+    description: DAC1 interface reset
+    name: DAC1RST
+  - bit_offset: 30
+    bit_size: 1
+    description: Low Power Timer 2 reset
+    name: LPTIM2RST
+  - bit_offset: 31
+    bit_size: 1
+    description: Low Power Timer 1 reset
+    name: LPTIM1RST
+fieldset/APBRSTR2:
+  description: APB peripheral reset register 2
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: SYSCFG, COMP and VREFBUF reset
+    name: SYSCFGRST
+  - bit_offset: 11
+    bit_size: 1
+    description: TIM1 timer reset
+    name: TIM1RST
+  - bit_offset: 12
+    bit_size: 1
+    description: SPI1 reset
+    name: SPI1RST
+  - bit_offset: 14
+    bit_size: 1
+    description: USART1 reset
+    name: USART1RST
+  - bit_offset: 15
+    bit_size: 1
+    description: TIM14 timer reset
+    name: TIM14RST
+  - bit_offset: 16
+    bit_size: 1
+    description: TIM15 timer reset
+    name: TIM15RST
+  - bit_offset: 17
+    bit_size: 1
+    description: TIM16 timer reset
+    name: TIM16RST
+  - bit_offset: 18
+    bit_size: 1
+    description: TIM17 timer reset
+    name: TIM17RST
+  - bit_offset: 20
+    bit_size: 1
+    description: ADC reset
+    name: ADCRST
+fieldset/APBSMENR1:
+  description: APB peripheral clock enable in Sleep mode register 1
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: TIM2 timer clock enable during Sleep mode
+    name: TIM2SMEN
+  - bit_offset: 1
+    bit_size: 1
+    description: TIM3 timer clock enable during Sleep mode
+    name: TIM3SMEN
+  - bit_offset: 4
+    bit_size: 1
+    description: TIM6 timer clock enable during Sleep mode
+    name: TIM6SMEN
+  - bit_offset: 5
+    bit_size: 1
+    description: TIM7 timer clock enable during Sleep mode
+    name: TIM7SMEN
+  - bit_offset: 10
+    bit_size: 1
+    description: RTC APB clock enable during Sleep mode
+    name: RTCAPBSMEN
+  - bit_offset: 11
+    bit_size: 1
+    description: WWDG clock enable during Sleep mode
+    name: WWDGSMEN
+  - bit_offset: 14
+    bit_size: 1
+    description: SPI2 clock enable during Sleep mode
+    name: SPI2SMEN
+  - bit_offset: 17
+    bit_size: 1
+    description: USART2 clock enable during Sleep mode
+    name: USART2SMEN
+  - bit_offset: 18
+    bit_size: 1
+    description: USART3 clock enable during Sleep mode
+    name: USART3SMEN
+  - bit_offset: 19
+    bit_size: 1
+    description: USART4 clock enable during Sleep mode
+    name: USART4SMEN
+  - bit_offset: 20
+    bit_size: 1
+    description: LPUART1 clock enable during Sleep mode
+    name: LPUART1SMEN
+  - bit_offset: 21
+    bit_size: 1
+    description: I2C1 clock enable during Sleep mode
+    name: I2C1SMEN
+  - bit_offset: 22
+    bit_size: 1
+    description: I2C2 clock enable during Sleep mode
+    name: I2C2SMEN
+  - bit_offset: 24
+    bit_size: 1
+    description: HDMI CEC clock enable during Sleep mode
+    name: CECSMEN
+  - bit_offset: 25
+    bit_size: 1
+    description: UCPD1 clock enable during Sleep mode
+    name: UCPD1SMEN
+  - bit_offset: 26
+    bit_size: 1
+    description: UCPD2 clock enable during Sleep mode
+    name: UCPD2SMEN
+  - bit_offset: 27
+    bit_size: 1
+    description: Debug support clock enable during Sleep mode
+    name: DBGSMEN
+  - bit_offset: 28
+    bit_size: 1
+    description: Power interface clock enable during Sleep mode
+    name: PWRSMEN
+  - bit_offset: 29
+    bit_size: 1
+    description: DAC1 interface clock enable during Sleep mode
+    name: DAC1SMEN
+  - bit_offset: 30
+    bit_size: 1
+    description: Low Power Timer 2 clock enable during Sleep mode
+    name: LPTIM2SMEN
+  - bit_offset: 31
+    bit_size: 1
+    description: Low Power Timer 1 clock enable during Sleep mode
+    name: LPTIM1SMEN
+fieldset/APBSMENR2:
+  description: APB peripheral clock enable in Sleep mode register 2
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: SYSCFG, COMP and VREFBUF clock enable during Sleep mode
+    name: SYSCFGSMEN
+  - bit_offset: 11
+    bit_size: 1
+    description: TIM1 timer clock enable during Sleep mode
+    name: TIM1SMEN
+  - bit_offset: 12
+    bit_size: 1
+    description: SPI1 clock enable during Sleep mode
+    name: SPI1SMEN
+  - bit_offset: 14
+    bit_size: 1
+    description: USART1 clock enable during Sleep mode
+    name: USART1SMEN
+  - bit_offset: 15
+    bit_size: 1
+    description: TIM14 timer clock enable during Sleep mode
+    name: TIM14SMEN
+  - bit_offset: 16
+    bit_size: 1
+    description: TIM15 timer clock enable during Sleep mode
+    name: TIM15SMEN
+  - bit_offset: 17
+    bit_size: 1
+    description: TIM16 timer clock enable during Sleep mode
+    name: TIM16SMEN
+  - bit_offset: 18
+    bit_size: 1
+    description: TIM16 timer clock enable during Sleep mode
+    name: TIM17SMEN
+  - bit_offset: 20
+    bit_size: 1
+    description: ADC clock enable during Sleep mode
+    name: ADCSMEN
+fieldset/BDCR:
+  description: RTC domain control register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: LSE oscillator enable
+    name: LSEON
+  - bit_offset: 1
+    bit_size: 1
+    description: LSE oscillator ready
+    name: LSERDY
+  - bit_offset: 2
+    bit_size: 1
+    description: LSE oscillator bypass
+    name: LSEBYP
+  - bit_offset: 3
+    bit_size: 2
+    description: LSE oscillator drive capability
+    name: LSEDRV
+  - bit_offset: 5
+    bit_size: 1
+    description: CSS on LSE enable
+    name: LSECSSON
+  - bit_offset: 6
+    bit_size: 1
+    description: CSS on LSE failure Detection
+    name: LSECSSD
+  - bit_offset: 8
+    bit_size: 2
+    description: RTC clock source selection
+    name: RTCSEL
+  - bit_offset: 15
+    bit_size: 1
+    description: RTC clock enable
+    name: RTCEN
+  - bit_offset: 16
+    bit_size: 1
+    description: RTC domain software reset
+    name: BDRST
+  - bit_offset: 24
+    bit_size: 1
+    description: Low-speed clock output (LSCO) enable
+    name: LSCOEN
+  - bit_offset: 25
+    bit_size: 1
+    description: Low-speed clock output selection
+    name: LSCOSEL
+fieldset/CCIPR:
+  description: Peripherals independent clock configuration register
+  fields:
+  - bit_offset: 0
+    bit_size: 2
+    description: USART1 clock source selection
+    name: USART1SEL
+  - bit_offset: 2
+    bit_size: 2
+    description: USART2 clock source selection
+    name: USART2SEL
+  - bit_offset: 6
+    bit_size: 1
+    description: HDMI CEC clock source selection
+    name: CECSEL
+  - bit_offset: 10
+    bit_size: 2
+    description: LPUART1 clock source selection
+    name: LPUART1SEL
+  - bit_offset: 12
+    bit_size: 2
+    description: I2C1 clock source selection
+    name: I2C1SEL
+  - bit_offset: 14
+    bit_size: 2
+    description: I2S1 clock source selection
+    name: I2S2SEL
+  - bit_offset: 18
+    bit_size: 2
+    description: LPTIM1 clock source selection
+    name: LPTIM1SEL
+  - bit_offset: 20
+    bit_size: 2
+    description: LPTIM2 clock source selection
+    name: LPTIM2SEL
+  - bit_offset: 22
+    bit_size: 1
+    description: TIM1 clock source selection
+    name: TIM1SEL
+  - bit_offset: 24
+    bit_size: 1
+    description: TIM15 clock source selection
+    name: TIM15SEL
+  - bit_offset: 26
+    bit_size: 2
+    description: RNG clock source selection
+    name: RNGSEL
+  - bit_offset: 28
+    bit_size: 2
+    description: Division factor of RNG clock divider
+    name: RNGDIV
+  - bit_offset: 30
+    bit_size: 2
+    description: ADCs clock source selection
+    name: ADCSEL
+fieldset/CFGR:
+  description: Clock configuration register
+  fields:
+  - bit_offset: 0
+    bit_size: 3
+    description: System clock switch
+    name: SW
+  - bit_offset: 3
+    bit_size: 3
+    description: System clock switch status
+    name: SWS
+  - bit_offset: 8
+    bit_size: 4
+    description: AHB prescaler
+    name: HPRE
+  - bit_offset: 12
+    bit_size: 3
+    description: APB prescaler
+    name: PPRE
+  - bit_offset: 24
+    bit_size: 3
+    description: Microcontroller clock output
+    name: MCOSEL
+  - bit_offset: 28
+    bit_size: 3
+    description: Microcontroller clock output prescaler
+    name: MCOPRE
+fieldset/CICR:
+  description: Clock interrupt clear register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: LSI ready interrupt clear
+    name: LSIRDYC
+  - bit_offset: 1
+    bit_size: 1
+    description: LSE ready interrupt clear
+    name: LSERDYC
+  - bit_offset: 3
+    bit_size: 1
+    description: HSI ready interrupt clear
+    name: HSIRDYC
+  - bit_offset: 4
+    bit_size: 1
+    description: HSE ready interrupt clear
+    name: HSERDYC
+  - bit_offset: 5
+    bit_size: 1
+    description: PLL ready interrupt clear
+    name: PLLSYSRDYC
+  - bit_offset: 8
+    bit_size: 1
+    description: Clock security system interrupt clear
+    name: CSSC
+  - bit_offset: 9
+    bit_size: 1
+    description: LSE Clock security system interrupt clear
+    name: LSECSSC
+fieldset/CIER:
+  description: Clock interrupt enable register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: LSI ready interrupt enable
+    name: LSIRDYIE
+  - bit_offset: 1
+    bit_size: 1
+    description: LSE ready interrupt enable
+    name: LSERDYIE
+  - bit_offset: 3
+    bit_size: 1
+    description: HSI ready interrupt enable
+    name: HSIRDYIE
+  - bit_offset: 4
+    bit_size: 1
+    description: HSE ready interrupt enable
+    name: HSERDYIE
+  - bit_offset: 5
+    bit_size: 1
+    description: PLL ready interrupt enable
+    name: PLLSYSRDYIE
+fieldset/CIFR:
+  description: Clock interrupt flag register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: LSI ready interrupt flag
+    name: LSIRDYF
+  - bit_offset: 1
+    bit_size: 1
+    description: LSE ready interrupt flag
+    name: LSERDYF
+  - bit_offset: 3
+    bit_size: 1
+    description: HSI ready interrupt flag
+    name: HSIRDYF
+  - bit_offset: 4
+    bit_size: 1
+    description: HSE ready interrupt flag
+    name: HSERDYF
+  - bit_offset: 5
+    bit_size: 1
+    description: PLL ready interrupt flag
+    name: PLLSYSRDYF
+  - bit_offset: 8
+    bit_size: 1
+    description: Clock security system interrupt flag
+    name: CSSF
+  - bit_offset: 9
+    bit_size: 1
+    description: LSE Clock security system interrupt flag
+    name: LSECSSF
+fieldset/CR:
+  description: Clock control register
+  fields:
+  - bit_offset: 8
+    bit_size: 1
+    description: HSI16 clock enable
+    name: HSION
+  - bit_offset: 9
+    bit_size: 1
+    description: HSI16 always enable for peripheral kernels
+    name: HSIKERON
+  - bit_offset: 10
+    bit_size: 1
+    description: HSI16 clock ready flag
+    name: HSIRDY
+  - bit_offset: 11
+    bit_size: 3
+    description: HSI16 clock division factor
+    name: HSIDIV
+  - bit_offset: 16
+    bit_size: 1
+    description: HSE clock enable
+    name: HSEON
+  - bit_offset: 17
+    bit_size: 1
+    description: HSE clock ready flag
+    name: HSERDY
+  - bit_offset: 18
+    bit_size: 1
+    description: HSE crystal oscillator bypass
+    name: HSEBYP
+  - bit_offset: 19
+    bit_size: 1
+    description: Clock security system enable
+    name: CSSON
+  - bit_offset: 24
+    bit_size: 1
+    description: PLL enable
+    name: PLLON
+  - bit_offset: 25
+    bit_size: 1
+    description: PLL clock ready flag
+    name: PLLRDY
+fieldset/CSR:
+  description: Control/status register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: LSI oscillator enable
+    name: LSION
+  - bit_offset: 1
+    bit_size: 1
+    description: LSI oscillator ready
+    name: LSIRDY
+  - bit_offset: 23
+    bit_size: 1
+    description: Remove reset flags
+    name: RMVF
+  - bit_offset: 25
+    bit_size: 1
+    description: Option byte loader reset flag
+    name: OBLRSTF
+  - bit_offset: 26
+    bit_size: 1
+    description: Pin reset flag
+    name: PINRSTF
+  - bit_offset: 27
+    bit_size: 1
+    description: BOR or POR/PDR flag
+    name: PWRRSTF
+  - bit_offset: 28
+    bit_size: 1
+    description: Software reset flag
+    name: SFTRSTF
+  - bit_offset: 29
+    bit_size: 1
+    description: Independent window watchdog reset flag
+    name: IWDGRSTF
+  - bit_offset: 30
+    bit_size: 1
+    description: Window watchdog reset flag
+    name: WWDGRSTF
+  - bit_offset: 31
+    bit_size: 1
+    description: Low-power reset flag
+    name: LPWRRSTF
+fieldset/ICSCR:
+  description: Internal clock sources calibration register
+  fields:
+  - bit_offset: 0
+    bit_size: 8
+    description: HSI16 clock calibration
+    name: HSICAL
+  - bit_offset: 8
+    bit_size: 7
+    description: HSI16 clock trimming
+    name: HSITRIM
+fieldset/IOPENR:
+  description: GPIO clock enable register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: I/O port A clock enable
+    name: IOPAEN
+  - bit_offset: 1
+    bit_size: 1
+    description: I/O port B clock enable
+    name: IOPBEN
+  - bit_offset: 2
+    bit_size: 1
+    description: I/O port C clock enable
+    name: IOPCEN
+  - bit_offset: 3
+    bit_size: 1
+    description: I/O port D clock enable
+    name: IOPDEN
+  - bit_offset: 5
+    bit_size: 1
+    description: I/O port F clock enable
+    name: IOPFEN
+fieldset/IOPRSTR:
+  description: GPIO reset register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: I/O port A reset
+    name: IOPARST
+  - bit_offset: 1
+    bit_size: 1
+    description: I/O port B reset
+    name: IOPBRST
+  - bit_offset: 2
+    bit_size: 1
+    description: I/O port C reset
+    name: IOPCRST
+  - bit_offset: 3
+    bit_size: 1
+    description: I/O port D reset
+    name: IOPDRST
+  - bit_offset: 5
+    bit_size: 1
+    description: I/O port F reset
+    name: IOPFRST
+fieldset/IOPSMENR:
+  description: GPIO in Sleep mode clock enable register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: I/O port A clock enable during Sleep mode
+    name: IOPASMEN
+  - bit_offset: 1
+    bit_size: 1
+    description: I/O port B clock enable during Sleep mode
+    name: IOPBSMEN
+  - bit_offset: 2
+    bit_size: 1
+    description: I/O port C clock enable during Sleep mode
+    name: IOPCSMEN
+  - bit_offset: 3
+    bit_size: 1
+    description: I/O port D clock enable during Sleep mode
+    name: IOPDSMEN
+  - bit_offset: 5
+    bit_size: 1
+    description: I/O port F clock enable during Sleep mode
+    name: IOPFSMEN
+fieldset/PLLSYSCFGR:
+  description: PLL configuration register
+  fields:
+  - bit_offset: 0
+    bit_size: 2
+    description: PLL input clock source
+    name: PLLSRC
+  - bit_offset: 4
+    bit_size: 3
+    description: Division factor M of the PLL input clock divider
+    name: PLLM
+  - bit_offset: 8
+    bit_size: 7
+    description: PLL frequency multiplication factor N
+    name: PLLN
+  - bit_offset: 16
+    bit_size: 1
+    description: PLLPCLK clock output enable
+    name: PLLPEN
+  - bit_offset: 17
+    bit_size: 5
+    description: PLL VCO division factor P for PLLPCLK clock output
+    name: PLLP
+  - bit_offset: 24
+    bit_size: 1
+    description: PLLQCLK clock output enable
+    name: PLLQEN
+  - bit_offset: 25
+    bit_size: 3
+    description: PLL VCO division factor Q for PLLQCLK clock output
+    name: PLLQ
+  - bit_offset: 28
+    bit_size: 1
+    description: PLLRCLK clock output enable
+    name: PLLREN
+  - bit_offset: 29
+    bit_size: 3
+    description: PLL VCO division factor R for PLLRCLK clock output
+    name: PLLR
diff --git a/parse.py b/parse.py
index 0cc114f..82539fd 100755
--- a/parse.py
+++ b/parse.py
@@ -357,6 +357,7 @@ perimap = [
     ('STM32F0.0.*:RCC:.*', 'rcc_f0x0/RCC'),
     ('STM32F0.*:RCC:.*', 'rcc_f0/RCC'),
     ('STM32F1.*:RCC:.*', 'rcc_f1/RCC'),
+    ('STM32G0.*:RCC:.*', 'rcc_g0/RCC'),
     ('.*:STM32H7AB_rcc_v1_0', ''),  # rcc_h7ab/RCC
     ('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
     ('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),