Merge pull request #281 from noppej/gfxmmu

Add GFXMMU peripheral
2023-10-14 02:26:15 +00:00 · 2023-10-14 02:26:15 +00:00 · e90a83a4f0
commit e90a83a4f0
parent 06e776c04a bcaacfcfa2
9 changed files with 519 additions and 152 deletions
--- a/.gitignore
+++ b/.gitignore
@ -3,7 +3,7 @@
 /sources
 /tmp
 .idea/
-transform*.yaml
+# transform*.yaml
 __pycache__

 target/
--- a/data/registers/gfxmmu_v1.yaml
+++ b/data/registers/gfxmmu_v1.yaml
@ -0,0 +1,141 @@
+block/GFXMMU:
+  description: GFXMMU.
+  items:
+  - name: CR
+    description: GFXMMU configuration register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: GFXMMU status register.
+    byte_offset: 4
+    access: Read
+    fieldset: SR
+  - name: FCR
+    description: GFXMMU flag clear register.
+    byte_offset: 8
+    access: Write
+    fieldset: FCR
+  - name: DVR
+    description: GFXMMU default value register.
+    byte_offset: 16
+    fieldset: DVR
+  - name: BCR
+    description: GFXMMU buffer 0 configuration register.
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 32
+    fieldset: BCR
+  - name: LUTL
+    description: GFXMMU LUT entry 0 low.
+    array:
+      len: 1024
+      stride: 8
+    byte_offset: 4096
+    fieldset: LUTL
+  - name: LUTH
+    description: GFXMMU LUT entry 0 high.
+    array:
+      len: 1024
+      stride: 8
+    byte_offset: 4100
+    fieldset: LUTH
+fieldset/BCR:
+  description: GFXMMU buffer configuration register.
+  fields:
+  - name: PBO
+    description: Physical buffer offset. Offset of the physical buffer.
+    bit_offset: 4
+    bit_size: 19
+  - name: PBBA
+    description: Physical buffer base address. Base address MSB of the physical buffer.
+    bit_offset: 23
+    bit_size: 9
+fieldset/CR:
+  description: GFXMMU configuration register.
+  fields:
+  - name: BOIE
+    description: Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: AMEIE
+    description: AHB master error interrupt enable. This bit enables the AHB master error interrupt.
+    bit_offset: 4
+    bit_size: 1
+  - name: BM
+    description: 192 Block mode. This bit defines the number of blocks per line.
+    bit_offset: 6
+    bit_size: 1
+    array:
+      len: 1
+      stride: 0
+    enum: BM192
+fieldset/DVR:
+  description: GFXMMU default value register.
+  fields:
+  - name: DV
+    description: Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped.
+    bit_offset: 0
+    bit_size: 32
+fieldset/FCR:
+  description: GFXMMU flag clear register.
+  fields:
+  - name: CBOF
+    description: Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: CAMEF
+    description: Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register.
+    bit_offset: 4
+    bit_size: 1
+fieldset/LUTH:
+  description: GFXMMU LUT entry high.
+  fields:
+  - name: LO
+    description: Line offset. Line offset of line number x (i.e. offset of block 0 of line x).
+    bit_offset: 4
+    bit_size: 18
+fieldset/LUTL:
+  description: GFXMMU LUT entry low.
+  fields:
+  - name: EN
+    description: Line enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: FVB
+    description: First Valid Block. Number of the first valid block of line number x.
+    bit_offset: 8
+    bit_size: 8
+  - name: LVB
+    description: Last Valid Block. Number of the last valid block of line number X.
+    bit_offset: 16
+    bit_size: 8
+fieldset/SR:
+  description: GFXMMU status register.
+  fields:
+  - name: BOF
+    description: Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: AMEF
+    description: AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF.
+    bit_offset: 4
+    bit_size: 1
+enum/BM192:
+  bit_size: 1
+  variants:
+  - name: 256BlocksPerLine
+    description: 256 blocks per line.
+    value: 0
+  - name: 192BlocksPerLine
+    description: 192 blocks per line.
+    value: 1
--- a/data/registers/gfxmmu_v2.yaml
+++ b/data/registers/gfxmmu_v2.yaml
@ -0,0 +1,200 @@
+block/GFXMMU:
+  description: GFXMMU.
+  items:
+  - name: CR
+    description: GFXMMU configuration register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: GFXMMU status register.
+    byte_offset: 4
+    access: Read
+    fieldset: SR
+  - name: FCR
+    description: GFXMMU flag clear register.
+    byte_offset: 8
+    access: Write
+    fieldset: FCR
+  - name: CCR
+    description: GFXMMU cache control register.
+    byte_offset: 12
+    fieldset: CCR
+  - name: DVR
+    description: GFXMMU default value register.
+    byte_offset: 16
+    fieldset: DVR
+  - name: BCR
+    description: GFXMMU buffer 0 configuration register.
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 32
+    fieldset: BCR
+  - name: LUTL
+    description: GFXMMU LUT entry 0 low.
+    array:
+      len: 1024
+      stride: 8
+    byte_offset: 4096
+    fieldset: LUTL
+  - name: LUTH
+    description: GFXMMU LUT entry 0 high.
+    array:
+      len: 1024
+      stride: 8
+    byte_offset: 4100
+    fieldset: LUTH
+fieldset/BCR:
+  description: GFXMMU buffer configuration register.
+  fields:
+  - name: PBO
+    description: Physical buffer offset. Offset of the physical buffer.
+    bit_offset: 4
+    bit_size: 19
+  - name: PBBA
+    description: Physical buffer base address. Base address MSB of the physical buffer.
+    bit_offset: 23
+    bit_size: 9
+fieldset/CCR:
+  description: GFXMMU cache control register.
+  fields:
+  - name: FF
+    description: Force flush. When set, the cache entries are flushed. This bit is reset by hardware when the flushing is complete. Write 0 has no effect.
+    bit_offset: 0
+    bit_size: 1
+  - name: FI
+    description: Force invalidate. When set, the cache entries are invalidated. This bit is reset by hardware when the invalidation is complete. Write 0 has no effect.
+    bit_offset: 1
+    bit_size: 1
+fieldset/CR:
+  description: GFXMMU configuration register.
+  fields:
+  - name: BOIE
+    description: Buffer overflow interrupt enable. This bit enables the buffer 0 overflow interrupt.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: AMEIE
+    description: AHB master error interrupt enable. This bit enables the AHB master error interrupt.
+    bit_offset: 4
+    bit_size: 1
+  - name: BM
+    description: 192 Block mode. This bit defines the number of blocks per line.
+    bit_offset: 6
+    bit_size: 1
+    array:
+      len: 1
+      stride: 0
+    enum: BM192
+  - name: CE
+    description: Cache enable. This bit enables the cache unit.
+    bit_offset: 7
+    bit_size: 1
+  - name: CL
+    description: Cache lock. This bit lock the cache onto the buffer defined in the CLB field.
+    bit_offset: 8
+    bit_size: 1
+  - name: CLB
+    description: Cache lock buffer. This field select the buffer on which the cache is locked.
+    bit_offset: 9
+    bit_size: 2
+    enum: CLB
+  - name: FC
+    description: Force caching. This bit force the caching into the cache regardless of the MPU attributes.  The cache must be enable (CE bit set).
+    bit_offset: 11
+    bit_size: 1
+  - name: PD
+    description: Prefetch disable. This bit disables the prefetch of the cache.
+    bit_offset: 12
+    bit_size: 1
+  - name: OC
+    description: Outter cachability. This bit configure the cachability of an access generated by the GFXMMU cache.
+    bit_offset: 16
+    bit_size: 1
+  - name: OB
+    description: Outter bufferability. This bit configure the bufferability of an access generated by the GFXMMU cache.
+    bit_offset: 17
+    bit_size: 1
+fieldset/DVR:
+  description: GFXMMU default value register.
+  fields:
+  - name: DV
+    description: Default value. This field indicates the default 32-bit value which is returned when a master accesses a virtual memory location not physically mapped.
+    bit_offset: 0
+    bit_size: 32
+fieldset/FCR:
+  description: GFXMMU flag clear register.
+  fields:
+  - name: CBOF
+    description: Clear buffer overflow flag. Writing 1 clears the buffer 0 overflow flag in the GFXMMU_SR register.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: CAMEF
+    description: Clear AHB master error flag. Writing 1 clears the AHB master error flag in the GFXMMU_SR register.
+    bit_offset: 4
+    bit_size: 1
+fieldset/LUTH:
+  description: GFXMMU LUT entry high.
+  fields:
+  - name: LO
+    description: Line offset. Line offset of line number x (i.e. offset of block 0 of line x).
+    bit_offset: 4
+    bit_size: 18
+fieldset/LUTL:
+  description: GFXMMU LUT entry low.
+  fields:
+  - name: EN
+    description: Line enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: FVB
+    description: First Valid Block. Number of the first valid block of line number x.
+    bit_offset: 8
+    bit_size: 8
+  - name: LVB
+    description: Last Valid Block. Number of the last valid block of line number X.
+    bit_offset: 16
+    bit_size: 8
+fieldset/SR:
+  description: GFXMMU status register.
+  fields:
+  - name: BOF
+    description: Buffer overflow flag. This bit is set when an overflow occurs during the offset calculation of the buffer 0. It is cleared by writing 1 to CB0OF.
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 4
+      stride: 1
+  - name: AMEF
+    description: AHB master error flag. This bit is set when an AHB error happens during a transaction. It is cleared by writing 1 to CAMEF.
+    bit_offset: 4
+    bit_size: 1
+enum/BM192:
+  bit_size: 1
+  variants:
+  - name: 256BlocksPerLine
+    description: 256 blocks per line.
+    value: 0
+  - name: 192BlocksPerLine
+    description: 192 blocks per line.
+    value: 1
+enum/CLB:
+  bit_size: 2
+  variants:
+  - name: LockedOnBuffer0
+    description: Cache locked on buffer 0.
+    value: 0
+  - name: LockedOnBuffer1
+    description: Cache locked on buffer 1.
+    value: 1
+  - name: LockedOnBuffer2
+    description: Cache locked on buffer 2.
+    value: 2
+  - name: LockedOnBuffer3
+    description: Cache locked on buffer 3.
+    value: 3
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@ -489,6 +489,8 @@ impl PeriMatcher {
                "STM32H5.*:OCTOSPI[12]:OCTOSPI:octospi1_v5_1.*",
                ("octospi", "v2", "OCTOSPI"),
            ),
+            ("STM32L4.*:GFXMMU:.*", ("gfxmmu", "v1", "GFXMMU")),
+            ("STM32U5.*:GFXMMU:.*", ("gfxmmu", "v2", "GFXMMU")),
        ];

        Self {
--- a/transform-GFXMMU.yaml
+++ b/transform-GFXMMU.yaml
@ -0,0 +1,26 @@
+transforms:
+  - !RenameRegisters
+    block: .*
+    from: GFXMMU_(.+)
+    to: $1
+  - !RenameFields
+    fieldset: .*
+    from: GFXMMU_(.+)
+    to: $1
+  - !Rename
+    from: GFXMMU_(.+)
+    to: $1
+  - !DeleteEnums
+    from: .*(IE|_EN|FI|FF|PD|OC|OB|FC|CL|CE)$
+    bit_size: 1
+  - !MakeFieldArray
+    fieldsets: .*
+    from: ([A-Z]+)\d+([A-Z]*)
+    to: $1$2
+  - !MergeFieldsets
+    from: ([A-Z]+)\d+([A-Z]*)
+    to: $1$2
+  - !MakeRegisterArray
+    blocks: .*
+    from: ([A-Z]+)\d+([A-Z]*)
+    to: $1$2
--- a/transform-HRTIM.yaml
+++ b/transform-HRTIM.yaml
@ -1,85 +1,84 @@
 transforms:
- DeleteEnums:
+  - !DeleteEnums
    from: (CHP1|CMP1DE|CMP1IE|CPT1DE|CPT1IE|DIDL1|DLYPRTDE|DLYPRTEN|DLYPRTIE|DTEN|EE1LTCH)
    bit_size: 1
- DeleteEnums:
+  - !DeleteEnums
    from: (MCMP1IE|REPIE|RSTIE|RSTx1DE|RSTx1IE|SETx1DE|SETx1IE|SYNCRSTM|SYNCSTRTM|TACEN|TBU)
    bit_size: 1
- DeleteEnums:
+  - !DeleteEnums
    from: (TBU|TxREPU|TxRSTU|UPDDE|UPDIE|EE6LTCH|HALF|MCEN|MCMP1DE|MREPU|MSTU|PREEN|PSHPLL)
    bit_size: 1
- DeleteEnums:
+  - !DeleteEnums
    from: (REPDE|RETRIG|RSTDE|EE6LTCH)
    bit_size: 1
- MergeEnums: 
+  - !MergeEnums
    from: CPT(\d)[A-Z]CR_(.*)
    to: CAPTUREEFFECT
- MergeEnums:
+  - !MergeEnums
    from: (CPT1|MCMP1|MREP|MUPD|REP|RST|RSTx1|SETx1|SYNC|TIMAISR_CMP1|TIMBISR_CMP1|TIMCISR_CMP1|TIMDISR_CMP1|TIMEISR_CMP1|UPD)
    to: EVENT
- MergeEnums:
+  - !MergeEnums
    from: (DTFLKx|DTFSLKx|DTRLKx|DTRSLKx|FLTLCK)
    to: LOCKED
- MergeEnums:
+  - !MergeEnums
    from: (RST[A-E][1-2]R_CMP1|RST[A-E][1-2]R_EXTEVNT1|RST[A-E][1-2]R_MSTCMP1|RST[A-E][1-2]R_MSTPER|RST[A-E][1-2]R_PER|RST[A-E][1-2]R_RESYNC|RST[A-E][1-2]R_SRT|RST[A-E][1-2]R_TIMEVNT1|RST[A-E][1-2])
    to: INACTIVEEFFECT
- MergeEnums:
+  - !MergeEnums
    from: (CMP2|RSTAR_EXTEVNT1|RSTAR_MSTCMP1|RSTAR_MSTPER|RSTBR_EXTEVNT1|RSTBR_MSTCMP1|RSTBR_MSTPER|RSTCR_EXTEVNT1|RSTCR_MSTCMP1|RSTCR_MSTPER|RSTDR_EXTEVNT1|RSTDR_MSTCMP1|RSTDR_MSTPER|RSTER_EXTEVNT1|RSTER_MSTCMP1|RSTER_MSTPER|TIMACMP1|TIMBCMP1|UPDT)
    to: RESETEFFECT
- MergeEnums:
+  - !MergeEnums
    from: OUT[A-C]R_DLYPRT
    to: OUTAR_DLYPRT
- MergeEnums:
+  - !MergeEnums
    from: OUT[D-E]R_DLYPRT
    to: OUTDR_DLYPRT
- MergeEnums:
+  - !MergeEnums
    from: (SET[A-E][1-2]R_CMP1|SET[A-E][1-2]R_EXTEVNT1|SET[A-E][1-2]R_MSTCMP1|SET[A-E][1-2]R_MSTPER|SET[A-E][1-2]R_PER|SET[A-E][1-2]R_RESYNC|SET[A-E][1-2]R_SST|SET[A-E][1-2]R_TIMEVNT1|SET[A-E][1-2]R_UPDATE)
    to: ACTIVEEFFECT
- MergeEnums: 
+  - !MergeEnums
    from: (O1CPY|O1STAT)
    to: OUTPUTSTATE
- MergeEnums: 
+  - !MergeEnums
    from: TIM[A-E]ISR_DLYPRT
    to: TIMAISR_DLYPRT
-
-#  - MergeEnums:
+#  - !MergeEnums
 #      from: CCMR\d_Input_CC\dS
 #      to: CCMR_Input_CCS
 #      check: Layout

-  # Remove digits from enum names
-#  - MergeEnums:
+# Remove digits from enum names
+#  - !MergeEnums
 #      from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]*
 #      to: $1$2$3
 #      skip_unmergeable: true
 #
-#  - MakeFieldArray:
+#  - !MakeFieldArray
 #      fieldsets: .*
 #      from: ([A-Z]+)\d+
 #      to: $1
 #      allow_cursed: true
-#  - MakeFieldArray:
+#  - !MakeFieldArray
 #      fieldsets: .*
 #      from: P\d+WP
 #      to: PWP
-#  - MakeRegisterArray:
+#  - !MakeRegisterArray
 #      blocks: .*
 #      from: ([A-Z]+)\d+
 #      to: $1
-#  - MakeRegisterArray:
+#  - !MakeRegisterArray
 #      blocks: .*
 #      from: EXTICR\d+
 #      to: EXTICR
-#  - MergeEnums:
+#  - !MergeEnums
 #      from: '[HL](IFCR|ISR)_(.*)'
 #      to: $2
-#  - MergeFieldsets:
+#  - !MergeFieldsets
 #      from: '[HL](IFCR|ISR)'
 #      to: $1
-#  - MergeFieldsets:
+#  - !MergeFieldsets
 #      from: EXTICR\d
 #      to: EXTICR
-#  - MakeRegisterArray:
+#  - !MakeRegisterArray
 #      blocks: .*
 #      from: '[HL](IFCR|ISR)'
 #      to: $1
--- a/transform-RCC.yaml
+++ b/transform-RCC.yaml
@ -1,64 +1,63 @@
 transforms:
-
-  - MergeEnums:
-      from: CCMR\d_Input_CC\dS
-      to: CCMR_Input_CCS
-      check: Layout
+  - !MergeEnums
+    from: CCMR\d_Input_CC\dS
+    to: CCMR_Input_CCS
+    check: Layout

  # Remove digits from enum names
-  - MergeEnums:
-      from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]*
-      to: $1$2$3
-      skip_unmergeable: true
+  - !MergeEnums
+    from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]*
+    to: $1$2$3
+    skip_unmergeable: true

-      #- MakeFieldArray:
-      #    fieldsets: .*
-      #    from: ([A-Z]+)\d([A-Z]*)
-      #    to: $1$2
-      #    allow_cursed: true
-  - MakeFieldArray:
-      fieldsets: .*
-      from: P\d+WP
-      to: PWP 
-#  - MakeRegisterArray:
-#      blocks: .*
-#      from: ([A-Z]+)\d+
-#      to: $1
-  - MakeRegisterArray:
-      blocks: .*
-      from: EXTICR\d+
-      to: EXTICR 
-  - MergeEnums:
-      from: '[HL](IFCR|ISR)_(.*)'
-      to: $2
-  - MergeFieldsets:
-      from: '[HL](IFCR|ISR)'
-      to: $1
-  - MergeFieldsets:
-      from: EXTICR\d 
-      to: EXTICR 
-  - MakeRegisterArray:
-      blocks: .*
-      from: '[HL](IFCR|ISR)'
-      to: $1
-  - DeleteEnums:
-      from: '.*EN'
-      bit_size: 1
-  - DeleteEnums:
-      from: '.*RST'
-      bit_size: 1
-  - DeleteEnums:
-      from: '.*ON'
-      bit_size: 1
-  - MakeRegisterArray:
-      blocks: .*
-      from: PLL\d+(.*)
-      to: PLL$1
-  - MakeFieldArray:
-      fieldsets: .*
-      from: PLL\d+(.*)
-      to: PLL$1
-  - MakeFieldArray:
-      fieldsets: (PLLCFGR|PLLCKSELR)
-      from: DIV([A-Z]+)\d+([A-Z]*)
-      to: DIV$1$2
+    #- !MakeFieldArray
+    #    fieldsets: .*
+    #    from: ([A-Z]+)\d([A-Z]*)
+    #    to: $1$2
+    #    allow_cursed: true
+  - !MakeFieldArray
+    fieldsets: .*
+    from: P\d+WP
+    to: PWP
+  #  - !MakeRegisterArray
+  #      blocks: .*
+  #      from: ([A-Z]+)\d+
+  #      to: $1
+  - !MakeRegisterArray
+    blocks: .*
+    from: EXTICR\d+
+    to: EXTICR
+  - !MergeEnums
+    from: "[HL](IFCR|ISR)_(.*)"
+    to: $2
+  - !MergeFieldsets
+    from: "[HL](IFCR|ISR)"
+    to: $1
+  - !MergeFieldsets
+    from: EXTICR\d
+    to: EXTICR
+  - !MakeRegisterArray
+    blocks: .*
+    from: "[HL](IFCR|ISR)"
+    to: $1
+  - !DeleteEnums
+    from: ".*EN"
+    bit_size: 1
+  - !DeleteEnums
+    from: ".*RST"
+    bit_size: 1
+  - !DeleteEnums
+    from: ".*ON"
+    bit_size: 1
+  - !MakeRegisterArray
+    blocks: .*
+    from: PLL\d+(.*)
+    to: PLL$1
+  - !MakeFieldArray
+    fieldsets: .*
+    from: PLL\d+(.*)
+    to: PLL$1
+  - !MakeFieldArray
+    fieldsets: (PLLCFGR|PLLCKSELR)
+    from: DIV([A-Z]+)\d+([A-Z]*)
+    to: DIV$1$2
--- a/transform-USB_OTG.yaml
+++ b/transform-USB_OTG.yaml
@ -1,27 +1,27 @@
 transforms:
  # OTG_FS_HOST
-  - ModifyByteOffset:
-      block: OTG_FS_HOST
-      add_offset: 0x400
-  - MergeFieldsets:
-      from: (HCINT|HCCHAR|HCINTMSK|HCTSIZ)\d
-      to: $1
-  - MakeRegisterArray:
-      blocks: .*
-      from: (HCINT|HCCHAR|HCINTMSK|HCTSIZ)\d
-      to: $1
+  - !ModifyByteOffset
+    block: OTG_FS_HOST
+    add_offset: 0x400
+  - !MergeFieldsets
+    from: (HCINT|HCCHAR|HCINTMSK|HCTSIZ)\d
+    to: $1
+  - !MakeRegisterArray
+    blocks: .*
+    from: (HCINT|HCCHAR|HCINTMSK|HCTSIZ)\d
+    to: $1
  # OTG_FS_DEVICE
-  - ModifyByteOffset:
-      block: OTG_FS_DEVICE
-      add_offset: 0x800
+  - !ModifyByteOffset
+    block: OTG_FS_DEVICE
+    add_offset: 0x800
  # Excluding endpoint 0, it has special registers.
-  - MergeFieldsets:
-      from: (DIEPCTL|D[IO]EPINT|D[IO]EPTSIZ|DTXFSTS)[1-9]
-      to: $1
-  - MakeRegisterArray:
-      blocks: .*
-      from: (DIEPCTL|D[IO]EPINT|D[IO]EPTSIZ|DTXFSTS)[1-9]
-      to: $1
-  - ModifyByteOffset:
-      block: OTG_FS_PWRCLK
-      add_offset: 0xE00
+  - !MergeFieldsets
+    from: (DIEPCTL|D[IO]EPINT|D[IO]EPTSIZ|DTXFSTS)[1-9]
+    to: $1
+  - !MakeRegisterArray
+    blocks: .*
+    from: (DIEPCTL|D[IO]EPINT|D[IO]EPTSIZ|DTXFSTS)[1-9]
+    to: $1
+  - !ModifyByteOffset
+    block: OTG_FS_PWRCLK
+    add_offset: 0xE00
--- a/transform.yaml
+++ b/transform.yaml
@ -1,42 +1,42 @@
 transforms:
-  - MergeEnums:
-      from: CCMR\d_Input_CC\dS
-      to: CCMR_Input_CCS
-      check: Layout
+  - !MergeEnums
+    from: CCMR\d_Input_CC\dS
+    to: CCMR_Input_CCS
+    check: Layout

  # Remove digits from enum names
-  - MergeEnums:
-      from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]*
-      to: $1$2$3
-      skip_unmergeable: true
+  - !MergeEnums
+    from: ([^\d]*)[\d]*([^\d]*)[\d]*([^\d]*)[\d]*
+    to: $1$2$3
+    skip_unmergeable: true

-  - MakeFieldArray:
-      fieldsets: .*
-      from: ([A-Z]+)\d+
-      to: $1
-      allow_cursed: true
-  - MakeFieldArray:
-      fieldsets: .*
-      from: P\d+WP
-      to: PWP 
-#  - MakeRegisterArray:
-#      blocks: .*
-#      from: ([A-Z]+)\d+
-#      to: $1
-  - MakeRegisterArray:
-      blocks: .*
-      from: EXTICR\d+
-      to: EXTICR 
-  - MergeEnums:
-      from: '[HL](IFCR|ISR)_(.*)'
-      to: $2
-  - MergeFieldsets:
-      from: '[HL](IFCR|ISR)'
-      to: $1
-  - MergeFieldsets:
-      from: EXTICR\d 
-      to: EXTICR 
-  - MakeRegisterArray:
-      blocks: .*
-      from: '[HL](IFCR|ISR)'
-      to: $1
+  - !MakeFieldArray
+    fieldsets: .*
+    from: ([A-Z]+)\d+
+    to: $1
+    allow_cursed: true
+  - !MakeFieldArray
+    fieldsets: .*
+    from: P\d+WP
+    to: PWP
+  #  - !MakeRegisterArray
+  #      blocks: .*
+  #      from: ([A-Z]+)\d+
+  #      to: $1
+  - !MakeRegisterArray
+    blocks: .*
+    from: EXTICR\d+
+    to: EXTICR
+  - !MergeEnums
+    from: "[HL](IFCR|ISR)_(.*)"
+    to: $2
+  - !MergeFieldsets
+    from: "[HL](IFCR|ISR)"
+    to: $1
+  - !MergeFieldsets
+    from: EXTICR\d
+    to: EXTICR
+  - !MakeRegisterArray
+    blocks: .*
+    from: "[HL](IFCR|ISR)"
+    to: $1