Clean up rcc_f1.yaml
This commit is contained in:
Grant Miller
parent
d7674ab524
commit
e905859bdf
@ -42,14 +42,6 @@ block/RCC:
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description: Control/status register (RCC_CSR)
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byte_offset: 36
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fieldset: CSR
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- name: AHBRSTR
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description: AHB peripheral clock reset register (RCC_AHBRSTR)
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byte_offset: 40
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fieldset: AHBRSTR
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- name: CFGR2
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description: Clock configuration register 2
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byte_offset: 44
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fieldset: CFGR2
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fieldset/AHBENR:
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description: AHB Peripheral Clock enable register (RCC_AHBENR)
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fields:
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@ -81,33 +73,6 @@ fieldset/AHBENR:
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description: SDIO clock enable
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bit_offset: 10
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bit_size: 1
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- name: USB_OTG_FSEN
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description: USB OTG FS clock enable
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bit_offset: 12
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bit_size: 1
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- name: ETHEN
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description: Ethernet MAC clock enable
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bit_offset: 14
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bit_size: 1
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- name: ETHTXEN
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description: Ethernet MAC TX clock enable
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bit_offset: 15
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bit_size: 1
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- name: ETHRXEN
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description: Ethernet MAC RX clock enable
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bit_offset: 16
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bit_size: 1
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fieldset/AHBRSTR:
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description: AHB peripheral clock reset register (RCC_AHBRSTR)
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fields:
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- name: USB_OTG_FSRST
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description: USB OTG FS reset
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bit_offset: 12
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bit_size: 1
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- name: ETHRST
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description: Ethernet MAC reset
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bit_offset: 14
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bit_size: 1
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fieldset/APB1ENR:
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description: APB1 peripheral clock enable register (RCC_APB1ENR)
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fields:
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@ -187,18 +152,10 @@ fieldset/APB1ENR:
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description: USB clock enable
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bit_offset: 23
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bit_size: 1
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- name: CAN1EN
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description: CAN1 clock enable
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bit_offset: 25
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bit_size: 1
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- name: CANEN
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description: CAN clock enable
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bit_offset: 25
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bit_size: 1
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- name: CAN2EN
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description: CAN2 clock enable
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bit_offset: 26
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bit_size: 1
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- name: BKPEN
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description: Backup interface clock enable
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bit_offset: 27
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@ -211,10 +168,6 @@ fieldset/APB1ENR:
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description: DAC interface clock enable
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bit_offset: 29
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bit_size: 1
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- name: CECEN
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description: CEC clock enable
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bit_offset: 30
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bit_size: 1
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fieldset/APB1RSTR:
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description: APB1 peripheral reset register (RCC_APB1RSTR)
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fields:
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@ -294,18 +247,10 @@ fieldset/APB1RSTR:
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description: USB reset
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bit_offset: 23
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bit_size: 1
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- name: CAN1RST
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description: CAN1 reset
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bit_offset: 25
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bit_size: 1
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- name: CANRST
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description: CAN reset
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bit_offset: 25
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bit_size: 1
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- name: CAN2RST
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description: CAN2 reset
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bit_offset: 26
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bit_size: 1
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- name: BKPRST
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description: Backup interface reset
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bit_offset: 27
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@ -318,10 +263,6 @@ fieldset/APB1RSTR:
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description: DAC interface reset
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bit_offset: 29
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bit_size: 1
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- name: CECRST
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description: CEC reset
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bit_offset: 30
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bit_size: 1
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fieldset/APB2ENR:
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description: APB2 peripheral clock enable register (RCC_APB2ENR)
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fields:
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@ -385,18 +326,6 @@ fieldset/APB2ENR:
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description: ADC3 interface clock enable
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bit_offset: 15
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bit_size: 1
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- name: TIM15EN
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description: TIM15 Timer clock enable
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bit_offset: 16
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bit_size: 1
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- name: TIM16EN
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description: TIM16 Timer clock enable
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bit_offset: 17
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bit_size: 1
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- name: TIM17EN
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description: TIM17 Timer clock enable
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bit_offset: 18
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bit_size: 1
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- name: TIM9EN
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description: TIM9 Timer clock enable
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bit_offset: 19
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@ -472,18 +401,6 @@ fieldset/APB2RSTR:
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description: ADC 3 interface reset
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bit_offset: 15
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bit_size: 1
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- name: TIM15RST
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description: TIM15 timer reset
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bit_offset: 16
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bit_size: 1
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- name: TIM16RST
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description: TIM16 timer reset
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bit_offset: 17
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bit_size: 1
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- name: TIM17RST
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description: TIM17 timer reset
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bit_offset: 18
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bit_size: 1
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- name: TIM9RST
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description: TIM9 timer reset
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bit_offset: 19
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@ -572,11 +489,6 @@ fieldset/CFGR:
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bit_offset: 18
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bit_size: 4
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enum: PLLMUL
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- name: OTGFSPRE
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description: USB OTG FS prescaler
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bit_offset: 22
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bit_size: 1
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enum: OTGFSPRE
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- name: USBPRE
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description: USB prescaler
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bit_offset: 22
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@ -587,44 +499,6 @@ fieldset/CFGR:
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bit_offset: 24
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bit_size: 3
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enum: MCO
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fieldset/CFGR2:
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description: Clock configuration register2 (RCC_CFGR2)
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fields:
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- name: PREDIV1
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description: PREDIV1 division factor
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bit_offset: 0
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bit_size: 4
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enum: PREDIV1
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- name: PREDIV2
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description: PREDIV2 division factor
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bit_offset: 4
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bit_size: 4
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enum: PREDIV1
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- name: PLL2MUL
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description: PLL2 Multiplication Factor
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bit_offset: 8
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bit_size: 4
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enum: PLL2MUL
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- name: PLL3MUL
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description: PLL3 Multiplication Factor
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bit_offset: 12
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bit_size: 4
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enum: PLL2MUL
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- name: PREDIV1SRC
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description: PREDIV1 entry clock source
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bit_offset: 16
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bit_size: 1
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enum: PREDIV1SRC
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- name: I2S2SRC
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description: I2S2 clock source
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bit_offset: 17
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bit_size: 1
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enum: I2S2SRC
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- name: I2S3SRC
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description: I2S3 clock source
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bit_offset: 18
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bit_size: 1
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enum: I2S2SRC
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fieldset/CIR:
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description: Clock interrupt register (RCC_CIR)
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fields:
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@ -648,14 +522,6 @@ fieldset/CIR:
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description: PLL Ready Interrupt flag
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bit_offset: 4
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bit_size: 1
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- name: PLL2RDYF
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description: PLL2 Ready Interrupt flag
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bit_offset: 5
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bit_size: 1
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- name: PLL3RDYF
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description: PLL3 Ready Interrupt flag
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bit_offset: 6
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bit_size: 1
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- name: CSSF
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description: Clock Security System Interrupt flag
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bit_offset: 7
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@ -680,14 +546,6 @@ fieldset/CIR:
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description: PLL Ready Interrupt Enable
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bit_offset: 12
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bit_size: 1
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- name: PLL2RDYIE
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description: PLL2 Ready Interrupt Enable
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bit_offset: 13
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bit_size: 1
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- name: PLL3RDYIE
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description: PLL3 Ready Interrupt Enable
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bit_offset: 14
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bit_size: 1
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- name: LSIRDYC
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description: LSI Ready Interrupt Clear
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bit_offset: 16
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@ -708,14 +566,6 @@ fieldset/CIR:
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description: PLL Ready Interrupt Clear
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bit_offset: 20
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bit_size: 1
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- name: PLL2RDYC
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description: PLL2 Ready Interrupt Clear
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bit_offset: 21
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bit_size: 1
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- name: PLL3RDYC
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description: PLL3 Ready Interrupt Clear
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bit_offset: 22
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bit_size: 1
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- name: CSSC
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description: Clock security system interrupt clear
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bit_offset: 23
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@ -763,22 +613,6 @@ fieldset/CR:
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description: PLL clock ready flag
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bit_offset: 25
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bit_size: 1
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- name: PLL2ON
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description: PLL2 enable
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bit_offset: 26
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bit_size: 1
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- name: PLL2RDY
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description: PLL2 clock ready flag
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bit_offset: 27
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bit_size: 1
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- name: PLL3ON
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description: PLL3 enable
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bit_offset: 28
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bit_size: 1
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- name: PLL3RDY
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description: PLL3 clock ready flag
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bit_offset: 29
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bit_size: 1
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fieldset/CSR:
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description: Control/status register (RCC_CSR)
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fields:
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@ -863,15 +697,6 @@ enum/HPRE:
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- name: Div512
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description: SYSCLK divided by 512
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value: 15
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enum/I2S2SRC:
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bit_size: 1
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variants:
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- name: SYSCLK
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description: System clock (SYSCLK) selected as I2S clock entry
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value: 0
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- name: PLL3
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description: PLL3 VCO clock selected as I2S clock entry
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value: 1
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enum/MCO:
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bit_size: 3
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variants:
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@ -890,45 +715,6 @@ enum/MCO:
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- name: PLL
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description: PLL clock divided by 2 selected
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value: 7
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enum/OTGFSPRE:
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bit_size: 1
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variants:
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- name: DIV1_5
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description: PLL clock is divided by 1.5
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value: 0
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- name: DIV1
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description: PLL clock is not divided
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value: 1
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enum/PLL2MUL:
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bit_size: 4
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variants:
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- name: Mul8
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description: PLL clock entry x8
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value: 6
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- name: Mul9
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description: PLL clock entry x9
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value: 7
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- name: Mul10
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description: PLL clock entry x10
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value: 8
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- name: Mul11
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description: PLL clock entry x11
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value: 9
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- name: Mul12
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description: PLL clock entry x12
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value: 10
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- name: Mul13
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description: PLL clock entry x13
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value: 11
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- name: Mul14
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description: PLL clock entry x14
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value: 12
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- name: Mul16
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description: PLL clock entry x16
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value: 14
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- name: Mul20
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description: PLL clock entry x20
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value: 15
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enum/PLLMUL:
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bit_size: 4
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variants:
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@ -1016,66 +802,6 @@ enum/PPRE1:
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- name: Div16
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description: HCLK divided by 16
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value: 7
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enum/PREDIV1:
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bit_size: 4
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variants:
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- name: Div1
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description: PREDIV input clock not divided
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value: 0
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- name: Div2
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description: PREDIV input clock divided by 2
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value: 1
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- name: Div3
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description: PREDIV input clock divided by 3
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value: 2
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- name: Div4
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description: PREDIV input clock divided by 4
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value: 3
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- name: Div5
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description: PREDIV input clock divided by 5
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value: 4
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- name: Div6
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description: PREDIV input clock divided by 6
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value: 5
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- name: Div7
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description: PREDIV input clock divided by 7
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value: 6
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- name: Div8
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description: PREDIV input clock divided by 8
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value: 7
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- name: Div9
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description: PREDIV input clock divided by 9
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value: 8
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- name: Div10
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description: PREDIV input clock divided by 10
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value: 9
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- name: Div11
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description: PREDIV input clock divided by 11
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value: 10
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- name: Div12
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description: PREDIV input clock divided by 12
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value: 11
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- name: Div13
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description: PREDIV input clock divided by 13
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value: 12
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- name: Div14
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description: PREDIV input clock divided by 14
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value: 13
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- name: Div15
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description: PREDIV input clock divided by 15
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value: 14
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- name: Div16
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description: PREDIV input clock divided by 16
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value: 15
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enum/PREDIV1SRC:
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bit_size: 1
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variants:
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- name: HSE
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description: HSE oscillator clock selected as PREDIV1 clock entry
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value: 0
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- name: PLL2
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description: PLL2 selected as PREDIV1 clock entry
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value: 1
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enum/RTCSEL:
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bit_size: 2
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variants:
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