From e905859bdfe3a479cd44bc68f07b3a0811f0cff3 Mon Sep 17 00:00:00 2001 From: Grant Miller Date: Sun, 1 May 2022 13:31:59 -0500 Subject: [PATCH] Clean up rcc_f1.yaml --- data/registers/rcc_f1.yaml | 274 ------------------------------------- 1 file changed, 274 deletions(-) diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 3b7a5d2..77ea7b2 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -42,14 +42,6 @@ block/RCC: description: Control/status register (RCC_CSR) byte_offset: 36 fieldset: CSR - - name: AHBRSTR - description: AHB peripheral clock reset register (RCC_AHBRSTR) - byte_offset: 40 - fieldset: AHBRSTR - - name: CFGR2 - description: Clock configuration register 2 - byte_offset: 44 - fieldset: CFGR2 fieldset/AHBENR: description: AHB Peripheral Clock enable register (RCC_AHBENR) fields: @@ -81,33 +73,6 @@ fieldset/AHBENR: description: SDIO clock enable bit_offset: 10 bit_size: 1 - - name: USB_OTG_FSEN - description: USB OTG FS clock enable - bit_offset: 12 - bit_size: 1 - - name: ETHEN - description: Ethernet MAC clock enable - bit_offset: 14 - bit_size: 1 - - name: ETHTXEN - description: Ethernet MAC TX clock enable - bit_offset: 15 - bit_size: 1 - - name: ETHRXEN - description: Ethernet MAC RX clock enable - bit_offset: 16 - bit_size: 1 -fieldset/AHBRSTR: - description: AHB peripheral clock reset register (RCC_AHBRSTR) - fields: - - name: USB_OTG_FSRST - description: USB OTG FS reset - bit_offset: 12 - bit_size: 1 - - name: ETHRST - description: Ethernet MAC reset - bit_offset: 14 - bit_size: 1 fieldset/APB1ENR: description: APB1 peripheral clock enable register (RCC_APB1ENR) fields: @@ -187,18 +152,10 @@ fieldset/APB1ENR: description: USB clock enable bit_offset: 23 bit_size: 1 - - name: CAN1EN - description: CAN1 clock enable - bit_offset: 25 - bit_size: 1 - name: CANEN description: CAN clock enable bit_offset: 25 bit_size: 1 - - name: CAN2EN - description: CAN2 clock enable - bit_offset: 26 - bit_size: 1 - name: BKPEN description: Backup interface clock enable bit_offset: 27 @@ -211,10 +168,6 @@ fieldset/APB1ENR: description: DAC interface clock enable bit_offset: 29 bit_size: 1 - - name: CECEN - description: CEC clock enable - bit_offset: 30 - bit_size: 1 fieldset/APB1RSTR: description: APB1 peripheral reset register (RCC_APB1RSTR) fields: @@ -294,18 +247,10 @@ fieldset/APB1RSTR: description: USB reset bit_offset: 23 bit_size: 1 - - name: CAN1RST - description: CAN1 reset - bit_offset: 25 - bit_size: 1 - name: CANRST description: CAN reset bit_offset: 25 bit_size: 1 - - name: CAN2RST - description: CAN2 reset - bit_offset: 26 - bit_size: 1 - name: BKPRST description: Backup interface reset bit_offset: 27 @@ -318,10 +263,6 @@ fieldset/APB1RSTR: description: DAC interface reset bit_offset: 29 bit_size: 1 - - name: CECRST - description: CEC reset - bit_offset: 30 - bit_size: 1 fieldset/APB2ENR: description: APB2 peripheral clock enable register (RCC_APB2ENR) fields: @@ -385,18 +326,6 @@ fieldset/APB2ENR: description: ADC3 interface clock enable bit_offset: 15 bit_size: 1 - - name: TIM15EN - description: TIM15 Timer clock enable - bit_offset: 16 - bit_size: 1 - - name: TIM16EN - description: TIM16 Timer clock enable - bit_offset: 17 - bit_size: 1 - - name: TIM17EN - description: TIM17 Timer clock enable - bit_offset: 18 - bit_size: 1 - name: TIM9EN description: TIM9 Timer clock enable bit_offset: 19 @@ -472,18 +401,6 @@ fieldset/APB2RSTR: description: ADC 3 interface reset bit_offset: 15 bit_size: 1 - - name: TIM15RST - description: TIM15 timer reset - bit_offset: 16 - bit_size: 1 - - name: TIM16RST - description: TIM16 timer reset - bit_offset: 17 - bit_size: 1 - - name: TIM17RST - description: TIM17 timer reset - bit_offset: 18 - bit_size: 1 - name: TIM9RST description: TIM9 timer reset bit_offset: 19 @@ -572,11 +489,6 @@ fieldset/CFGR: bit_offset: 18 bit_size: 4 enum: PLLMUL - - name: OTGFSPRE - description: USB OTG FS prescaler - bit_offset: 22 - bit_size: 1 - enum: OTGFSPRE - name: USBPRE description: USB prescaler bit_offset: 22 @@ -587,44 +499,6 @@ fieldset/CFGR: bit_offset: 24 bit_size: 3 enum: MCO -fieldset/CFGR2: - description: Clock configuration register2 (RCC_CFGR2) - fields: - - name: PREDIV1 - description: PREDIV1 division factor - bit_offset: 0 - bit_size: 4 - enum: PREDIV1 - - name: PREDIV2 - description: PREDIV2 division factor - bit_offset: 4 - bit_size: 4 - enum: PREDIV1 - - name: PLL2MUL - description: PLL2 Multiplication Factor - bit_offset: 8 - bit_size: 4 - enum: PLL2MUL - - name: PLL3MUL - description: PLL3 Multiplication Factor - bit_offset: 12 - bit_size: 4 - enum: PLL2MUL - - name: PREDIV1SRC - description: PREDIV1 entry clock source - bit_offset: 16 - bit_size: 1 - enum: PREDIV1SRC - - name: I2S2SRC - description: I2S2 clock source - bit_offset: 17 - bit_size: 1 - enum: I2S2SRC - - name: I2S3SRC - description: I2S3 clock source - bit_offset: 18 - bit_size: 1 - enum: I2S2SRC fieldset/CIR: description: Clock interrupt register (RCC_CIR) fields: @@ -648,14 +522,6 @@ fieldset/CIR: description: PLL Ready Interrupt flag bit_offset: 4 bit_size: 1 - - name: PLL2RDYF - description: PLL2 Ready Interrupt flag - bit_offset: 5 - bit_size: 1 - - name: PLL3RDYF - description: PLL3 Ready Interrupt flag - bit_offset: 6 - bit_size: 1 - name: CSSF description: Clock Security System Interrupt flag bit_offset: 7 @@ -680,14 +546,6 @@ fieldset/CIR: description: PLL Ready Interrupt Enable bit_offset: 12 bit_size: 1 - - name: PLL2RDYIE - description: PLL2 Ready Interrupt Enable - bit_offset: 13 - bit_size: 1 - - name: PLL3RDYIE - description: PLL3 Ready Interrupt Enable - bit_offset: 14 - bit_size: 1 - name: LSIRDYC description: LSI Ready Interrupt Clear bit_offset: 16 @@ -708,14 +566,6 @@ fieldset/CIR: description: PLL Ready Interrupt Clear bit_offset: 20 bit_size: 1 - - name: PLL2RDYC - description: PLL2 Ready Interrupt Clear - bit_offset: 21 - bit_size: 1 - - name: PLL3RDYC - description: PLL3 Ready Interrupt Clear - bit_offset: 22 - bit_size: 1 - name: CSSC description: Clock security system interrupt clear bit_offset: 23 @@ -763,22 +613,6 @@ fieldset/CR: description: PLL clock ready flag bit_offset: 25 bit_size: 1 - - name: PLL2ON - description: PLL2 enable - bit_offset: 26 - bit_size: 1 - - name: PLL2RDY - description: PLL2 clock ready flag - bit_offset: 27 - bit_size: 1 - - name: PLL3ON - description: PLL3 enable - bit_offset: 28 - bit_size: 1 - - name: PLL3RDY - description: PLL3 clock ready flag - bit_offset: 29 - bit_size: 1 fieldset/CSR: description: Control/status register (RCC_CSR) fields: @@ -863,15 +697,6 @@ enum/HPRE: - name: Div512 description: SYSCLK divided by 512 value: 15 -enum/I2S2SRC: - bit_size: 1 - variants: - - name: SYSCLK - description: System clock (SYSCLK) selected as I2S clock entry - value: 0 - - name: PLL3 - description: PLL3 VCO clock selected as I2S clock entry - value: 1 enum/MCO: bit_size: 3 variants: @@ -890,45 +715,6 @@ enum/MCO: - name: PLL description: PLL clock divided by 2 selected value: 7 -enum/OTGFSPRE: - bit_size: 1 - variants: - - name: DIV1_5 - description: PLL clock is divided by 1.5 - value: 0 - - name: DIV1 - description: PLL clock is not divided - value: 1 -enum/PLL2MUL: - bit_size: 4 - variants: - - name: Mul8 - description: PLL clock entry x8 - value: 6 - - name: Mul9 - description: PLL clock entry x9 - value: 7 - - name: Mul10 - description: PLL clock entry x10 - value: 8 - - name: Mul11 - description: PLL clock entry x11 - value: 9 - - name: Mul12 - description: PLL clock entry x12 - value: 10 - - name: Mul13 - description: PLL clock entry x13 - value: 11 - - name: Mul14 - description: PLL clock entry x14 - value: 12 - - name: Mul16 - description: PLL clock entry x16 - value: 14 - - name: Mul20 - description: PLL clock entry x20 - value: 15 enum/PLLMUL: bit_size: 4 variants: @@ -1016,66 +802,6 @@ enum/PPRE1: - name: Div16 description: HCLK divided by 16 value: 7 -enum/PREDIV1: - bit_size: 4 - variants: - - name: Div1 - description: PREDIV input clock not divided - value: 0 - - name: Div2 - description: PREDIV input clock divided by 2 - value: 1 - - name: Div3 - description: PREDIV input clock divided by 3 - value: 2 - - name: Div4 - description: PREDIV input clock divided by 4 - value: 3 - - name: Div5 - description: PREDIV input clock divided by 5 - value: 4 - - name: Div6 - description: PREDIV input clock divided by 6 - value: 5 - - name: Div7 - description: PREDIV input clock divided by 7 - value: 6 - - name: Div8 - description: PREDIV input clock divided by 8 - value: 7 - - name: Div9 - description: PREDIV input clock divided by 9 - value: 8 - - name: Div10 - description: PREDIV input clock divided by 10 - value: 9 - - name: Div11 - description: PREDIV input clock divided by 11 - value: 10 - - name: Div12 - description: PREDIV input clock divided by 12 - value: 11 - - name: Div13 - description: PREDIV input clock divided by 13 - value: 12 - - name: Div14 - description: PREDIV input clock divided by 14 - value: 13 - - name: Div15 - description: PREDIV input clock divided by 15 - value: 14 - - name: Div16 - description: PREDIV input clock divided by 16 - value: 15 -enum/PREDIV1SRC: - bit_size: 1 - variants: - - name: HSE - description: HSE oscillator clock selected as PREDIV1 clock entry - value: 0 - - name: PLL2 - description: PLL2 selected as PREDIV1 clock entry - value: 1 enum/RTCSEL: bit_size: 2 variants: