Add OR register.

OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse.
OR2 and OR3 are just AF1 and AF2.

data/registers/timer_l0.yaml

@@ -44,6 +44,11 @@ block/TIM_1CH:
       stride: 4
     byte_offset: 52
     fieldset: CCR_1CH
+  - name: OR
+    description: |-
+      Option register 1
+      Note: Check Reference Manual to parse this register content
+    byte_offset: 80
 block/TIM_2CH:
   extends: TIM_1CH
   description: 2-channel timers

data/registers/timer_v1.yaml

@@ -44,6 +44,11 @@ block/TIM_1CH:
       stride: 4
     byte_offset: 52
     fieldset: CCR_1CH
+  - name: OR
+    description: |-
+      Option register 1
+      Note: Check Reference Manual to parse this register content
+    byte_offset: 80
   - name: TISEL
     description: input selection register
     byte_offset: 104

data/registers/timer_v2.yaml

@@ -55,6 +55,11 @@ block/TIM_1CH:
     description: input selection register
     byte_offset: 92
     fieldset: TISEL_1CH
+  - name: OR
+    description: |-
+      Option register 1
+      Note: Check Reference Manual to parse this register content
+    byte_offset: 104
 block/TIM_1CH_CMP:
   extends: TIM_1CH
   description: 1-channel with one complementary output timers