From e8573898509760027c9f4cc3c621fb215a45d4d4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Mon, 5 Feb 2024 15:40:49 +0800 Subject: [PATCH] Add OR register. OR1 is the same as OR. The content is different across chip serials. Leave entire register to HAL to parse. OR2 and OR3 are just AF1 and AF2. --- data/registers/timer_l0.yaml | 5 +++++ data/registers/timer_v1.yaml | 5 +++++ data/registers/timer_v2.yaml | 5 +++++ 3 files changed, 15 insertions(+) diff --git a/data/registers/timer_l0.yaml b/data/registers/timer_l0.yaml index 43c28c3..d1d4d45 100644 --- a/data/registers/timer_l0.yaml +++ b/data/registers/timer_l0.yaml @@ -44,6 +44,11 @@ block/TIM_1CH: stride: 4 byte_offset: 52 fieldset: CCR_1CH + - name: OR + description: |- + Option register 1 + Note: Check Reference Manual to parse this register content + byte_offset: 80 block/TIM_2CH: extends: TIM_1CH description: 2-channel timers diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index b54bcff..b2f9d59 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -44,6 +44,11 @@ block/TIM_1CH: stride: 4 byte_offset: 52 fieldset: CCR_1CH + - name: OR + description: |- + Option register 1 + Note: Check Reference Manual to parse this register content + byte_offset: 80 - name: TISEL description: input selection register byte_offset: 104 diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml index 28de6a5..691f7ec 100644 --- a/data/registers/timer_v2.yaml +++ b/data/registers/timer_v2.yaml @@ -55,6 +55,11 @@ block/TIM_1CH: description: input selection register byte_offset: 92 fieldset: TISEL_1CH + - name: OR + description: |- + Option register 1 + Note: Check Reference Manual to parse this register content + byte_offset: 104 block/TIM_1CH_CMP: extends: TIM_1CH description: 1-channel with one complementary output timers