Add Flash, RTC, PWR for STM32WB55, fix IPCC CPU registers

data/extra/family/STM32WB.yaml

@@ -2,3 +2,6 @@ peripherals:
     VREFINTCAL: 
         address: 0x1FFF75AA
         block: vrefintcal_v1/VREFINTCAL
+    FLASH:
+        address: 0x58004000
+        block: flash_wb55/FLASH

data/registers/flash_wb55.yaml

@@ -0,0 +1,559 @@
+---
+block/FLASH:
+  description: Flash
+  items:
+  - byte_offset: 0
+    description: Access control register
+    fieldset: ACR
+    name: ACR
+  - access: Write
+    byte_offset: 8
+    description: Flash key register
+    fieldset: KEYR
+    name: KEYR
+  - access: Write
+    byte_offset: 12
+    description: Option byte key register
+    fieldset: OPTKEYR
+    name: OPTKEYR
+  - byte_offset: 16
+    description: Status register
+    fieldset: SR
+    name: SR
+  - byte_offset: 20
+    description: Flash control register
+    fieldset: CR
+    name: CR
+  - byte_offset: 24
+    description: Flash ECC register
+    fieldset: ECCR
+    name: ECCR
+  - byte_offset: 32
+    description: Flash option register
+    fieldset: OPTR
+    name: OPTR
+  - byte_offset: 36
+    description: Flash Bank 1 PCROP Start address zone A register
+    fieldset: PCROP1ASR
+    name: PCROP1ASR
+  - byte_offset: 40
+    description: Flash Bank 1 PCROP End address zone A register
+    fieldset: PCROP1AER
+    name: PCROP1AER
+  - byte_offset: 44
+    description: Flash Bank 1 WRP area A address register
+    fieldset: WRP1AR
+    name: WRP1AR
+  - byte_offset: 48
+    description: Flash Bank 1 WRP area B address register
+    fieldset: WRP1BR
+    name: WRP1BR
+  - byte_offset: 52
+    description: Flash Bank 1 PCROP Start address area B register
+    fieldset: PCROP1BSR
+    name: PCROP1BSR
+  - byte_offset: 56
+    description: Flash Bank 1 PCROP End address area B register
+    fieldset: PCROP1BER
+    name: PCROP1BER
+  - byte_offset: 60
+    description: IPCC mailbox data buffer address register
+    fieldset: IPCCBR
+    name: IPCCBR
+  - byte_offset: 92
+    description: CPU2 cortex M0 access control register
+    fieldset: C2ACR
+    name: C2ACR
+  - byte_offset: 96
+    description: CPU2 cortex M0 status register
+    fieldset: C2SR
+    name: C2SR
+  - byte_offset: 100
+    description: CPU2 cortex M0 control register
+    fieldset: C2CR
+    name: C2CR
+  - byte_offset: 128
+    description: Secure flash start address register
+    fieldset: SFR
+    name: SFR
+  - byte_offset: 132
+    description: Secure SRAM2 start address and cortex M0 reset vector register
+    fieldset: SRRVR
+    name: SRRVR
+fieldset/ACR:
+  description: Access control register
+  fields:
+  - bit_offset: 0
+    bit_size: 3
+    description: Latency
+    name: LATENCY
+  - bit_offset: 8
+    bit_size: 1
+    description: Prefetch enable
+    name: PRFTEN
+  - bit_offset: 9
+    bit_size: 1
+    description: Instruction cache enable
+    name: ICEN
+  - bit_offset: 10
+    bit_size: 1
+    description: Data cache enable
+    name: DCEN
+  - bit_offset: 11
+    bit_size: 1
+    description: Instruction cache reset
+    name: ICRST
+  - bit_offset: 12
+    bit_size: 1
+    description: Data cache reset
+    name: DCRST
+  - bit_offset: 15
+    bit_size: 1
+    description: CPU1 CortexM4 program erase suspend request
+    name: PES
+  - bit_offset: 16
+    bit_size: 1
+    description: Flash User area empty
+    name: EMPTY
+fieldset/C2ACR:
+  description: CPU2 cortex M0 access control register
+  fields:
+  - bit_offset: 8
+    bit_size: 1
+    description: CPU2 cortex M0 prefetch enable
+    name: PRFTEN
+  - bit_offset: 9
+    bit_size: 1
+    description: CPU2 cortex M0 instruction cache enable
+    name: ICEN
+  - bit_offset: 11
+    bit_size: 1
+    description: CPU2 cortex M0 instruction cache reset
+    name: ICRST
+  - bit_offset: 15
+    bit_size: 1
+    description: CPU2 cortex M0 program erase suspend request
+    name: PES
+fieldset/C2CR:
+  description: CPU2 cortex M0 control register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Programming
+    name: PG
+  - bit_offset: 1
+    bit_size: 1
+    description: Page erase
+    name: PER
+  - bit_offset: 2
+    bit_size: 1
+    description: Masse erase
+    name: MER
+  - bit_offset: 3
+    bit_size: 8
+    description: Page Number selection
+    name: PNB
+  - bit_offset: 16
+    bit_size: 1
+    description: Start
+    name: STRT
+  - bit_offset: 18
+    bit_size: 1
+    description: Fast programming
+    name: FSTPG
+  - bit_offset: 24
+    bit_size: 1
+    description: End of operation interrupt enable
+    name: EOPIE
+  - bit_offset: 25
+    bit_size: 1
+    description: Error interrupt enable
+    name: ERRIE
+  - bit_offset: 26
+    bit_size: 1
+    description: PCROP read error interrupt enable
+    name: RDERRIE
+fieldset/C2SR:
+  description: CPU2 cortex M0 status register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: End of operation
+    name: EOP
+  - bit_offset: 1
+    bit_size: 1
+    description: Operation error
+    name: OPERR
+  - bit_offset: 3
+    bit_size: 1
+    description: Programming error
+    name: PROGERR
+  - bit_offset: 4
+    bit_size: 1
+    description: write protection error
+    name: WRPERR
+  - bit_offset: 5
+    bit_size: 1
+    description: Programming alignment error
+    name: PGAERR
+  - bit_offset: 6
+    bit_size: 1
+    description: Size error
+    name: SIZERR
+  - bit_offset: 7
+    bit_size: 1
+    description: Programming sequence error
+    name: PGSERR
+  - bit_offset: 8
+    bit_size: 1
+    description: Fast programming data miss error
+    name: MISSERR
+  - bit_offset: 9
+    bit_size: 1
+    description: Fast programming error
+    name: FASTERR
+  - bit_offset: 14
+    bit_size: 1
+    description: PCROP read error
+    name: RDERR
+  - bit_offset: 16
+    bit_size: 1
+    description: Busy
+    name: BSY
+  - bit_offset: 18
+    bit_size: 1
+    description: Programming or erase configuration busy
+    name: CFGBSY
+  - bit_offset: 19
+    bit_size: 1
+    description: Programming or erase operation suspended
+    name: PESD
+fieldset/CR:
+  description: Flash control register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Programming
+    name: PG
+  - bit_offset: 1
+    bit_size: 1
+    description: Page erase
+    name: PER
+  - bit_offset: 2
+    bit_size: 1
+    description: This bit triggers the mass erase (all user pages) when set
+    name: MER
+  - bit_offset: 3
+    bit_size: 8
+    description: Page number selection
+    name: PNB
+  - bit_offset: 16
+    bit_size: 1
+    description: Start
+    name: STRT
+  - bit_offset: 17
+    bit_size: 1
+    description: Options modification start
+    name: OPTSTRT
+  - bit_offset: 18
+    bit_size: 1
+    description: Fast programming
+    name: FSTPG
+  - bit_offset: 24
+    bit_size: 1
+    description: End of operation interrupt enable
+    name: EOPIE
+  - bit_offset: 25
+    bit_size: 1
+    description: Error interrupt enable
+    name: ERRIE
+  - bit_offset: 26
+    bit_size: 1
+    description: PCROP read error interrupt enable
+    name: RDERRIE
+  - bit_offset: 27
+    bit_size: 1
+    description: Force the option byte loading
+    name: OBL_LAUNCH
+  - bit_offset: 30
+    bit_size: 1
+    description: Options Lock
+    name: OPTLOCK
+  - bit_offset: 31
+    bit_size: 1
+    description: FLASH_CR Lock
+    name: LOCK
+fieldset/ECCR:
+  description: Flash ECC register
+  fields:
+  - bit_offset: 0
+    bit_size: 17
+    description: ECC fail address
+    name: ADDR_ECC
+  - bit_offset: 20
+    bit_size: 1
+    description: System Flash ECC fail
+    name: SYSF_ECC
+  - bit_offset: 24
+    bit_size: 1
+    description: ECC correction interrupt enable
+    name: ECCCIE
+  - bit_offset: 26
+    bit_size: 3
+    description: CPU identification
+    name: CPUID
+  - bit_offset: 30
+    bit_size: 1
+    description: ECC correction
+    name: ECCC
+  - bit_offset: 31
+    bit_size: 1
+    description: ECC detection
+    name: ECCD
+fieldset/IPCCBR:
+  description: IPCC mailbox data buffer address register
+  fields:
+  - bit_offset: 0
+    bit_size: 14
+    description: PCC mailbox data buffer base address
+    name: IPCCDBA
+fieldset/KEYR:
+  description: Flash key register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: KEYR
+    name: KEYR
+fieldset/OPTKEYR:
+  description: Option byte key register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: Option byte key
+    name: OPTKEYR
+fieldset/OPTR:
+  description: Flash option register
+  fields:
+  - bit_offset: 0
+    bit_size: 8
+    description: Read protection level
+    name: RDP
+  - bit_offset: 8
+    bit_size: 1
+    description: Security enabled
+    name: ESE
+  - bit_offset: 9
+    bit_size: 3
+    description: BOR reset Level
+    name: BOR_LEV
+  - bit_offset: 12
+    bit_size: 1
+    description: nRST_STOP
+    name: nRST_STOP
+  - bit_offset: 13
+    bit_size: 1
+    description: nRST_STDBY
+    name: nRST_STDBY
+  - bit_offset: 14
+    bit_size: 1
+    description: nRST_SHDW
+    name: nRST_SHDW
+  - bit_offset: 16
+    bit_size: 1
+    description: Independent watchdog selection
+    name: IDWG_SW
+  - bit_offset: 17
+    bit_size: 1
+    description: Independent watchdog counter freeze in Stop mode
+    name: IWDG_STOP
+  - bit_offset: 18
+    bit_size: 1
+    description: Independent watchdog counter freeze in Standby mode
+    name: IWDG_STDBY
+  - bit_offset: 19
+    bit_size: 1
+    description: Window watchdog selection
+    name: WWDG_SW
+  - bit_offset: 23
+    bit_size: 1
+    description: Boot configuration
+    name: nBOOT1
+  - bit_offset: 24
+    bit_size: 1
+    description: SRAM2 parity check enable
+    name: SRAM2_PE
+  - bit_offset: 25
+    bit_size: 1
+    description: SRAM2 Erase when system reset
+    name: SRAM2_RST
+  - bit_offset: 26
+    bit_size: 1
+    description: Software Boot0
+    name: nSWBOOT0
+  - bit_offset: 27
+    bit_size: 1
+    description: nBoot0 option bit
+    name: nBOOT0
+  - bit_offset: 29
+    bit_size: 3
+    description: Radio Automatic Gain Control Trimming
+    name: AGC_TRIM
+fieldset/PCROP1AER:
+  description: Flash Bank 1 PCROP End address zone A register
+  fields:
+  - bit_offset: 0
+    bit_size: 9
+    description: Bank 1 PCROP area end offset
+    name: PCROP1A_END
+  - bit_offset: 31
+    bit_size: 1
+    description: PCROP area preserved when RDP level decreased
+    name: PCROP_RDP
+fieldset/PCROP1ASR:
+  description: Flash Bank 1 PCROP Start address zone A register
+  fields:
+  - bit_offset: 0
+    bit_size: 9
+    description: Bank 1 PCROPQ area start offset
+    name: PCROP1A_STRT
+fieldset/PCROP1BER:
+  description: Flash Bank 1 PCROP End address area B register
+  fields:
+  - bit_offset: 0
+    bit_size: 9
+    description: Bank 1 PCROP area end area B offset
+    name: PCROP1B_END
+fieldset/PCROP1BSR:
+  description: Flash Bank 1 PCROP Start address area B register
+  fields:
+  - bit_offset: 0
+    bit_size: 9
+    description: Bank 1 PCROP area B start offset
+    name: PCROP1B_STRT
+fieldset/SFR:
+  description: Secure flash start address register
+  fields:
+  - bit_offset: 0
+    bit_size: 8
+    description: Secure flash start address
+    name: SFSA
+  - bit_offset: 8
+    bit_size: 1
+    description: Flash security disable
+    name: FSD
+  - bit_offset: 12
+    bit_size: 1
+    description: Disable Cortex M0 debug access
+    name: DDS
+fieldset/SR:
+  description: Status register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: End of operation
+    name: EOP
+  - bit_offset: 1
+    bit_size: 1
+    description: Operation error
+    name: OPERR
+  - bit_offset: 3
+    bit_size: 1
+    description: Programming error
+    name: PROGERR
+  - bit_offset: 4
+    bit_size: 1
+    description: Write protected error
+    name: WRPERR
+  - bit_offset: 5
+    bit_size: 1
+    description: Programming alignment error
+    name: PGAERR
+  - bit_offset: 6
+    bit_size: 1
+    description: Size error
+    name: SIZERR
+  - bit_offset: 7
+    bit_size: 1
+    description: Programming sequence error
+    name: PGSERR
+  - bit_offset: 8
+    bit_size: 1
+    description: Fast programming data miss error
+    name: MISERR
+  - bit_offset: 9
+    bit_size: 1
+    description: Fast programming error
+    name: FASTERR
+  - bit_offset: 13
+    bit_size: 1
+    description: User Option OPTVAL indication
+    name: OPTNV
+  - bit_offset: 14
+    bit_size: 1
+    description: PCROP read error
+    name: RDERR
+  - bit_offset: 15
+    bit_size: 1
+    description: Option validity error
+    name: OPTVERR
+  - bit_offset: 16
+    bit_size: 1
+    description: Busy
+    name: BSY
+  - bit_offset: 18
+    bit_size: 1
+    description: Programming or erase configuration busy
+    name: CFGBSY
+  - bit_offset: 19
+    bit_size: 1
+    description: Programming or erase operation suspended
+    name: PESD
+fieldset/SRRVR:
+  description: Secure SRAM2 start address and cortex M0 reset vector register
+  fields:
+  - bit_offset: 0
+    bit_size: 18
+    description: cortex M0 access control register
+    name: SBRV
+  - bit_offset: 18
+    bit_size: 5
+    description: Secure backup SRAM2a start address
+    name: SBRSA
+  - bit_offset: 23
+    bit_size: 1
+    description: backup SRAM2a security disable
+    name: BRSD
+  - bit_offset: 25
+    bit_size: 5
+    description: Secure non backup SRAM2a start address
+    name: SNBRSA
+  - bit_offset: 30
+    bit_size: 1
+    description: non-backup SRAM2b security disable
+    name: NBRSD
+  - bit_offset: 31
+    bit_size: 1
+    description: CPU2 cortex M0 boot reset vector memory selection
+    name: C2OPT
+fieldset/WRP1AR:
+  description: Flash Bank 1 WRP area A address register
+  fields:
+  - bit_offset: 0
+    bit_size: 8
+    description: Bank 1 WRP first area A start offset
+    name: WRP1A_STRT
+  - bit_offset: 16
+    bit_size: 8
+    description: Bank 1 WRP first area A end offset
+    name: WRP1A_END
+fieldset/WRP1BR:
+  description: Flash Bank 1 WRP area B address register
+  fields:
+  - bit_offset: 0
+    bit_size: 8
+    description: Bank 1 WRP second area B start offset
+    name: WRP1B_END
+  - bit_offset: 16
+    bit_size: 8
+    description: Bank 1 WRP second area B end offset
+    name: WRP1B_STRT

data/registers/ipcc_v1.yaml

@@ -8,6 +8,7 @@ block/IPCC:
         len: 2
         stride: 16
       byte_offset: 0
+      block: IPCC_CPU
 block/IPCC_CPU:
   description: IPCC
   items:

data/registers/rtc_wb.yaml

@@ -0,0 +1,891 @@
+---
+block/RTC:
+  description: Real-time clock
+  items:
+  - name: TR
+    description: time register
+    byte_offset: 0
+    fieldset: TR
+  - name: DR
+    description: date register
+    byte_offset: 4
+    fieldset: DR
+  - name: CR
+    description: control register
+    byte_offset: 8
+    fieldset: CR
+  - byte_offset: 12
+    description: initialization and status register
+    fieldset: ISR
+    name: ISR
+  - byte_offset: 16
+    description: prescaler register
+    fieldset: PRER
+    name: PRER
+  - byte_offset: 20
+    description: wakeup timer register
+    fieldset: WUTR
+    name: WUTR
+  - byte_offset: 28
+    description: alarm A register
+    fieldset: ALRMAR
+    name: ALRMAR
+  - byte_offset: 32
+    description: alarm B register
+    fieldset: ALRMBR
+    name: ALRMBR
+  - access: Write
+    byte_offset: 36
+    description: write protection register
+    fieldset: WPR
+    name: WPR
+  - access: Read
+    byte_offset: 40
+    description: sub second register
+    fieldset: SSR
+    name: SSR
+  - access: Write
+    byte_offset: 44
+    description: shift control register
+    fieldset: SHIFTR
+    name: SHIFTR
+  - access: Read
+    byte_offset: 48
+    description: time stamp time register
+    fieldset: TSTR
+    name: TSTR
+  - access: Read
+    byte_offset: 52
+    description: time stamp date register
+    fieldset: TSDR
+    name: TSDR
+  - access: Read
+    byte_offset: 56
+    description: timestamp sub second register
+    fieldset: TSSSR
+    name: TSSSR
+  - byte_offset: 60
+    description: calibration register
+    fieldset: CALR
+    name: CALR
+  - byte_offset: 64
+    description: tamper configuration register
+    fieldset: TAMPCR
+    name: TAMPCR
+  - byte_offset: 68
+    description: alarm A sub second register
+    fieldset: ALRMASSR
+    name: ALRMASSR
+  - byte_offset: 72
+    description: alarm B sub second register
+    fieldset: ALRMBSSR
+    name: ALRMBSSR
+  - byte_offset: 76
+    description: option register
+    fieldset: OR
+    name: OR
+  - byte_offset: 80
+    description: backup register
+    fieldset: BKP0R
+    name: BKP0R
+  - byte_offset: 84
+    description: backup register
+    fieldset: BKP1R
+    name: BKP1R
+  - byte_offset: 88
+    description: backup register
+    fieldset: BKP2R
+    name: BKP2R
+  - byte_offset: 92
+    description: backup register
+    fieldset: BKP3R
+    name: BKP3R
+  - byte_offset: 96
+    description: backup register
+    fieldset: BKP4R
+    name: BKP4R
+  - byte_offset: 100
+    description: backup register
+    fieldset: BKP5R
+    name: BKP5R
+  - byte_offset: 104
+    description: backup register
+    fieldset: BKP6R
+    name: BKP6R
+  - byte_offset: 108
+    description: backup register
+    fieldset: BKP7R
+    name: BKP7R
+  - byte_offset: 112
+    description: backup register
+    fieldset: BKP8R
+    name: BKP8R
+  - byte_offset: 116
+    description: backup register
+    fieldset: BKP9R
+    name: BKP9R
+  - byte_offset: 120
+    description: backup register
+    fieldset: BKP10R
+    name: BKP10R
+  - byte_offset: 124
+    description: backup register
+    fieldset: BKP11R
+    name: BKP11R
+  - byte_offset: 128
+    description: backup register
+    fieldset: BKP12R
+    name: BKP12R
+  - byte_offset: 132
+    description: backup register
+    fieldset: BKP13R
+    name: BKP13R
+  - byte_offset: 136
+    description: backup register
+    fieldset: BKP14R
+    name: BKP14R
+  - byte_offset: 140
+    description: backup register
+    fieldset: BKP15R
+    name: BKP15R
+  - byte_offset: 144
+    description: backup register
+    fieldset: BKP16R
+    name: BKP16R
+  - byte_offset: 148
+    description: backup register
+    fieldset: BKP17R
+    name: BKP17R
+  - byte_offset: 152
+    description: backup register
+    fieldset: BKP18R
+    name: BKP18R
+  - byte_offset: 156
+    description: backup register
+    fieldset: BKP19R
+    name: BKP19R
+fieldset/ALRMAR:
+  description: alarm A register
+  fields:
+  - bit_offset: 0
+    bit_size: 4
+    description: Second units in BCD format
+    name: SU
+  - bit_offset: 4
+    bit_size: 3
+    description: Second tens in BCD format
+    name: ST
+  - bit_offset: 7
+    bit_size: 1
+    description: Alarm A seconds mask
+    name: MSK1
+  - bit_offset: 8
+    bit_size: 4
+    description: Minute units in BCD format
+    name: MNU
+  - bit_offset: 12
+    bit_size: 3
+    description: Minute tens in BCD format
+    name: MNT
+  - bit_offset: 15
+    bit_size: 1
+    description: Alarm A minutes mask
+    name: MSK2
+  - bit_offset: 16
+    bit_size: 4
+    description: Hour units in BCD format
+    name: HU
+  - bit_offset: 20
+    bit_size: 2
+    description: Hour tens in BCD format
+    name: HT
+  - bit_offset: 22
+    bit_size: 1
+    description: AM/PM notation
+    name: PM
+  - bit_offset: 23
+    bit_size: 1
+    description: Alarm A hours mask
+    name: MSK3
+  - bit_offset: 24
+    bit_size: 4
+    description: Date units or day in BCD format
+    name: DU
+  - bit_offset: 28
+    bit_size: 2
+    description: Date tens in BCD format
+    name: DT
+  - bit_offset: 30
+    bit_size: 1
+    description: Week day selection
+    name: WDSEL
+  - bit_offset: 31
+    bit_size: 1
+    description: Alarm A date mask
+    name: MSK4
+fieldset/ALRMASSR:
+  description: alarm A sub second register
+  fields:
+  - bit_offset: 0
+    bit_size: 15
+    description: Sub seconds value
+    name: SS
+  - bit_offset: 24
+    bit_size: 4
+    description: Mask the most-significant bits starting at this bit
+    name: MASKSS
+fieldset/ALRMBR:
+  description: alarm B register
+  fields:
+  - bit_offset: 0
+    bit_size: 4
+    description: Second units in BCD format
+    name: SU
+  - bit_offset: 4
+    bit_size: 3
+    description: Second tens in BCD format
+    name: ST
+  - bit_offset: 7
+    bit_size: 1
+    description: Alarm B seconds mask
+    name: MSK1
+  - bit_offset: 8
+    bit_size: 4
+    description: Minute units in BCD format
+    name: MNU
+  - bit_offset: 12
+    bit_size: 3
+    description: Minute tens in BCD format
+    name: MNT
+  - bit_offset: 15
+    bit_size: 1
+    description: Alarm B minutes mask
+    name: MSK2
+  - bit_offset: 16
+    bit_size: 4
+    description: Hour units in BCD format
+    name: HU
+  - bit_offset: 20
+    bit_size: 2
+    description: Hour tens in BCD format
+    name: HT
+  - bit_offset: 22
+    bit_size: 1
+    description: AM/PM notation
+    name: PM
+  - bit_offset: 23
+    bit_size: 1
+    description: Alarm B hours mask
+    name: MSK3
+  - bit_offset: 24
+    bit_size: 4
+    description: Date units or day in BCD format
+    name: DU
+  - bit_offset: 28
+    bit_size: 2
+    description: Date tens in BCD format
+    name: DT
+  - bit_offset: 30
+    bit_size: 1
+    description: Week day selection
+    name: WDSEL
+  - bit_offset: 31
+    bit_size: 1
+    description: Alarm B date mask
+    name: MSK4
+fieldset/ALRMBSSR:
+  description: alarm B sub second register
+  fields:
+  - bit_offset: 0
+    bit_size: 15
+    description: Sub seconds value
+    name: SS
+  - bit_offset: 24
+    bit_size: 4
+    description: Mask the most-significant bits starting at this bit
+    name: MASKSS
+fieldset/BKP0R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP10R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP11R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP12R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP13R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP14R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP15R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP16R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP17R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP18R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP19R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP1R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP2R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP3R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP4R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP5R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP6R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP7R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP8R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/BKP9R:
+  description: backup register
+  fields:
+  - bit_offset: 0
+    bit_size: 32
+    description: BKP
+    name: BKP
+fieldset/CALR:
+  description: calibration register
+  fields:
+  - bit_offset: 0
+    bit_size: 9
+    description: Calibration minus
+    name: CALM
+  - bit_offset: 13
+    bit_size: 1
+    description: Use a 16-second calibration cycle period
+    name: CALW16
+  - bit_offset: 14
+    bit_size: 1
+    description: Use an 8-second calibration cycle period
+    name: CALW8
+  - bit_offset: 15
+    bit_size: 1
+    description: Increase frequency of RTC by 488.5 ppm
+    name: CALP
+fieldset/CR:
+  description: control register
+  fields:
+  - bit_offset: 0
+    bit_size: 3
+    description: Wakeup clock selection
+    name: WUCKSEL
+  - bit_offset: 3
+    bit_size: 1
+    description: Time-stamp event active edge
+    name: TSEDGE
+  - bit_offset: 4
+    bit_size: 1
+    description: Reference clock detection enable (50 or 60 Hz)
+    name: REFCKON
+  - bit_offset: 5
+    bit_size: 1
+    description: Bypass the shadow registers
+    name: BYPSHAD
+  - bit_offset: 6
+    bit_size: 1
+    description: Hour format
+    name: FMT
+  - bit_offset: 8
+    bit_size: 1
+    description: Alarm A enable
+    name: ALRAE
+  - bit_offset: 9
+    bit_size: 1
+    description: Alarm B enable
+    name: ALRBE
+  - bit_offset: 10
+    bit_size: 1
+    description: Wakeup timer enable
+    name: WUTE
+  - bit_offset: 11
+    bit_size: 1
+    description: Time stamp enable
+    name: TSE
+  - bit_offset: 12
+    bit_size: 1
+    description: Alarm A interrupt enable
+    name: ALRAIE
+  - bit_offset: 13
+    bit_size: 1
+    description: Alarm B interrupt enable
+    name: ALRBIE
+  - bit_offset: 14
+    bit_size: 1
+    description: Wakeup timer interrupt enable
+    name: WUTIE
+  - bit_offset: 15
+    bit_size: 1
+    description: Time-stamp interrupt enable
+    name: TSIE
+  - bit_offset: 16
+    bit_size: 1
+    description: Add 1 hour (summer time change)
+    name: ADD1H
+  - bit_offset: 17
+    bit_size: 1
+    description: Subtract 1 hour (winter time change)
+    name: SUB1H
+  - bit_offset: 18
+    bit_size: 1
+    description: Backup
+    name: BKP
+  - bit_offset: 19
+    bit_size: 1
+    description: Calibration output selection
+    name: COSEL
+  - bit_offset: 20
+    bit_size: 1
+    description: Output polarity
+    name: POL
+  - bit_offset: 21
+    bit_size: 2
+    description: Output selection
+    name: OSEL
+  - bit_offset: 23
+    bit_size: 1
+    description: Calibration output enable
+    name: COE
+  - bit_offset: 24
+    bit_size: 1
+    description: timestamp on internal event enable
+    name: ITSE
+fieldset/DR:
+  description: date register
+  fields:
+  - bit_offset: 0
+    bit_size: 4
+    description: Date units in BCD format
+    name: DU
+  - bit_offset: 4
+    bit_size: 2
+    description: Date tens in BCD format
+    name: DT
+  - bit_offset: 8
+    bit_size: 4
+    description: Month units in BCD format
+    name: MU
+  - bit_offset: 12
+    bit_size: 1
+    description: Month tens in BCD format
+    name: MT
+  - bit_offset: 13
+    bit_size: 3
+    description: Week day units
+    name: WDU
+  - bit_offset: 16
+    bit_size: 4
+    description: Year units in BCD format
+    name: YU
+  - bit_offset: 20
+    bit_size: 4
+    description: Year tens in BCD format
+    name: YT
+fieldset/ISR:
+  description: initialization and status register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Alarm A write flag
+    name: ALRAWF
+  - bit_offset: 1
+    bit_size: 1
+    description: Alarm B write flag
+    name: ALRBWF
+  - bit_offset: 2
+    bit_size: 1
+    description: Wakeup timer write flag
+    name: WUTWF
+  - bit_offset: 3
+    bit_size: 1
+    description: Shift operation pending
+    name: SHPF
+  - bit_offset: 4
+    bit_size: 1
+    description: Initialization status flag
+    name: INITS
+  - bit_offset: 5
+    bit_size: 1
+    description: Registers synchronization flag
+    name: RSF
+  - bit_offset: 6
+    bit_size: 1
+    description: Initialization flag
+    name: INITF
+  - bit_offset: 7
+    bit_size: 1
+    description: Initialization mode
+    name: INIT
+  - bit_offset: 8
+    bit_size: 1
+    description: Alarm A flag
+    name: ALRAF
+  - bit_offset: 9
+    bit_size: 1
+    description: Alarm B flag
+    name: ALRBF
+  - bit_offset: 10
+    bit_size: 1
+    description: Wakeup timer flag
+    name: WUTF
+  - bit_offset: 11
+    bit_size: 1
+    description: Time-stamp flag
+    name: TSF
+  - bit_offset: 12
+    bit_size: 1
+    description: Time-stamp overflow flag
+    name: TSOVF
+  - bit_offset: 13
+    bit_size: 1
+    description: Tamper detection flag
+    name: TAMP1F
+  - bit_offset: 14
+    bit_size: 1
+    description: RTC_TAMP2 detection flag
+    name: TAMP2F
+  - bit_offset: 15
+    bit_size: 1
+    description: RTC_TAMP3 detection flag
+    name: TAMP3F
+  - bit_offset: 16
+    bit_size: 1
+    description: Recalibration pending Flag
+    name: RECALPF
+  - bit_offset: 17
+    bit_size: 1
+    description: INTERNAL TIME-STAMP FLAG
+    name: ITSF
+fieldset/OR:
+  description: option register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: RTC_ALARM on PC13 output type
+    name: RTC_ALARM_TYPE
+  - bit_offset: 1
+    bit_size: 1
+    description: RTC_OUT remap
+    name: RTC_OUT_RMP
+fieldset/PRER:
+  description: prescaler register
+  fields:
+  - bit_offset: 0
+    bit_size: 15
+    description: Synchronous prescaler factor
+    name: PREDIV_S
+  - bit_offset: 16
+    bit_size: 7
+    description: Asynchronous prescaler factor
+    name: PREDIV_A
+fieldset/SHIFTR:
+  description: shift control register
+  fields:
+  - bit_offset: 0
+    bit_size: 15
+    description: Subtract a fraction of a second
+    name: SUBFS
+  - bit_offset: 31
+    bit_size: 1
+    description: Add one second
+    name: ADD1S
+fieldset/SSR:
+  description: sub second register
+  fields:
+  - bit_offset: 0
+    bit_size: 16
+    description: Sub second value
+    name: SS
+fieldset/TAMPCR:
+  description: tamper configuration register
+  fields:
+  - bit_offset: 0
+    bit_size: 1
+    description: Tamper 1 detection enable
+    name: TAMP1E
+  - bit_offset: 1
+    bit_size: 1
+    description: Active level for tamper 1
+    name: TAMP1TRG
+  - bit_offset: 2
+    bit_size: 1
+    description: Tamper interrupt enable
+    name: TAMPIE
+  - bit_offset: 3
+    bit_size: 1
+    description: Tamper 2 detection enable
+    name: TAMP2E
+  - bit_offset: 4
+    bit_size: 1
+    description: Active level for tamper 2
+    name: TAMP2TRG
+  - bit_offset: 5
+    bit_size: 1
+    description: Tamper 3 detection enable
+    name: TAMP3E
+  - bit_offset: 6
+    bit_size: 1
+    description: Active level for tamper 3
+    name: TAMP3TRG
+  - bit_offset: 7
+    bit_size: 1
+    description: Activate timestamp on tamper detection event
+    name: TAMPTS
+  - bit_offset: 8
+    bit_size: 3
+    description: Tamper sampling frequency
+    name: TAMPFREQ
+  - bit_offset: 11
+    bit_size: 2
+    description: Tamper filter count
+    name: TAMPFLT
+  - bit_offset: 13
+    bit_size: 2
+    description: Tamper precharge duration
+    name: TAMPPRCH
+  - bit_offset: 15
+    bit_size: 1
+    description: TAMPER pull-up disable
+    name: TAMPPUDIS
+  - bit_offset: 16
+    bit_size: 1
+    description: Tamper 1 interrupt enable
+    name: TAMP1IE
+  - bit_offset: 17
+    bit_size: 1
+    description: Tamper 1 no erase
+    name: TAMP1NOERASE
+  - bit_offset: 18
+    bit_size: 1
+    description: Tamper 1 mask flag
+    name: TAMP1MF
+  - bit_offset: 19
+    bit_size: 1
+    description: Tamper 2 interrupt enable
+    name: TAMP2IE
+  - bit_offset: 20
+    bit_size: 1
+    description: Tamper 2 no erase
+    name: TAMP2NOERASE
+  - bit_offset: 21
+    bit_size: 1
+    description: Tamper 2 mask flag
+    name: TAMP2MF
+  - bit_offset: 22
+    bit_size: 1
+    description: Tamper 3 interrupt enable
+    name: TAMP3IE
+  - bit_offset: 23
+    bit_size: 1
+    description: Tamper 3 no erase
+    name: TAMP3NOERASE
+  - bit_offset: 24
+    bit_size: 1
+    description: Tamper 3 mask flag
+    name: TAMP3MF
+fieldset/TR:
+  description: time register
+  fields:
+  - bit_offset: 0
+    bit_size: 4
+    description: Second units in BCD format
+    name: SU
+  - bit_offset: 4
+    bit_size: 3
+    description: Second tens in BCD format
+    name: ST
+  - bit_offset: 8
+    bit_size: 4
+    description: Minute units in BCD format
+    name: MNU
+  - bit_offset: 12
+    bit_size: 3
+    description: Minute tens in BCD format
+    name: MNT
+  - bit_offset: 16
+    bit_size: 4
+    description: Hour units in BCD format
+    name: HU
+  - bit_offset: 20
+    bit_size: 2
+    description: Hour tens in BCD format
+    name: HT
+  - bit_offset: 22
+    bit_size: 1
+    description: AM/PM notation
+    name: PM
+fieldset/TSDR:
+  description: time stamp date register
+  fields:
+  - bit_offset: 0
+    bit_size: 4
+    description: Date units in BCD format
+    name: DU
+  - bit_offset: 4
+    bit_size: 2
+    description: Date tens in BCD format
+    name: DT
+  - bit_offset: 8
+    bit_size: 4
+    description: Month units in BCD format
+    name: MU
+  - bit_offset: 12
+    bit_size: 1
+    description: Month tens in BCD format
+    name: MT
+  - bit_offset: 13
+    bit_size: 3
+    description: Week day units
+    name: WDU
+fieldset/TSSSR:
+  description: timestamp sub second register
+  fields:
+  - bit_offset: 0
+    bit_size: 16
+    description: Sub second value
+    name: SS
+fieldset/TSTR:
+  description: time stamp time register
+  fields:
+  - bit_offset: 0
+    bit_size: 4
+    description: Second units in BCD format
+    name: SU
+  - bit_offset: 4
+    bit_size: 3
+    description: Second tens in BCD format
+    name: ST
+  - bit_offset: 8
+    bit_size: 4
+    description: Minute units in BCD format
+    name: MNU
+  - bit_offset: 12
+    bit_size: 3
+    description: Minute tens in BCD format
+    name: MNT
+  - bit_offset: 16
+    bit_size: 4
+    description: Hour units in BCD format
+    name: HU
+  - bit_offset: 20
+    bit_size: 2
+    description: Hour tens in BCD format
+    name: HT
+  - bit_offset: 22
+    bit_size: 1
+    description: AM/PM notation
+    name: PM
+fieldset/WPR:
+  description: write protection register
+  fields:
+  - bit_offset: 0
+    bit_size: 8
+    description: Write protection key
+    name: KEY
+fieldset/WUTR:
+  description: wakeup timer register
+  fields:
+  - bit_offset: 0
+    bit_size: 16
+    description: Wakeup auto-reload value bits
+    name: WUT

stm32data/__main__.py

@@ -148,6 +148,7 @@ perimap = [
     ('.*:MDIOS:mdios1_v1_0', 'mdios_v1/MDIOS'),
     ('.*:QUADSPI:quadspi1_v1_0', 'quadspi_v1/QUADSPI'),
     ('.*:RTC:rtc2_v2_6', 'rtc_v2/RTC'),
+    ('.*:RTC:rtc2_v2_WB', 'rtc_wb/RTC'),
     ('.*:SAI:sai1_v1_1', 'sai_v1/SAI'),
     ('.*:SDMMC:sdmmc_v1_3', 'sdmmc_v1/SDMMC'),
     ('.*:SPDIFRX:spdifrx1_v1_0', 'spdifrx_v1/SPDIFRX'),
@@ -200,6 +201,7 @@ perimap = [
     ('STM32L1.*:PWR:.*', 'pwr_l1/PWR'),
     ('STM32U5.*:PWR:.*', 'pwr_u5/PWR'),
     ('STM32WL.*:PWR:.*', 'pwr_wl5/PWR'),
+    ('STM32WB.*:PWR:.*', 'pwr_wb55/PWR'),
     ('STM32H7.*:FLASH:.*', 'flash_h7/FLASH'),
     ('STM32F0.*:FLASH:.*', 'flash_f0/FLASH'),
     ('STM32F1.*:FLASH:.*', 'flash_f1/FLASH'),
@@ -208,6 +210,7 @@ perimap = [
     ('STM32F7.*:FLASH:.*', 'flash_f7/FLASH'),
     ('STM32L4.*:FLASH:.*', 'flash_l4/FLASH'),
     ('STM32U5.*:FLASH:.*', 'flash_u5/FLASH'),
+    ('STM32WB.*:FLASH:.*', 'flash_wb55/FLASH'),
     ('STM32F7.*:ETH:ETH:ethermac110_v2_0', 'eth_v1c/ETH'),
     ('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'),