guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fix ADC, DAC clock muxes for H5, U5

Browse Source 
the clock selection bit is named ADCDACSEL, shared between all ADCs and
DACs
This commit is contained in:
Torin Cooper-Bennun 2024-03-04 10:52:06 +00:00
parent e7f91751fb
commit d1f376978d
3 changed files with 15 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
data/registers/rcc_h5.yaml
View File

@ -2114,7 +2114,7 @@ fieldset/SECCFGR:
enum/ADCDACSEL: enum/ADCDACSEL:
bit_size: 3 bit_size: 3
variants: variants:
- name: HCLK1 - name: HCLK2
description: rcc_hclk selected as kernel clock (default after reset) description: rcc_hclk selected as kernel clock (default after reset)
value: 0 value: 0
- name: SYS - name: SYS

2
data/registers/rcc_h50.yaml
View File

@ -1335,7 +1335,7 @@ fieldset/RSR:
enum/ADCDACSEL: enum/ADCDACSEL:
bit_size: 3 bit_size: 3
variants: variants:
- name: HCLK1 - name: HCLK2
description: rcc_hclk selected as kernel clock (default after reset) description: rcc_hclk selected as kernel clock (default after reset)
value: 0 value: 0
- name: SYS - name: SYS

23
stm32-data-gen/src/rcc.rs
View File

@ -255,15 +255,15 @@ impl ParsedRccs {
("PSSI", &["DCMI_PSSI"]), ("PSSI", &["DCMI_PSSI"]),
("FDCAN1", &["FDCAN12"]), ("FDCAN1", &["FDCAN12"]),
("FDCAN2", &["FDCAN12"]), ("FDCAN2", &["FDCAN12"]),
("ADC", &["ADC1"]), ("ADC", &["ADC1", "ADCDAC"]),
("ADC1", &["ADC12"]), ("ADC1", &["ADC12", "ADCDAC"]),
("ADC2", &["ADC12"]), ("ADC2", &["ADC12", "ADCDAC"]),
("ADC3", &["ADC34", "ADC345"]), ("ADC3", &["ADC34", "ADC345", "ADCDAC"]),
("ADC4", &["ADC34", "ADC345"]), ("ADC4", &["ADC34", "ADC345", "ADCDAC"]),
("ADC5", &["ADC345"]), ("ADC5", &["ADC345", "ADCDAC"]),
("DAC", &["DAC1"]), ("DAC", &["DAC1", "ADCDAC"]),
("DAC1", &["DAC12"]), ("DAC1", &["DAC12", "ADCDAC"]),
("DAC2", &["DAC12"]), ("DAC2", &["DAC12", "ADCDAC"]),
("ETH", &["ETHMAC", "ETH1MAC"]), ("ETH", &["ETHMAC", "ETH1MAC"]),
("SPI1", &["SPI12", "SPI123"]), ("SPI1", &["SPI12", "SPI123"]),
("SPI2", &["SPI12", "SPI123"]), ("SPI2", &["SPI12", "SPI123"]),
@ -307,7 +307,10 @@ impl ParsedRccs {
let kernel_clock = match mux { let kernel_clock = match mux {
Some(mux) => { Some(mux) => {
// check for mismatch between mux and bus clock. // check for mismatch between mux and bus clock.
if phclk.is_match(&en_rst.bus_clock) { //
// U5 has one ADCDACSEL for multiple ADCs which may be on
// different HCLKs, so we skip the check in that case
if !(rcc_version == "u5" && peri_name.starts_with("ADC")) && phclk.is_match(&en_rst.bus_clock) {
for v in &mux.variants { for v in &mux.variants {
if phclk.is_match(v) && v != &maybe_kernel_clock { if phclk.is_match(v) && v != &maybe_kernel_clock {
panic!( panic!(