diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml
index a1eed1d..17041c7 100644
--- a/data/registers/rcc_h5.yaml
+++ b/data/registers/rcc_h5.yaml
@@ -2114,7 +2114,7 @@ fieldset/SECCFGR:
 enum/ADCDACSEL:
   bit_size: 3
   variants:
-  - name: HCLK1
+  - name: HCLK2
     description: rcc_hclk selected as kernel clock (default after reset)
     value: 0
   - name: SYS
diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml
index 2bedff9..4309016 100644
--- a/data/registers/rcc_h50.yaml
+++ b/data/registers/rcc_h50.yaml
@@ -1335,7 +1335,7 @@ fieldset/RSR:
 enum/ADCDACSEL:
   bit_size: 3
   variants:
-  - name: HCLK1
+  - name: HCLK2
     description: rcc_hclk selected as kernel clock (default after reset)
     value: 0
   - name: SYS
diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs
index 9a6236e..60c2947 100644
--- a/stm32-data-gen/src/rcc.rs
+++ b/stm32-data-gen/src/rcc.rs
@@ -255,15 +255,15 @@ impl ParsedRccs {
             ("PSSI", &["DCMI_PSSI"]),
             ("FDCAN1", &["FDCAN12"]),
             ("FDCAN2", &["FDCAN12"]),
-            ("ADC", &["ADC1"]),
-            ("ADC1", &["ADC12"]),
-            ("ADC2", &["ADC12"]),
-            ("ADC3", &["ADC34", "ADC345"]),
-            ("ADC4", &["ADC34", "ADC345"]),
-            ("ADC5", &["ADC345"]),
-            ("DAC", &["DAC1"]),
-            ("DAC1", &["DAC12"]),
-            ("DAC2", &["DAC12"]),
+            ("ADC", &["ADC1", "ADCDAC"]),
+            ("ADC1", &["ADC12", "ADCDAC"]),
+            ("ADC2", &["ADC12", "ADCDAC"]),
+            ("ADC3", &["ADC34", "ADC345", "ADCDAC"]),
+            ("ADC4", &["ADC34", "ADC345", "ADCDAC"]),
+            ("ADC5", &["ADC345", "ADCDAC"]),
+            ("DAC", &["DAC1", "ADCDAC"]),
+            ("DAC1", &["DAC12", "ADCDAC"]),
+            ("DAC2", &["DAC12", "ADCDAC"]),
             ("ETH", &["ETHMAC", "ETH1MAC"]),
             ("SPI1", &["SPI12", "SPI123"]),
             ("SPI2", &["SPI12", "SPI123"]),
@@ -307,7 +307,10 @@ impl ParsedRccs {
         let kernel_clock = match mux {
             Some(mux) => {
                 // check for mismatch between mux and bus clock.
-                if phclk.is_match(&en_rst.bus_clock) {
+                //
+                // U5 has one ADCDACSEL for multiple ADCs which may be on
+                // different HCLKs, so we skip the check in that case
+                if !(rcc_version == "u5" && peri_name.starts_with("ADC")) && phclk.is_match(&en_rst.bus_clock) {
                     for v in &mux.variants {
                         if phclk.is_match(v) && v != &maybe_kernel_clock {
                             panic!(