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Merge pull request #112 from VasanthakumarV/f3-timers

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Assign correct register blocks for F3 Timers
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Dario Nieuwenhuis 2021-12-23 11:46:55 +01:00 committed by GitHub
commit ce7607e119
1 changed files with 5 additions and 0 deletions
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stm32data/__main__.py
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@ -220,6 +220,11 @@ perimap = [
('STM32H7.*:TIM6:.*', 'timer_v1/TIM_BASIC'), ('STM32H7.*:TIM6:.*', 'timer_v1/TIM_BASIC'),
('STM32H7.*:TIM7:.*', 'timer_v1/TIM_BASIC'), ('STM32H7.*:TIM7:.*', 'timer_v1/TIM_BASIC'),
('STM32H7.*:TIM8:.*', 'timer_v1/TIM_ADV'), ('STM32H7.*:TIM8:.*', 'timer_v1/TIM_ADV'),
('STM32F3.*:TIM(6|7){1}:.*', 'timer_v1/TIM_BASIC'),
('STM32F3.*:TIM(3|4|15|16|17){1}:.*', 'timer_v1/TIM_GP16'),
('STM32F3.*:TIM2:.*', 'timer_v1/TIM_GP32'),
('STM32F3.*:TIM(1|8|20){1}:.*', 'timer_v1/TIM_ADV'),
('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'), ('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'),
('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'), ('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'),