From a5008c71d5e381a694223bda82231cbbd40b86f2 Mon Sep 17 00:00:00 2001 From: VasanthakumarV Date: Thu, 23 Dec 2021 15:59:58 +0530 Subject: [PATCH] [manual] Map register blocks to timers for F3 chips --- stm32data/__main__.py | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/stm32data/__main__.py b/stm32data/__main__.py index 1f51fb5..fbf664d 100755 --- a/stm32data/__main__.py +++ b/stm32data/__main__.py @@ -220,6 +220,11 @@ perimap = [ ('STM32H7.*:TIM6:.*', 'timer_v1/TIM_BASIC'), ('STM32H7.*:TIM7:.*', 'timer_v1/TIM_BASIC'), ('STM32H7.*:TIM8:.*', 'timer_v1/TIM_ADV'), + + ('STM32F3.*:TIM(6|7){1}:.*', 'timer_v1/TIM_BASIC'), + ('STM32F3.*:TIM(3|4|15|16|17){1}:.*', 'timer_v1/TIM_GP16'), + ('STM32F3.*:TIM2:.*', 'timer_v1/TIM_GP32'), + ('STM32F3.*:TIM(1|8|20){1}:.*', 'timer_v1/TIM_ADV'), ('STM32F7.*:TIM1:.*', 'timer_v1/TIM_ADV'), ('STM32F7.*:TIM8:.*', 'timer_v1/TIM_ADV'),