Merge branch 'embassy-rs:main' into cryp

data/registers/hash_v1.yaml

@@ -0,0 +1,113 @@
+block/HASH:
+  description: Hash processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: DIN
+    description: data input register.
+    byte_offset: 4
+    access: Write
+  - name: STR
+    description: start register.
+    byte_offset: 8
+    access: Write
+    fieldset: STR
+  - name: HR
+    description: digest registers.
+    array:
+      len: 5
+      stride: 4
+    byte_offset: 12
+    access: Read
+  - name: IMR
+    description: interrupt enable register.
+    byte_offset: 32
+    fieldset: IMR
+  - name: SR
+    description: status register.
+    byte_offset: 36
+    fieldset: SR
+  - name: CSR
+    description: context swap registers.
+    array:
+      len: 51
+      stride: 4
+    byte_offset: 248
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: INIT
+    description: Initialize message digest calculation.
+    bit_offset: 2
+    bit_size: 1
+  - name: DMAE
+    description: DMA enable.
+    bit_offset: 3
+    bit_size: 1
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 4
+    bit_size: 2
+  - name: MODE
+    description: Mode selection.
+    bit_offset: 6
+    bit_size: 1
+  - name: ALGO
+    description: Algorithm selection.
+    bit_offset: 7
+    bit_size: 1
+  - name: NBW
+    description: Number of words already pushed.
+    bit_offset: 8
+    bit_size: 4
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 12
+    bit_size: 1
+  - name: LKEY
+    description: Long key selection.
+    bit_offset: 16
+    bit_size: 1
+fieldset/IMR:
+  description: interrupt enable register.
+  fields:
+  - name: DINIE
+    description: Data input interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIE
+    description: Digest calculation completion interrupt enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: DINIS
+    description: Data input interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIS
+    description: Digest calculation completion interrupt status.
+    bit_offset: 1
+    bit_size: 1
+  - name: DMAS
+    description: DMA Status.
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 3
+    bit_size: 1
+fieldset/STR:
+  description: start register.
+  fields:
+  - name: NBLW
+    description: Number of valid bits in the last word of the message.
+    bit_offset: 0
+    bit_size: 5
+  - name: DCAL
+    description: Digest calculation.
+    bit_offset: 8
+    bit_size: 1

data/registers/hash_v2.yaml

@@ -0,0 +1,127 @@
+block/HASH:
+  description: Hash processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: DIN
+    description: data input register.
+    byte_offset: 4
+    access: Write
+  - name: STR
+    description: start register.
+    byte_offset: 8
+    fieldset: STR
+  - name: HRA
+    description: digest registers.
+    array:
+      len: 5
+      stride: 4
+    byte_offset: 12
+    access: Read
+  - name: IMR
+    description: interrupt enable register.
+    byte_offset: 32
+    fieldset: IMR
+  - name: SR
+    description: status register.
+    byte_offset: 36
+    fieldset: SR
+  - name: CSR
+    description: context swap registers.
+    array:
+      len: 54
+      stride: 4
+    byte_offset: 248
+  - name: HR
+    description: HASH digest register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 784
+    access: Read
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: INIT
+    description: Initialize message digest calculation.
+    bit_offset: 2
+    bit_size: 1
+  - name: DMAE
+    description: DMA enable.
+    bit_offset: 3
+    bit_size: 1
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 4
+    bit_size: 2
+  - name: MODE
+    description: Mode selection.
+    bit_offset: 6
+    bit_size: 1
+  - name: ALGO0
+    description: Algorithm selection.
+    bit_offset: 7
+    bit_size: 1
+  - name: NBW
+    description: Number of words already pushed.
+    bit_offset: 8
+    bit_size: 4
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 12
+    bit_size: 1
+  - name: MDMAT
+    description: Multiple DMA Transfers.
+    bit_offset: 13
+    bit_size: 1
+  - name: LKEY
+    description: Long key selection.
+    bit_offset: 16
+    bit_size: 1
+  - name: ALGO1
+    description: ALGO.
+    bit_offset: 18
+    bit_size: 1
+fieldset/IMR:
+  description: interrupt enable register.
+  fields:
+  - name: DINIE
+    description: Data input interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIE
+    description: Digest calculation completion interrupt enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: DINIS
+    description: Data input interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIS
+    description: Digest calculation completion interrupt status.
+    bit_offset: 1
+    bit_size: 1
+  - name: DMAS
+    description: DMA Status.
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 3
+    bit_size: 1
+fieldset/STR:
+  description: start register.
+  fields:
+  - name: NBLW
+    description: Number of valid bits in the last word of the message.
+    bit_offset: 0
+    bit_size: 5
+  - name: DCAL
+    description: Digest calculation.
+    bit_offset: 8
+    bit_size: 1

data/registers/hash_v3.yaml

@@ -0,0 +1,135 @@
+block/HASH:
+  description: Hash processor.
+  items:
+  - name: CR
+    description: control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: DIN
+    description: data input register.
+    byte_offset: 4
+    access: Write
+  - name: STR
+    description: start register.
+    byte_offset: 8
+    fieldset: STR
+  - name: HRA
+    description: digest registers.
+    array:
+      len: 5
+      stride: 4
+    byte_offset: 12
+    access: Read
+  - name: IMR
+    description: interrupt enable register.
+    byte_offset: 32
+    fieldset: IMR
+  - name: SR
+    description: status register.
+    byte_offset: 36
+    fieldset: SR
+  - name: CSR
+    description: context swap registers.
+    array:
+      len: 54
+      stride: 4
+    byte_offset: 248
+  - name: HR
+    description: HASH digest register.
+    array:
+      len: 8
+      stride: 4
+    byte_offset: 784
+    access: Read
+fieldset/CR:
+  description: control register.
+  fields:
+  - name: INIT
+    description: Initialize message digest calculation.
+    bit_offset: 2
+    bit_size: 1
+  - name: DMAE
+    description: DMA enable.
+    bit_offset: 3
+    bit_size: 1
+  - name: DATATYPE
+    description: Data type selection.
+    bit_offset: 4
+    bit_size: 2
+  - name: MODE
+    description: Mode selection.
+    bit_offset: 6
+    bit_size: 1
+  - name: NBW
+    description: Number of words already pushed.
+    bit_offset: 8
+    bit_size: 4
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 12
+    bit_size: 1
+  - name: MDMAT
+    description: Multiple DMA Transfers.
+    bit_offset: 13
+    bit_size: 1
+  - name: LKEY
+    description: Long key selection.
+    bit_offset: 16
+    bit_size: 1
+  - name: ALGO
+    description: Algorithm selection.
+    bit_offset: 17
+    bit_size: 2
+fieldset/IMR:
+  description: interrupt enable register.
+  fields:
+  - name: DINIE
+    description: Data input interrupt enable.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIE
+    description: Digest calculation completion interrupt enable.
+    bit_offset: 1
+    bit_size: 1
+fieldset/SR:
+  description: status register.
+  fields:
+  - name: DINIS
+    description: Data input interrupt status.
+    bit_offset: 0
+    bit_size: 1
+  - name: DCIS
+    description: Digest calculation completion interrupt status.
+    bit_offset: 1
+    bit_size: 1
+  - name: DMAS
+    description: DMA Status.
+    bit_offset: 2
+    bit_size: 1
+  - name: BUSY
+    description: Busy bit.
+    bit_offset: 3
+    bit_size: 1
+  - name: NBWP
+    description: Number of words already pushed.
+    bit_offset: 9
+    bit_size: 5
+  - name: DINNE
+    description: DIN not empty.
+    bit_offset: 15
+    bit_size: 1
+  - name: NBWE
+    description: Number of words expected.
+    bit_offset: 16
+    bit_size: 5
+fieldset/STR:
+  description: start register.
+  fields:
+  - name: NBLW
+    description: Number of valid bits in the last word of the message.
+    bit_offset: 0
+    bit_size: 5
+  - name: DCAL
+    description: Digest calculation.
+    bit_offset: 8
+    bit_size: 1

data/registers/rcc_h50.yaml

@@ -379,7 +379,7 @@ fieldset/APB1HENR:
     description: "LPTIM2 clock enable\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1EN
+  - name: FDCAN12EN
     description: "FDCAN1 peripheral clock enable\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -394,7 +394,7 @@ fieldset/APB1HLPENR:
     description: "LPTIM2 clock enable during sleep mode\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1LPEN
+  - name: FDCAN12LPEN
     description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -409,7 +409,7 @@ fieldset/APB1HRSTR:
     description: "LPTIM2 block reset\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1RST
+  - name: FDCAN12RST
     description: "FDCAN1 block reset\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -905,7 +905,7 @@ fieldset/CCIPR5:
     bit_offset: 4
     bit_size: 2
     enum: RNGSEL
-  - name: FDCAN1SEL
+  - name: FDCAN12SEL
     description: FDCAN1 kernel clock source selection
     bit_offset: 8
     bit_size: 2

stm32-data-gen/src/chips.rs

@@ -122,6 +122,7 @@ impl PeriMatcher {
             (".*:USART:sci3_v1_2", ("usart", "v4", "USART")),
             (".*:USART:sci3_v2_0", ("usart", "v4", "USART")),
             (".*:USART:sci3_v2_1", ("usart", "v4", "USART")),
+            (".*:UART:sci2_v1_1", ("usart", "v1", "USART")),
             (".*:UART:sci2_v1_2_F4", ("usart", "v2", "USART")),
             (".*:UART:sci2_v2_1", ("usart", "v3", "USART")),
             (".*:UART:sci2_v3_0", ("usart", "v4", "USART")),
@@ -528,6 +529,10 @@ impl PeriMatcher {
             ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")),
             ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")),
             ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")),
+            (".*:HASH:hash1_v1_0", ("hash", "v1", "HASH")),
+            (".*:HASH:hash1_v2_0", ("hash", "v2", "HASH")),
+            (".*:HASH:hash1_v2_2", ("hash", "v2", "HASH")),
+            (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")),
         ];
 
         Self {