From 6fae02614a020a890dc95d22465516573aa85389 Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Mon, 29 Jan 2024 18:48:07 -0500 Subject: [PATCH 1/4] Added hash registers and perimap. --- data/registers/hash_v1.yaml | 137 +++++++++++++++++++++++++++++ data/registers/hash_v2.yaml | 159 ++++++++++++++++++++++++++++++++++ data/registers/hash_v3.yaml | 167 ++++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 4 + 4 files changed, 467 insertions(+) create mode 100644 data/registers/hash_v1.yaml create mode 100644 data/registers/hash_v2.yaml create mode 100644 data/registers/hash_v3.yaml diff --git a/data/registers/hash_v1.yaml b/data/registers/hash_v1.yaml new file mode 100644 index 0000000..1afddec --- /dev/null +++ b/data/registers/hash_v1.yaml @@ -0,0 +1,137 @@ +block/HASH: + description: Hash processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: DIN + description: data input register. + byte_offset: 4 + access: Write + fieldset: DIN + - name: STR + description: start register. + byte_offset: 8 + access: Write + fieldset: STR + - name: HR + description: digest registers. + array: + len: 5 + stride: 4 + byte_offset: 12 + access: Read + fieldset: HR + - name: IMR + description: interrupt enable register. + byte_offset: 32 + fieldset: IMR + - name: SR + description: status register. + byte_offset: 36 + fieldset: SR + - name: CSR + description: context swap registers. + array: + len: 51 + stride: 4 + byte_offset: 248 + fieldset: CSR +fieldset/CR: + description: control register. + fields: + - name: INIT + description: Initialize message digest calculation. + bit_offset: 2 + bit_size: 1 + - name: DMAE + description: DMA enable. + bit_offset: 3 + bit_size: 1 + - name: DATATYPE + description: Data type selection. + bit_offset: 4 + bit_size: 2 + - name: MODE + description: Mode selection. + bit_offset: 6 + bit_size: 1 + - name: ALGO + description: Algorithm selection. + bit_offset: 7 + bit_size: 1 + - name: NBW + description: Number of words already pushed. + bit_offset: 8 + bit_size: 4 + - name: DINNE + description: DIN not empty. + bit_offset: 12 + bit_size: 1 + - name: LKEY + description: Long key selection. + bit_offset: 16 + bit_size: 1 +fieldset/CSR: + description: context swap registers. + fields: + - name: CSR + description: CSR0. + bit_offset: 0 + bit_size: 32 +fieldset/DIN: + description: data input register. + fields: + - name: DATAIN + description: Data input. + bit_offset: 0 + bit_size: 32 +fieldset/HR: + description: digest registers. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/IMR: + description: interrupt enable register. + fields: + - name: DINIE + description: Data input interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: DCIE + description: Digest calculation completion interrupt enable. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: DINIS + description: Data input interrupt status. + bit_offset: 0 + bit_size: 1 + - name: DCIS + description: Digest calculation completion interrupt status. + bit_offset: 1 + bit_size: 1 + - name: DMAS + description: DMA Status. + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 3 + bit_size: 1 +fieldset/STR: + description: start register. + fields: + - name: NBLW + description: Number of valid bits in the last word of the message. + bit_offset: 0 + bit_size: 5 + - name: DCAL + description: Digest calculation. + bit_offset: 8 + bit_size: 1 diff --git a/data/registers/hash_v2.yaml b/data/registers/hash_v2.yaml new file mode 100644 index 0000000..cc3e2a0 --- /dev/null +++ b/data/registers/hash_v2.yaml @@ -0,0 +1,159 @@ +block/HASH: + description: Hash processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: DIN + description: data input register. + byte_offset: 4 + access: Write + fieldset: DIN + - name: STR + description: start register. + byte_offset: 8 + fieldset: STR + - name: HRA + description: digest registers. + array: + len: 5 + stride: 4 + byte_offset: 12 + access: Read + fieldset: HRA + - name: IMR + description: interrupt enable register. + byte_offset: 32 + fieldset: IMR + - name: SR + description: status register. + byte_offset: 36 + fieldset: SR + - name: CSR + description: context swap registers. + array: + len: 54 + stride: 4 + byte_offset: 248 + fieldset: CSR + - name: HR + description: HASH digest register. + array: + len: 8 + stride: 4 + byte_offset: 784 + access: Read + fieldset: HR +fieldset/CR: + description: control register. + fields: + - name: INIT + description: Initialize message digest calculation. + bit_offset: 2 + bit_size: 1 + - name: DMAE + description: DMA enable. + bit_offset: 3 + bit_size: 1 + - name: DATATYPE + description: Data type selection. + bit_offset: 4 + bit_size: 2 + - name: MODE + description: Mode selection. + bit_offset: 6 + bit_size: 1 + - name: ALGO0 + description: Algorithm selection. + bit_offset: 7 + bit_size: 1 + - name: NBW + description: Number of words already pushed. + bit_offset: 8 + bit_size: 4 + - name: DINNE + description: DIN not empty. + bit_offset: 12 + bit_size: 1 + - name: MDMAT + description: Multiple DMA Transfers. + bit_offset: 13 + bit_size: 1 + - name: LKEY + description: Long key selection. + bit_offset: 16 + bit_size: 1 + - name: ALGO1 + description: ALGO. + bit_offset: 18 + bit_size: 1 +fieldset/CSR: + description: context swap registers. + fields: + - name: CSR + description: CSR0. + bit_offset: 0 + bit_size: 32 +fieldset/DIN: + description: data input register. + fields: + - name: DATAIN + description: Data input. + bit_offset: 0 + bit_size: 32 +fieldset/HR: + description: HASH digest register. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/HRA: + description: digest registers. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/IMR: + description: interrupt enable register. + fields: + - name: DINIE + description: Data input interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: DCIE + description: Digest calculation completion interrupt enable. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: DINIS + description: Data input interrupt status. + bit_offset: 0 + bit_size: 1 + - name: DCIS + description: Digest calculation completion interrupt status. + bit_offset: 1 + bit_size: 1 + - name: DMAS + description: DMA Status. + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 3 + bit_size: 1 +fieldset/STR: + description: start register. + fields: + - name: NBLW + description: Number of valid bits in the last word of the message. + bit_offset: 0 + bit_size: 5 + - name: DCAL + description: Digest calculation. + bit_offset: 8 + bit_size: 1 diff --git a/data/registers/hash_v3.yaml b/data/registers/hash_v3.yaml new file mode 100644 index 0000000..d8a31f6 --- /dev/null +++ b/data/registers/hash_v3.yaml @@ -0,0 +1,167 @@ +block/HASH: + description: Hash processor. + items: + - name: CR + description: control register. + byte_offset: 0 + fieldset: CR + - name: DIN + description: data input register. + byte_offset: 4 + access: Write + fieldset: DIN + - name: STR + description: start register. + byte_offset: 8 + fieldset: STR + - name: HRA + description: digest registers. + array: + len: 5 + stride: 4 + byte_offset: 12 + access: Read + fieldset: HRA + - name: IMR + description: interrupt enable register. + byte_offset: 32 + fieldset: IMR + - name: SR + description: status register. + byte_offset: 36 + fieldset: SR + - name: CSR + description: context swap registers. + array: + len: 54 + stride: 4 + byte_offset: 248 + fieldset: CSR + - name: HR + description: HASH digest register. + array: + len: 8 + stride: 4 + byte_offset: 784 + access: Read + fieldset: HR +fieldset/CR: + description: control register. + fields: + - name: INIT + description: Initialize message digest calculation. + bit_offset: 2 + bit_size: 1 + - name: DMAE + description: DMA enable. + bit_offset: 3 + bit_size: 1 + - name: DATATYPE + description: Data type selection. + bit_offset: 4 + bit_size: 2 + - name: MODE + description: Mode selection. + bit_offset: 6 + bit_size: 1 + - name: NBW + description: Number of words already pushed. + bit_offset: 8 + bit_size: 4 + - name: DINNE + description: DIN not empty. + bit_offset: 12 + bit_size: 1 + - name: MDMAT + description: Multiple DMA Transfers. + bit_offset: 13 + bit_size: 1 + - name: LKEY + description: Long key selection. + bit_offset: 16 + bit_size: 1 + - name: ALGO + description: Algorithm selection. + bit_offset: 17 + bit_size: 2 +fieldset/CSR: + description: context swap registers. + fields: + - name: CSR + description: CSR0. + bit_offset: 0 + bit_size: 32 +fieldset/DIN: + description: data input register. + fields: + - name: DATAIN + description: Data input. + bit_offset: 0 + bit_size: 32 +fieldset/HR: + description: HASH digest register. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/HRA: + description: digest registers. + fields: + - name: H + description: H0. + bit_offset: 0 + bit_size: 32 +fieldset/IMR: + description: interrupt enable register. + fields: + - name: DINIE + description: Data input interrupt enable. + bit_offset: 0 + bit_size: 1 + - name: DCIE + description: Digest calculation completion interrupt enable. + bit_offset: 1 + bit_size: 1 +fieldset/SR: + description: status register. + fields: + - name: DINIS + description: Data input interrupt status. + bit_offset: 0 + bit_size: 1 + - name: DCIS + description: Digest calculation completion interrupt status. + bit_offset: 1 + bit_size: 1 + - name: DMAS + description: DMA Status. + bit_offset: 2 + bit_size: 1 + - name: BUSY + description: Busy bit. + bit_offset: 3 + bit_size: 1 + - name: NBWP + description: Number of words already pushed. + bit_offset: 9 + bit_size: 5 + - name: DINNE + description: DIN not empty. + bit_offset: 15 + bit_size: 1 + - name: NBWE + description: Number of words expected. + bit_offset: 16 + bit_size: 5 +fieldset/STR: + description: start register. + fields: + - name: NBLW + description: Number of valid bits in the last word of the message. + bit_offset: 0 + bit_size: 5 + - name: DCAL + description: Digest calculation. + bit_offset: 8 + bit_size: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 5c7a45e..0b9df9e 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -528,6 +528,10 @@ impl PeriMatcher { ("STM32U5.*:TSC:.*", ("tsc", "v3", "TSC")), ("*:VREFINTCAL:.*", ("vrefintcal", "v1", "VREFINTCAL")), ("STM32U5.*:ADF[12]:.*", ("adf", "v1", "ADF")), + (".*:HASH:hash1_v1_0", ("hash", "v1", "HASH")), + (".*:HASH:hash1_v2_0", ("hash", "v2", "HASH")), + (".*:HASH:hash1_v2_2", ("hash", "v2", "HASH")), + (".*:HASH:hash1_v4_0", ("hash", "v3", "HASH")), ]; Self { From b14a4f1f18d2781b1aec7ee356720f645ad607e0 Mon Sep 17 00:00:00 2001 From: Carlos Barrales Ruiz Date: Tue, 30 Jan 2024 01:01:13 +0100 Subject: [PATCH 2/4] Fix UART definitions present in STM32F1 series (sci2_v1_1) --- stm32-data-gen/src/chips.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 5c7a45e..95ca041 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -122,6 +122,7 @@ impl PeriMatcher { (".*:USART:sci3_v1_2", ("usart", "v4", "USART")), (".*:USART:sci3_v2_0", ("usart", "v4", "USART")), (".*:USART:sci3_v2_1", ("usart", "v4", "USART")), + (".*:UART:sci2_v1_1", ("usart", "v1", "USART")), (".*:UART:sci2_v1_2_F4", ("usart", "v2", "USART")), (".*:UART:sci2_v2_1", ("usart", "v3", "USART")), (".*:UART:sci2_v3_0", ("usart", "v4", "USART")), From ab2bc2a739324793656ca1640e1caee2d88df72d Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Tue, 30 Jan 2024 02:22:27 +0100 Subject: [PATCH 3/4] rcc: fix h5 fdcan inconsistency. --- data/registers/rcc_h50.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index ae5d726..38dfa38 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -379,7 +379,7 @@ fieldset/APB1HENR: description: "LPTIM2 clock enable\r Set and reset by software." bit_offset: 5 bit_size: 1 - - name: FDCAN1EN + - name: FDCAN12EN description: "FDCAN1 peripheral clock enable\r Set and reset by software." bit_offset: 9 bit_size: 1 @@ -394,7 +394,7 @@ fieldset/APB1HLPENR: description: "LPTIM2 clock enable during sleep mode\r Set and reset by software." bit_offset: 5 bit_size: 1 - - name: FDCAN1LPEN + - name: FDCAN12LPEN description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software." bit_offset: 9 bit_size: 1 @@ -409,7 +409,7 @@ fieldset/APB1HRSTR: description: "LPTIM2 block reset\r Set and reset by software." bit_offset: 5 bit_size: 1 - - name: FDCAN1RST + - name: FDCAN12RST description: "FDCAN1 block reset\r Set and reset by software." bit_offset: 9 bit_size: 1 @@ -905,7 +905,7 @@ fieldset/CCIPR5: bit_offset: 4 bit_size: 2 enum: RNGSEL - - name: FDCAN1SEL + - name: FDCAN12SEL description: FDCAN1 kernel clock source selection bit_offset: 8 bit_size: 2 From 6ed714a195a342e0d7d13a446972535e661ca6fe Mon Sep 17 00:00:00 2001 From: Caleb Garrett <47389035+caleb-garrett@users.noreply.github.com> Date: Mon, 29 Jan 2024 20:46:56 -0500 Subject: [PATCH 4/4] Removed hash fieldsets for single 32-bit wide fields. --- data/registers/hash_v1.yaml | 24 ------------------------ data/registers/hash_v2.yaml | 32 -------------------------------- data/registers/hash_v3.yaml | 32 -------------------------------- 3 files changed, 88 deletions(-) diff --git a/data/registers/hash_v1.yaml b/data/registers/hash_v1.yaml index 1afddec..ef179b1 100644 --- a/data/registers/hash_v1.yaml +++ b/data/registers/hash_v1.yaml @@ -9,7 +9,6 @@ block/HASH: description: data input register. byte_offset: 4 access: Write - fieldset: DIN - name: STR description: start register. byte_offset: 8 @@ -22,7 +21,6 @@ block/HASH: stride: 4 byte_offset: 12 access: Read - fieldset: HR - name: IMR description: interrupt enable register. byte_offset: 32 @@ -37,7 +35,6 @@ block/HASH: len: 51 stride: 4 byte_offset: 248 - fieldset: CSR fieldset/CR: description: control register. fields: @@ -73,27 +70,6 @@ fieldset/CR: description: Long key selection. bit_offset: 16 bit_size: 1 -fieldset/CSR: - description: context swap registers. - fields: - - name: CSR - description: CSR0. - bit_offset: 0 - bit_size: 32 -fieldset/DIN: - description: data input register. - fields: - - name: DATAIN - description: Data input. - bit_offset: 0 - bit_size: 32 -fieldset/HR: - description: digest registers. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 fieldset/IMR: description: interrupt enable register. fields: diff --git a/data/registers/hash_v2.yaml b/data/registers/hash_v2.yaml index cc3e2a0..b80ef98 100644 --- a/data/registers/hash_v2.yaml +++ b/data/registers/hash_v2.yaml @@ -9,7 +9,6 @@ block/HASH: description: data input register. byte_offset: 4 access: Write - fieldset: DIN - name: STR description: start register. byte_offset: 8 @@ -21,7 +20,6 @@ block/HASH: stride: 4 byte_offset: 12 access: Read - fieldset: HRA - name: IMR description: interrupt enable register. byte_offset: 32 @@ -36,7 +34,6 @@ block/HASH: len: 54 stride: 4 byte_offset: 248 - fieldset: CSR - name: HR description: HASH digest register. array: @@ -44,7 +41,6 @@ block/HASH: stride: 4 byte_offset: 784 access: Read - fieldset: HR fieldset/CR: description: control register. fields: @@ -88,34 +84,6 @@ fieldset/CR: description: ALGO. bit_offset: 18 bit_size: 1 -fieldset/CSR: - description: context swap registers. - fields: - - name: CSR - description: CSR0. - bit_offset: 0 - bit_size: 32 -fieldset/DIN: - description: data input register. - fields: - - name: DATAIN - description: Data input. - bit_offset: 0 - bit_size: 32 -fieldset/HR: - description: HASH digest register. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 -fieldset/HRA: - description: digest registers. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 fieldset/IMR: description: interrupt enable register. fields: diff --git a/data/registers/hash_v3.yaml b/data/registers/hash_v3.yaml index d8a31f6..9d310d7 100644 --- a/data/registers/hash_v3.yaml +++ b/data/registers/hash_v3.yaml @@ -9,7 +9,6 @@ block/HASH: description: data input register. byte_offset: 4 access: Write - fieldset: DIN - name: STR description: start register. byte_offset: 8 @@ -21,7 +20,6 @@ block/HASH: stride: 4 byte_offset: 12 access: Read - fieldset: HRA - name: IMR description: interrupt enable register. byte_offset: 32 @@ -36,7 +34,6 @@ block/HASH: len: 54 stride: 4 byte_offset: 248 - fieldset: CSR - name: HR description: HASH digest register. array: @@ -44,7 +41,6 @@ block/HASH: stride: 4 byte_offset: 784 access: Read - fieldset: HR fieldset/CR: description: control register. fields: @@ -84,34 +80,6 @@ fieldset/CR: description: Algorithm selection. bit_offset: 17 bit_size: 2 -fieldset/CSR: - description: context swap registers. - fields: - - name: CSR - description: CSR0. - bit_offset: 0 - bit_size: 32 -fieldset/DIN: - description: data input register. - fields: - - name: DATAIN - description: Data input. - bit_offset: 0 - bit_size: 32 -fieldset/HR: - description: HASH digest register. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 -fieldset/HRA: - description: digest registers. - fields: - - name: H - description: H0. - bit_offset: 0 - bit_size: 32 fieldset/IMR: description: interrupt enable register. fields: