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This commit is contained in:
Dario Nieuwenhuis 2024-02-15 23:25:16 +01:00
parent 3a9e43b7e9
commit c8698f3cd8
2 changed files with 46 additions and 46 deletions
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16
data/registers/timer_v1.yaml
View File

@ -1438,19 +1438,19 @@ fieldset/SMCR_2CH:
- name: SMS - name: SMS
description: Slave mode selection description: Slave mode selection
bit_offset: bit_offset:
- start: 0 - start: 0
end: 2 end: 2
- start: 16 - start: 16
end: 16 end: 16
bit_size: 4 bit_size: 4
enum: SMS enum: SMS
- name: TS - name: TS
description: Trigger selection description: Trigger selection
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 20 - start: 20
end: 21 end: 21
bit_size: 5 bit_size: 5
enum: TS enum: TS
- name: MSM - name: MSM

76
data/registers/timer_v2.yaml
View File

@ -869,10 +869,10 @@ fieldset/CCMR3_ADV:
- name: OCM - name: OCM
description: Output compare x (x=5,6) mode description: Output compare x (x=5,6) mode
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 16 - start: 16
end: 16 end: 16
bit_size: 4 bit_size: 4
array: array:
len: 2 len: 2
@ -966,10 +966,10 @@ fieldset/CCMR_Output_1CH:
- name: OCM - name: OCM
description: Output compare y mode description: Output compare y mode
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 16 - start: 16
end: 16 end: 16
bit_size: 4 bit_size: 4
array: array:
len: 1 len: 1
@ -1004,10 +1004,10 @@ fieldset/CCMR_Output_2CH:
- name: OCM - name: OCM
description: Output compare y mode description: Output compare y mode
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 16 - start: 16
end: 16 end: 16
bit_size: 4 bit_size: 4
array: array:
len: 2 len: 2
@ -1209,10 +1209,10 @@ fieldset/CR2_2CH:
- name: MMS - name: MMS
description: Master mode selection description: Master mode selection
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 25 - start: 25
end: 25 end: 25
bit_size: 4 bit_size: 4
enum: MMS enum: MMS
- name: TI1S - name: TI1S
@ -1227,10 +1227,10 @@ fieldset/CR2_2CH_CMP:
- name: MMS - name: MMS
description: Master mode selection description: Master mode selection
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 25 - start: 25
end: 25 end: 25
bit_size: 4 bit_size: 4
enum: MMS enum: MMS
- name: TI1S - name: TI1S
@ -1274,10 +1274,10 @@ fieldset/CR2_BASIC:
- name: MMS - name: MMS
description: Master mode selection description: Master mode selection
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 25 - start: 25
end: 25 end: 25
bit_size: 4 bit_size: 4
enum: MMS enum: MMS
fieldset/CR2_GP16: fieldset/CR2_GP16:
@ -1646,19 +1646,19 @@ fieldset/SMCR_2CH:
- name: SMS - name: SMS
description: Slave mode selection description: Slave mode selection
bit_offset: bit_offset:
- start: 0 - start: 0
end: 2 end: 2
- start: 16 - start: 16
end: 16 end: 16
bit_size: 4 bit_size: 4
enum: SMS enum: SMS
- name: TS - name: TS
description: Trigger selection description: Trigger selection
bit_offset: bit_offset:
- start: 4 - start: 4
end: 6 end: 6
- start: 20 - start: 20
end: 21 end: 21
bit_size: 5 bit_size: 5
enum: TS enum: TS
- name: MSM - name: MSM
@ -2336,7 +2336,7 @@ enum/OCM:
description: Inversely to PwmMode1 description: Inversely to PwmMode1
value: 7 value: 7
- name: Retrigerrable_OPM_Mode_1 - name: Retrigerrable_OPM_Mode_1
description: | description: |-
In up-counting mode, the channel is active until a trigger In up-counting mode, the channel is active until a trigger
event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
mode 1 and the channels becomes active again at the next update. In down-counting mode 1 and the channels becomes active again at the next update. In down-counting
@ -2345,7 +2345,7 @@ enum/OCM:
inactive again at the next update. inactive again at the next update.
value: 8 value: 8
- name: Retrigerrable_OPM_Mode_2 - name: Retrigerrable_OPM_Mode_2
description: | description: |-
In up-counting mode, the channel is inactive until a In up-counting mode, the channel is inactive until a
trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
PWM mode 2 and the channels becomes inactive again at the next update. In down- PWM mode 2 and the channels becomes inactive again at the next update. In down-
@ -2360,23 +2360,23 @@ enum/OCM:
description: _reserved2 description: _reserved2
value: 11 value: 11
- name: Combined_PWM_Mode_1 - name: Combined_PWM_Mode_1
description: | description: |-
tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1ref has the same behavior as in PWM mode 1.
tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref. tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
value: 12 value: 12
- name: Combined_PWM_Mode_2 - name: Combined_PWM_Mode_2
description: | description: |-
tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1ref has the same behavior as in PWM mode 2.
tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref. tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
value: 13 value: 13
- name: Asymmetric_PWM_Mode_1 - name: Asymmetric_PWM_Mode_1
description: | description: |-
tim_oc1ref has the same behavior as in PWM mode 1. tim_oc1ref has the same behavior as in PWM mode 1.
tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is
counting down. counting down.
value: 14 value: 14
- name: Asymmetric_PWM_Mode_2 - name: Asymmetric_PWM_Mode_2
description: | description: |-
tim_oc1ref has the same behavior as in PWM mode 2. tim_oc1ref has the same behavior as in PWM mode 2.
tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is
counting down. counting down.