diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml
index 8c87951..6a76576 100644
--- a/data/registers/timer_v1.yaml
+++ b/data/registers/timer_v1.yaml
@@ -1438,19 +1438,19 @@ fieldset/SMCR_2CH:
   - name: SMS
     description: Slave mode selection
     bit_offset:
-      - start: 0
-        end: 2
-      - start: 16
-        end: 16
+    - start: 0
+      end: 2
+    - start: 16
+      end: 16
     bit_size: 4
     enum: SMS
   - name: TS
     description: Trigger selection
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 20
-        end: 21
+    - start: 4
+      end: 6
+    - start: 20
+      end: 21
     bit_size: 5
     enum: TS
   - name: MSM
diff --git a/data/registers/timer_v2.yaml b/data/registers/timer_v2.yaml
index 9606d57..8ba0b87 100644
--- a/data/registers/timer_v2.yaml
+++ b/data/registers/timer_v2.yaml
@@ -869,10 +869,10 @@ fieldset/CCMR3_ADV:
   - name: OCM
     description: Output compare x (x=5,6) mode
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 16
-        end: 16
+    - start: 4
+      end: 6
+    - start: 16
+      end: 16
     bit_size: 4
     array:
       len: 2
@@ -966,10 +966,10 @@ fieldset/CCMR_Output_1CH:
   - name: OCM
     description: Output compare y mode
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 16
-        end: 16
+    - start: 4
+      end: 6
+    - start: 16
+      end: 16
     bit_size: 4
     array:
       len: 1
@@ -1004,10 +1004,10 @@ fieldset/CCMR_Output_2CH:
   - name: OCM
     description: Output compare y mode
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 16
-        end: 16
+    - start: 4
+      end: 6
+    - start: 16
+      end: 16
     bit_size: 4
     array:
       len: 2
@@ -1209,10 +1209,10 @@ fieldset/CR2_2CH:
   - name: MMS
     description: Master mode selection
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 25
-        end: 25
+    - start: 4
+      end: 6
+    - start: 25
+      end: 25
     bit_size: 4
     enum: MMS
   - name: TI1S
@@ -1227,10 +1227,10 @@ fieldset/CR2_2CH_CMP:
   - name: MMS
     description: Master mode selection
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 25
-        end: 25
+    - start: 4
+      end: 6
+    - start: 25
+      end: 25
     bit_size: 4
     enum: MMS
   - name: TI1S
@@ -1274,10 +1274,10 @@ fieldset/CR2_BASIC:
   - name: MMS
     description: Master mode selection
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 25
-        end: 25
+    - start: 4
+      end: 6
+    - start: 25
+      end: 25
     bit_size: 4
     enum: MMS
 fieldset/CR2_GP16:
@@ -1646,19 +1646,19 @@ fieldset/SMCR_2CH:
   - name: SMS
     description: Slave mode selection
     bit_offset:
-      - start: 0
-        end: 2
-      - start: 16
-        end: 16
+    - start: 0
+      end: 2
+    - start: 16
+      end: 16
     bit_size: 4
     enum: SMS
   - name: TS
     description: Trigger selection
     bit_offset:
-      - start: 4
-        end: 6
-      - start: 20
-        end: 21
+    - start: 4
+      end: 6
+    - start: 20
+      end: 21
     bit_size: 5
     enum: TS
   - name: MSM
@@ -2336,7 +2336,7 @@ enum/OCM:
     description: Inversely to PwmMode1
     value: 7
   - name: Retrigerrable_OPM_Mode_1
-    description: |
+    description: |-
       In up-counting mode, the channel is active until a trigger
       event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
       mode 1 and the channels becomes active again at the next update. In down-counting
@@ -2345,7 +2345,7 @@ enum/OCM:
       inactive again at the next update.
     value: 8
   - name: Retrigerrable_OPM_Mode_2
-    description: |
+    description: |-
       In up-counting mode, the channel is inactive until a
       trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
       PWM mode 2 and the channels becomes inactive again at the next update. In down-
@@ -2360,23 +2360,23 @@ enum/OCM:
     description: _reserved2
     value: 11
   - name: Combined_PWM_Mode_1
-    description: |
+    description: |-
       tim_oc1ref has the same behavior as in PWM mode 1.
       tim_oc1refc is the logical OR between tim_oc1ref and tim_oc2ref.
     value: 12
   - name: Combined_PWM_Mode_2
-    description: |
+    description: |-
       tim_oc1ref has the same behavior as in PWM mode 2.
       tim_oc1refc is the logical AND between tim_oc1ref and tim_oc2ref.
     value: 13
   - name: Asymmetric_PWM_Mode_1
-    description: |
+    description: |-
       tim_oc1ref has the same behavior as in PWM mode 1.
       tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is
       counting down.
     value: 14
   - name: Asymmetric_PWM_Mode_2
-    description: |
+    description: |-
       tim_oc1ref has the same behavior as in PWM mode 2.
       tim_oc1refc outputs tim_oc1ref when the counter is counting up, tim_oc2ref when it is
       counting down.