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rcc: fix inconsistent naming.

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This commit is contained in:
Dario Nieuwenhuis 2022-02-14 02:07:08 +01:00
parent 2c5e858584
commit c2804abc9a
16 changed files with 34 additions and 70 deletions
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4
data/registers/rcc_f0.yaml
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@ -73,8 +73,8 @@ fieldset/AHBENR:
description: SRAM interface clock enable
bit_offset: 2
bit_size: 1
- name: FLITFEN
description: FLITF clock enable
- name: FLASHEN
description: FLASH clock enable
bit_offset: 4
bit_size: 1
- name: CRCEN

4
data/registers/rcc_f1.yaml
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@ -65,8 +65,8 @@ fieldset/AHBENR:
description: SRAM interface clock enable
bit_offset: 2
bit_size: 1
- name: FLITFEN
description: FLITF clock enable
- name: FLASHEN
description: FLASH clock enable
bit_offset: 4
bit_size: 1
- name: CRCEN

2
data/registers/rcc_f2.yaml
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@ -216,7 +216,7 @@ fieldset/AHB1LPENR:
description: CRC clock enable during Sleep mode
bit_offset: 12
bit_size: 1
- name: FLITFLPEN
- name: FLASHLPEN
description: Flash interface clock enable during Sleep mode
bit_offset: 15
bit_size: 1

4
data/registers/rcc_f3.yaml
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@ -69,8 +69,8 @@ fieldset/AHBENR:
description: SRAM interface clock enable
bit_offset: 2
bit_size: 1
- name: FLITFEN
description: FLITF clock enable
- name: FLASHEN
description: FLASH clock enable
bit_offset: 4
bit_size: 1
- name: FMCEN

4
data/registers/rcc_f4.yaml
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@ -256,7 +256,7 @@ fieldset/AHB1LPENR:
description: CRC clock enable during Sleep mode
bit_offset: 12
bit_size: 1
- name: FLITFLPEN
- name: FLASHLPEN
description: Flash interface clock enable during Sleep mode
bit_offset: 15
bit_size: 1
@ -1395,7 +1395,7 @@ fieldset/CKGATENR:
description: SRAM controller clock enable
bit_offset: 4
bit_size: 1
- name: FLITF_CKEN
- name: FLASH_CKEN
description: Flash interface clock enable
bit_offset: 5
bit_size: 1

2
data/registers/rcc_f410.yaml
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@ -132,7 +132,7 @@ fieldset/AHB1LPENR:
description: CRC clock enable during Sleep mode
bit_offset: 12
bit_size: 1
- name: FLITFLPEN
- name: FLASHLPEN
description: Flash interface clock enable during Sleep mode
bit_offset: 15
bit_size: 1

2
data/registers/rcc_f7.yaml
View File

@ -256,7 +256,7 @@ fieldset/AHB1LPENR:
description: AXI to AHB bridge clock enable during Sleep mode
bit_offset: 13
bit_size: 1
- name: FLITFLPEN
- name: FLASHLPEN
description: Flash interface clock enable during Sleep mode
bit_offset: 15
bit_size: 1

14
data/registers/rcc_g0.yaml
View File

@ -108,10 +108,6 @@ fieldset/AHBENR:
description: DMA1 clock enable
bit_offset: 0
bit_size: 1
- name: DMAEN
description: DMA clock enable
bit_offset: 0
bit_size: 1
- name: DMA2EN
description: DMA2 clock enable
bit_offset: 1
@ -139,16 +135,12 @@ fieldset/AHBRSTR:
description: DMA1 reset
bit_offset: 0
bit_size: 1
- name: DMARST
description: DMA1 reset
bit_offset: 0
bit_size: 1
- name: DMA2RST
description: DMA1 reset
bit_offset: 1
bit_size: 1
- name: FLASHRST
description: FLITF reset
description: FLASH reset
bit_offset: 8
bit_size: 1
- name: CRCRST
@ -170,10 +162,6 @@ fieldset/AHBSMENR:
description: DMA1 clock enable during Sleep mode
bit_offset: 0
bit_size: 1
- name: DMASMEN
description: DMA clock enable during Sleep mode
bit_offset: 0
bit_size: 1
- name: DMA2SMEN
description: DMA2 clock enable during Sleep mode
bit_offset: 1

6
data/registers/rcc_g4.yaml
View File

@ -135,7 +135,7 @@ fieldset/AHB1ENR:
description: DMA2 clock enable
bit_offset: 1
bit_size: 1
- name: DMAMUXEN
- name: DMAMUX1EN
description: DMAMUX clock enable
bit_offset: 2
bit_size: 1
@ -167,7 +167,7 @@ fieldset/AHB1RSTR:
bit_offset: 1
bit_size: 1
- name: DMAMUX1RST
description: DMAMUXRST
description: DMAMUX1RST
bit_offset: 2
bit_size: 1
- name: CORDICRST
@ -1264,7 +1264,7 @@ fieldset/CSR:
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
- name: LPWRSTF
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1

10
data/registers/rcc_h7.yaml
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@ -619,11 +619,7 @@ fieldset/AHB3LPENR:
bit_offset: 5
bit_size: 1
- name: FLASHLPEN
description: FLITF Clock Enable During CSleep Mode
bit_offset: 8
bit_size: 1
- name: FLITFLPEN
description: FLITF Clock Enable During CSleep Mode
description: FLASH Clock Enable During CSleep Mode
bit_offset: 8
bit_size: 1
- name: FMCLPEN
@ -3243,10 +3239,6 @@ fieldset/D3AMR:
description: Digital temperature sensor Autonomous mode enable
bit_offset: 26
bit_size: 1
- name: BKPRAMAMEN
description: Backup RAM Autonomous mode enable
bit_offset: 28
bit_size: 1
- name: BKPSRAMAMEN
description: Backup RAM Autonomous mode enable
bit_offset: 28

4
data/registers/rcc_h7ab.yaml
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@ -588,7 +588,7 @@ fieldset/AHB4ENR:
description: HSEM peripheral clock enable
bit_offset: 25
bit_size: 1
- name: BKPRAMEN
- name: BKPSRAMEN
description: Backup RAM Clock Enable
bit_offset: 28
bit_size: 1
@ -651,7 +651,7 @@ fieldset/AHB4LPENR:
description: ADC3 Peripheral Clocks Enable During CSleep Mode
bit_offset: 24
bit_size: 1
- name: BKPRAMLPEN
- name: BKPSRAMLPEN
description: Backup RAM Clock Enable During CSleep Mode
bit_offset: 28
bit_size: 1

8
data/registers/rcc_l0.yaml
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@ -418,10 +418,6 @@ fieldset/APB2ENR:
description: Firewall clock enable
bit_offset: 7
bit_size: 1
- name: MIFIEN
description: MiFaRe Firewall clock enable
bit_offset: 7
bit_size: 1
- name: ADCEN
description: ADC clock enable
bit_offset: 9
@ -876,10 +872,6 @@ fieldset/CSR:
description: Low-power reset flag
bit_offset: 31
bit_size: 1
- name: LPWRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1
fieldset/GPIOENR:
description: GPIO clock enable register
fields:

14
data/registers/rcc_l1.yaml
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@ -97,8 +97,8 @@ fieldset/AHBENR:
description: CRC clock enable
bit_offset: 12
bit_size: 1
- name: FLITFEN
description: FLITF clock enable
- name: FLASHEN
description: FLASH clock enable
bit_offset: 15
bit_size: 1
- name: DMA1EN
@ -152,8 +152,8 @@ fieldset/AHBLPENR:
description: CRC clock enable during Sleep mode
bit_offset: 12
bit_size: 1
- name: FLITFLPEN
description: FLITF clock enable during Sleep mode
- name: FLASHLPEN
description: FLASH clock enable during Sleep mode
bit_offset: 15
bit_size: 1
- name: SRAMLPEN
@ -207,8 +207,8 @@ fieldset/AHBRSTR:
description: CRC reset
bit_offset: 12
bit_size: 1
- name: FLITFRST
description: FLITF reset
- name: FLASHRST
description: FLASH reset
bit_offset: 15
bit_size: 1
- name: DMA1RST
@ -805,7 +805,7 @@ fieldset/CSR:
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
- name: LPWRSTF
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1

12
data/registers/rcc_l4.yaml
View File

@ -179,7 +179,7 @@ fieldset/AHB1RSTR:
bit_offset: 1
bit_size: 1
- name: DMAMUX1RST
description: DMAMUXRST
description: DMAMUX1RST
bit_offset: 2
bit_size: 1
- name: FLASHRST
@ -892,10 +892,6 @@ fieldset/APB2ENR:
description: SYSCFG clock enable
bit_offset: 0
bit_size: 1
- name: FIREWALLEN
description: Firewall clock enable
bit_offset: 7
bit_size: 1
- name: FWEN
description: Firewall clock enable
bit_offset: 7
@ -1535,10 +1531,6 @@ fieldset/CSR:
description: Remove reset flag
bit_offset: 23
bit_size: 1
- name: FIREWALLRSTF
description: Firewall reset flag
bit_offset: 24
bit_size: 1
- name: FWRSTF
description: Firewall reset flag
bit_offset: 24
@ -1567,7 +1559,7 @@ fieldset/CSR:
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
- name: LPWRSTF
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1

4
data/registers/rcc_l5.yaml
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@ -213,7 +213,7 @@ fieldset/AHB1RSTR:
bit_offset: 1
bit_size: 1
- name: DMAMUX1RST
description: DMAMUXRST
description: DMAMUX1RST
bit_offset: 2
bit_size: 1
- name: FLASHRST
@ -1739,7 +1739,7 @@ fieldset/CSR:
description: Window watchdog reset flag
bit_offset: 30
bit_size: 1
- name: LPWRSTF
- name: LPWRRSTF
description: Low-power reset flag
bit_offset: 31
bit_size: 1

10
data/registers/rcc_wb.yaml
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@ -207,7 +207,7 @@ fieldset/AHB1ENR:
description: DMA2 clock enable
bit_offset: 1
bit_size: 1
- name: DMAMUXEN
- name: DMAMUX1EN
description: DMAMUX clock enable
bit_offset: 2
bit_size: 1
@ -230,7 +230,7 @@ fieldset/AHB1RSTR:
description: DMA2 reset
bit_offset: 1
bit_size: 1
- name: DMAMUXRST
- name: DMAMUX1RST
description: DMAMUX reset
bit_offset: 2
bit_size: 1
@ -253,7 +253,7 @@ fieldset/AHB1SMENR:
description: CPU1 DMA2 clocks enable during Sleep and Stop modes
bit_offset: 1
bit_size: 1
- name: DMAMUXSMEN
- name: DMAMUX1SMEN
description: CPU1 DMAMUX clocks enable during Sleep and Stop modes
bit_offset: 2
bit_size: 1
@ -763,7 +763,7 @@ fieldset/C2AHB1ENR:
description: CPU2 DMA2 clock enable
bit_offset: 1
bit_size: 1
- name: DMAMUXEN
- name: DMAMUX1EN
description: CPU2 DMAMUX clock enable
bit_offset: 2
bit_size: 1
@ -790,7 +790,7 @@ fieldset/C2AHB1SMENR:
description: CPU2 DMA2 clocks enable during Sleep and Stop modes
bit_offset: 1
bit_size: 1
- name: DMAMUXSMEN
- name: DMAMUX1SMEN
description: CPU2 DMAMUX clocks enable during Sleep and Stop modes
bit_offset: 2
bit_size: 1