diff --git a/data/registers/rcc_f0.yaml b/data/registers/rcc_f0.yaml index ec88bd2..f58741a 100644 --- a/data/registers/rcc_f0.yaml +++ b/data/registers/rcc_f0.yaml @@ -73,8 +73,8 @@ fieldset/AHBENR: description: SRAM interface clock enable bit_offset: 2 bit_size: 1 - - name: FLITFEN - description: FLITF clock enable + - name: FLASHEN + description: FLASH clock enable bit_offset: 4 bit_size: 1 - name: CRCEN diff --git a/data/registers/rcc_f1.yaml b/data/registers/rcc_f1.yaml index 3ce88bc..4af8492 100644 --- a/data/registers/rcc_f1.yaml +++ b/data/registers/rcc_f1.yaml @@ -65,8 +65,8 @@ fieldset/AHBENR: description: SRAM interface clock enable bit_offset: 2 bit_size: 1 - - name: FLITFEN - description: FLITF clock enable + - name: FLASHEN + description: FLASH clock enable bit_offset: 4 bit_size: 1 - name: CRCEN diff --git a/data/registers/rcc_f2.yaml b/data/registers/rcc_f2.yaml index 662b06b..63e9555 100644 --- a/data/registers/rcc_f2.yaml +++ b/data/registers/rcc_f2.yaml @@ -216,7 +216,7 @@ fieldset/AHB1LPENR: description: CRC clock enable during Sleep mode bit_offset: 12 bit_size: 1 - - name: FLITFLPEN + - name: FLASHLPEN description: Flash interface clock enable during Sleep mode bit_offset: 15 bit_size: 1 diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3.yaml index a709c25..474e0d7 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3.yaml @@ -69,8 +69,8 @@ fieldset/AHBENR: description: SRAM interface clock enable bit_offset: 2 bit_size: 1 - - name: FLITFEN - description: FLITF clock enable + - name: FLASHEN + description: FLASH clock enable bit_offset: 4 bit_size: 1 - name: FMCEN diff --git a/data/registers/rcc_f4.yaml b/data/registers/rcc_f4.yaml index 1d3aae5..52910a9 100644 --- a/data/registers/rcc_f4.yaml +++ b/data/registers/rcc_f4.yaml @@ -256,7 +256,7 @@ fieldset/AHB1LPENR: description: CRC clock enable during Sleep mode bit_offset: 12 bit_size: 1 - - name: FLITFLPEN + - name: FLASHLPEN description: Flash interface clock enable during Sleep mode bit_offset: 15 bit_size: 1 @@ -1395,7 +1395,7 @@ fieldset/CKGATENR: description: SRAM controller clock enable bit_offset: 4 bit_size: 1 - - name: FLITF_CKEN + - name: FLASH_CKEN description: Flash interface clock enable bit_offset: 5 bit_size: 1 diff --git a/data/registers/rcc_f410.yaml b/data/registers/rcc_f410.yaml index 299afe2..638a180 100644 --- a/data/registers/rcc_f410.yaml +++ b/data/registers/rcc_f410.yaml @@ -132,7 +132,7 @@ fieldset/AHB1LPENR: description: CRC clock enable during Sleep mode bit_offset: 12 bit_size: 1 - - name: FLITFLPEN + - name: FLASHLPEN description: Flash interface clock enable during Sleep mode bit_offset: 15 bit_size: 1 diff --git a/data/registers/rcc_f7.yaml b/data/registers/rcc_f7.yaml index 748795e..51a2ccc 100644 --- a/data/registers/rcc_f7.yaml +++ b/data/registers/rcc_f7.yaml @@ -256,7 +256,7 @@ fieldset/AHB1LPENR: description: AXI to AHB bridge clock enable during Sleep mode bit_offset: 13 bit_size: 1 - - name: FLITFLPEN + - name: FLASHLPEN description: Flash interface clock enable during Sleep mode bit_offset: 15 bit_size: 1 diff --git a/data/registers/rcc_g0.yaml b/data/registers/rcc_g0.yaml index 59948dd..0a2a2ee 100644 --- a/data/registers/rcc_g0.yaml +++ b/data/registers/rcc_g0.yaml @@ -108,10 +108,6 @@ fieldset/AHBENR: description: DMA1 clock enable bit_offset: 0 bit_size: 1 - - name: DMAEN - description: DMA clock enable - bit_offset: 0 - bit_size: 1 - name: DMA2EN description: DMA2 clock enable bit_offset: 1 @@ -139,16 +135,12 @@ fieldset/AHBRSTR: description: DMA1 reset bit_offset: 0 bit_size: 1 - - name: DMARST - description: DMA1 reset - bit_offset: 0 - bit_size: 1 - name: DMA2RST description: DMA1 reset bit_offset: 1 bit_size: 1 - name: FLASHRST - description: FLITF reset + description: FLASH reset bit_offset: 8 bit_size: 1 - name: CRCRST @@ -170,10 +162,6 @@ fieldset/AHBSMENR: description: DMA1 clock enable during Sleep mode bit_offset: 0 bit_size: 1 - - name: DMASMEN - description: DMA clock enable during Sleep mode - bit_offset: 0 - bit_size: 1 - name: DMA2SMEN description: DMA2 clock enable during Sleep mode bit_offset: 1 diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml index 891f7eb..ba64430 100644 --- a/data/registers/rcc_g4.yaml +++ b/data/registers/rcc_g4.yaml @@ -135,7 +135,7 @@ fieldset/AHB1ENR: description: DMA2 clock enable bit_offset: 1 bit_size: 1 - - name: DMAMUXEN + - name: DMAMUX1EN description: DMAMUX clock enable bit_offset: 2 bit_size: 1 @@ -167,7 +167,7 @@ fieldset/AHB1RSTR: bit_offset: 1 bit_size: 1 - name: DMAMUX1RST - description: DMAMUXRST + description: DMAMUX1RST bit_offset: 2 bit_size: 1 - name: CORDICRST @@ -1264,7 +1264,7 @@ fieldset/CSR: description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - - name: LPWRSTF + - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 diff --git a/data/registers/rcc_h7.yaml b/data/registers/rcc_h7.yaml index f4ef2d6..5d3583b 100644 --- a/data/registers/rcc_h7.yaml +++ b/data/registers/rcc_h7.yaml @@ -619,11 +619,7 @@ fieldset/AHB3LPENR: bit_offset: 5 bit_size: 1 - name: FLASHLPEN - description: FLITF Clock Enable During CSleep Mode - bit_offset: 8 - bit_size: 1 - - name: FLITFLPEN - description: FLITF Clock Enable During CSleep Mode + description: FLASH Clock Enable During CSleep Mode bit_offset: 8 bit_size: 1 - name: FMCLPEN @@ -3243,10 +3239,6 @@ fieldset/D3AMR: description: Digital temperature sensor Autonomous mode enable bit_offset: 26 bit_size: 1 - - name: BKPRAMAMEN - description: Backup RAM Autonomous mode enable - bit_offset: 28 - bit_size: 1 - name: BKPSRAMAMEN description: Backup RAM Autonomous mode enable bit_offset: 28 diff --git a/data/registers/rcc_h7ab.yaml b/data/registers/rcc_h7ab.yaml index 97df91e..de1e43d 100644 --- a/data/registers/rcc_h7ab.yaml +++ b/data/registers/rcc_h7ab.yaml @@ -588,7 +588,7 @@ fieldset/AHB4ENR: description: HSEM peripheral clock enable bit_offset: 25 bit_size: 1 - - name: BKPRAMEN + - name: BKPSRAMEN description: Backup RAM Clock Enable bit_offset: 28 bit_size: 1 @@ -651,7 +651,7 @@ fieldset/AHB4LPENR: description: ADC3 Peripheral Clocks Enable During CSleep Mode bit_offset: 24 bit_size: 1 - - name: BKPRAMLPEN + - name: BKPSRAMLPEN description: Backup RAM Clock Enable During CSleep Mode bit_offset: 28 bit_size: 1 diff --git a/data/registers/rcc_l0.yaml b/data/registers/rcc_l0.yaml index cbdb4cc..f8dbf82 100644 --- a/data/registers/rcc_l0.yaml +++ b/data/registers/rcc_l0.yaml @@ -418,10 +418,6 @@ fieldset/APB2ENR: description: Firewall clock enable bit_offset: 7 bit_size: 1 - - name: MIFIEN - description: MiFaRe Firewall clock enable - bit_offset: 7 - bit_size: 1 - name: ADCEN description: ADC clock enable bit_offset: 9 @@ -876,10 +872,6 @@ fieldset/CSR: description: Low-power reset flag bit_offset: 31 bit_size: 1 - - name: LPWRSTF - description: Low-power reset flag - bit_offset: 31 - bit_size: 1 fieldset/GPIOENR: description: GPIO clock enable register fields: diff --git a/data/registers/rcc_l1.yaml b/data/registers/rcc_l1.yaml index da22f2f..f7995d5 100644 --- a/data/registers/rcc_l1.yaml +++ b/data/registers/rcc_l1.yaml @@ -97,8 +97,8 @@ fieldset/AHBENR: description: CRC clock enable bit_offset: 12 bit_size: 1 - - name: FLITFEN - description: FLITF clock enable + - name: FLASHEN + description: FLASH clock enable bit_offset: 15 bit_size: 1 - name: DMA1EN @@ -152,8 +152,8 @@ fieldset/AHBLPENR: description: CRC clock enable during Sleep mode bit_offset: 12 bit_size: 1 - - name: FLITFLPEN - description: FLITF clock enable during Sleep mode + - name: FLASHLPEN + description: FLASH clock enable during Sleep mode bit_offset: 15 bit_size: 1 - name: SRAMLPEN @@ -207,8 +207,8 @@ fieldset/AHBRSTR: description: CRC reset bit_offset: 12 bit_size: 1 - - name: FLITFRST - description: FLITF reset + - name: FLASHRST + description: FLASH reset bit_offset: 15 bit_size: 1 - name: DMA1RST @@ -805,7 +805,7 @@ fieldset/CSR: description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - - name: LPWRSTF + - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 diff --git a/data/registers/rcc_l4.yaml b/data/registers/rcc_l4.yaml index 50af48b..832eb6c 100644 --- a/data/registers/rcc_l4.yaml +++ b/data/registers/rcc_l4.yaml @@ -179,7 +179,7 @@ fieldset/AHB1RSTR: bit_offset: 1 bit_size: 1 - name: DMAMUX1RST - description: DMAMUXRST + description: DMAMUX1RST bit_offset: 2 bit_size: 1 - name: FLASHRST @@ -892,10 +892,6 @@ fieldset/APB2ENR: description: SYSCFG clock enable bit_offset: 0 bit_size: 1 - - name: FIREWALLEN - description: Firewall clock enable - bit_offset: 7 - bit_size: 1 - name: FWEN description: Firewall clock enable bit_offset: 7 @@ -1535,10 +1531,6 @@ fieldset/CSR: description: Remove reset flag bit_offset: 23 bit_size: 1 - - name: FIREWALLRSTF - description: Firewall reset flag - bit_offset: 24 - bit_size: 1 - name: FWRSTF description: Firewall reset flag bit_offset: 24 @@ -1567,7 +1559,7 @@ fieldset/CSR: description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - - name: LPWRSTF + - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 diff --git a/data/registers/rcc_l5.yaml b/data/registers/rcc_l5.yaml index 49e426c..7ee9c5a 100644 --- a/data/registers/rcc_l5.yaml +++ b/data/registers/rcc_l5.yaml @@ -213,7 +213,7 @@ fieldset/AHB1RSTR: bit_offset: 1 bit_size: 1 - name: DMAMUX1RST - description: DMAMUXRST + description: DMAMUX1RST bit_offset: 2 bit_size: 1 - name: FLASHRST @@ -1739,7 +1739,7 @@ fieldset/CSR: description: Window watchdog reset flag bit_offset: 30 bit_size: 1 - - name: LPWRSTF + - name: LPWRRSTF description: Low-power reset flag bit_offset: 31 bit_size: 1 diff --git a/data/registers/rcc_wb.yaml b/data/registers/rcc_wb.yaml index 08dc99b..7d8307b 100644 --- a/data/registers/rcc_wb.yaml +++ b/data/registers/rcc_wb.yaml @@ -207,7 +207,7 @@ fieldset/AHB1ENR: description: DMA2 clock enable bit_offset: 1 bit_size: 1 - - name: DMAMUXEN + - name: DMAMUX1EN description: DMAMUX clock enable bit_offset: 2 bit_size: 1 @@ -230,7 +230,7 @@ fieldset/AHB1RSTR: description: DMA2 reset bit_offset: 1 bit_size: 1 - - name: DMAMUXRST + - name: DMAMUX1RST description: DMAMUX reset bit_offset: 2 bit_size: 1 @@ -253,7 +253,7 @@ fieldset/AHB1SMENR: description: CPU1 DMA2 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - - name: DMAMUXSMEN + - name: DMAMUX1SMEN description: CPU1 DMAMUX clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1 @@ -763,7 +763,7 @@ fieldset/C2AHB1ENR: description: CPU2 DMA2 clock enable bit_offset: 1 bit_size: 1 - - name: DMAMUXEN + - name: DMAMUX1EN description: CPU2 DMAMUX clock enable bit_offset: 2 bit_size: 1 @@ -790,7 +790,7 @@ fieldset/C2AHB1SMENR: description: CPU2 DMA2 clocks enable during Sleep and Stop modes bit_offset: 1 bit_size: 1 - - name: DMAMUXSMEN + - name: DMAMUX1SMEN description: CPU2 DMAMUX clocks enable during Sleep and Stop modes bit_offset: 2 bit_size: 1