Merge branch 'main' of https://github.com/embassy-rs/stm32-data into rtc

d.ps1

@@ -12,7 +12,7 @@ Switch ($CMD)
         rm -r -Force ./sources/ -ErrorAction SilentlyContinue
         git clone https://github.com/embassy-rs/stm32-data-sources.git ./sources/
         cd ./sources/
-        git checkout ca89656b
+        git checkout a2062c088cf299bd3dc5128eeaa96e07fff2087c
         cd ..
     }
     "install-chiptool" {

data/registers/pwr_f0.yaml

@@ -0,0 +1,78 @@
+block/PWR:
+  description: Power control
+  items:
+  - name: CR
+    description: power control register
+    byte_offset: 0
+    fieldset: CR
+  - name: CSR
+    description: power control/status register
+    byte_offset: 4
+    fieldset: CSR
+fieldset/CR:
+  description: power control register
+  fields:
+  - name: LPDS
+    description: Low-power deep sleep
+    bit_offset: 0
+    bit_size: 1
+  - name: PDDS
+    description: Power down deepsleep
+    bit_offset: 1
+    bit_size: 1
+    enum: PDDS
+  - name: CWUF
+    description: Clear wakeup flag
+    bit_offset: 2
+    bit_size: 1
+  - name: CSBF
+    description: Clear standby flag
+    bit_offset: 3
+    bit_size: 1
+  - name: PVDE
+    description: Power voltage detector enable
+    bit_offset: 4
+    bit_size: 1
+  - name: PLS
+    description: PVD level selection
+    bit_offset: 5
+    bit_size: 3
+  - name: DBP
+    description: Disable backup domain write protection
+    bit_offset: 8
+    bit_size: 1
+fieldset/CSR:
+  description: power control/status register
+  fields:
+  - name: WUF
+    description: Wakeup flag
+    bit_offset: 0
+    bit_size: 1
+  - name: SBF
+    description: Standby flag
+    bit_offset: 1
+    bit_size: 1
+  - name: PVDO
+    description: PVD output
+    bit_offset: 2
+    bit_size: 1
+  - name: VREFINTRDY
+    description: VREFINT reference voltage ready
+    bit_offset: 3
+    bit_size: 1
+  - name: EWUP
+    description: Enable WKUP pin 1
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+enum/PDDS:
+  bit_size: 1
+  variants:
+  - name: STOP_MODE
+    description: Enter Stop mode when the CPU enters deepsleep
+    value: 0
+  - name: STANDBY_MODE
+    description: Enter Standby mode when the CPU enters deepsleep
+    value: 1

data/registers/pwr_f0x0.yaml

@@ -0,0 +1,62 @@
+block/PWR:
+  description: Power control
+  items:
+  - name: CR
+    description: power control register
+    byte_offset: 0
+    fieldset: CR
+  - name: CSR
+    description: power control/status register
+    byte_offset: 4
+    fieldset: CSR
+fieldset/CR:
+  description: power control register
+  fields:
+  - name: LPDS
+    description: Low-power deep sleep
+    bit_offset: 0
+    bit_size: 1
+  - name: PDDS
+    description: Power down deepsleep
+    bit_offset: 1
+    bit_size: 1
+    enum: PDDS
+  - name: CWUF
+    description: Clear wakeup flag
+    bit_offset: 2
+    bit_size: 1
+  - name: CSBF
+    description: Clear standby flag
+    bit_offset: 3
+    bit_size: 1
+  - name: DBP
+    description: Disable backup domain write protection
+    bit_offset: 8
+    bit_size: 1
+fieldset/CSR:
+  description: power control/status register
+  fields:
+  - name: WUF
+    description: Wakeup flag
+    bit_offset: 0
+    bit_size: 1
+  - name: SBF
+    description: Standby flag
+    bit_offset: 1
+    bit_size: 1
+  - name: EWUP
+    description: Enable WKUP pin 1
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 8
+      stride: 1
+enum/PDDS:
+  bit_size: 1
+  variants:
+  - name: STOP_MODE
+    description: Enter Stop mode when the CPU enters deepsleep
+    value: 0
+  - name: STANDBY_MODE
+    description: Enter Standby mode when the CPU enters deepsleep
+    value: 1

data/registers/pwr_f1.yaml

@@ -0,0 +1,71 @@
+block/PWR:
+  description: Power control
+  items:
+  - name: CR
+    description: Power control register (PWR_CR)
+    byte_offset: 0
+    fieldset: CR
+  - name: CSR
+    description: Power control register (PWR_CR)
+    byte_offset: 4
+    fieldset: CSR
+fieldset/CR:
+  description: Power control register (PWR_CR)
+  fields:
+  - name: LPDS
+    description: Low Power Deep Sleep
+    bit_offset: 0
+    bit_size: 1
+  - name: PDDS
+    description: Power Down Deep Sleep
+    bit_offset: 1
+    bit_size: 1
+    enum: PDDS
+  - name: CWUF
+    description: Clear Wake-up Flag
+    bit_offset: 2
+    bit_size: 1
+  - name: CSBF
+    description: Clear STANDBY Flag
+    bit_offset: 3
+    bit_size: 1
+  - name: PVDE
+    description: Power Voltage Detector Enable
+    bit_offset: 4
+    bit_size: 1
+  - name: PLS
+    description: PVD Level Selection
+    bit_offset: 5
+    bit_size: 3
+  - name: DBP
+    description: Disable Backup Domain write protection
+    bit_offset: 8
+    bit_size: 1
+fieldset/CSR:
+  description: Power control register (PWR_CR)
+  fields:
+  - name: WUF
+    description: Wake-Up Flag
+    bit_offset: 0
+    bit_size: 1
+  - name: SBF
+    description: STANDBY Flag
+    bit_offset: 1
+    bit_size: 1
+  - name: PVDO
+    description: PVD Output
+    bit_offset: 2
+    bit_size: 1
+  - name: EWUP
+    description: Enable WKUP pin
+    bit_offset: 8
+    bit_size: 1
+enum/PDDS:
+  bit_size: 1
+  variants:
+  - name: STOP_MODE
+    description: Enter Stop mode when the CPU enters deepsleep
+    value: 0
+  - name: STANDBY_MODE
+    description: Enter Standby mode when the CPU enters deepsleep
+    value: 1

data/registers/pwr_g0.yaml

@@ -73,6 +73,7 @@ fieldset/CR1:
     description: Voltage scaling range selection
     bit_offset: 9
     bit_size: 2
+    enum: VOS
   - name: LPR
     description: Low-power run
     bit_offset: 14
@@ -201,3 +202,10 @@ fieldset/SR2:
     description: Power voltage detector output
     bit_offset: 11
     bit_size: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Range1
+    value: 1
+  - name: Range2
+    value: 2

data/registers/pwr_g4.yaml

@@ -65,6 +65,7 @@ fieldset/CR1:
     description: Voltage scaling range selection
     bit_offset: 9
     bit_size: 2
+    enum: VOS
   - name: LPR
     description: Low-power run
     bit_offset: 14
@@ -280,3 +281,10 @@ fieldset/SR2:
     description: 'Peripheral voltage monitoring output: VDDA vs. 2.2 V'
     bit_offset: 15
     bit_size: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Range1
+    value: 1
+  - name: Range2
+    value: 2

data/registers/pwr_h7rm0399.yaml

@@ -220,6 +220,7 @@ fieldset/D3CR:
     description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.'
     bit_offset: 14
     bit_size: 2
+    enum: VOS
 fieldset/WKUPCR:
   description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
   fields:
@@ -261,3 +262,12 @@ fieldset/WKUPFR:
     array:
       len: 6
       stride: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Scale3
+    value: 1
+  - name: Scale2
+    value: 2
+  - name: Scale1
+    value: 3

data/registers/pwr_h7rm0433.yaml

@@ -155,7 +155,7 @@ fieldset/CR3:
     bit_offset: 1
     bit_size: 1
   - name: SCUEN
-    description: SD converter Enable
+    description: Supply configuration update enable
     bit_offset: 2
     bit_size: 1
   - name: VBE
@@ -208,6 +208,7 @@ fieldset/D3CR:
     description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.'
     bit_offset: 14
     bit_size: 2
+    enum: VOS
 fieldset/WKUPCR:
   description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
   fields:
@@ -249,3 +250,12 @@ fieldset/WKUPFR:
     array:
       len: 6
       stride: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Scale3
+    value: 1
+  - name: Scale2
+    value: 2
+  - name: Scale1
+    value: 3

data/registers/pwr_h7rm0455.yaml

@@ -0,0 +1,275 @@
+block/PWR:
+  description: PWR
+  items:
+  - name: CR1
+    description: PWR control register 1
+    byte_offset: 0
+    fieldset: CR1
+  - name: CSR1
+    description: PWR control status register 1
+    byte_offset: 4
+    access: Read
+    fieldset: CSR1
+  - name: CR2
+    description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
+    byte_offset: 8
+    fieldset: CR2
+  - name: CR3
+    description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.'
+    byte_offset: 12
+    fieldset: CR3
+  - name: CPUCR
+    description: This register allows controlling CPU1 power.
+    byte_offset: 16
+    fieldset: CPUCR
+  - name: D3CR
+    description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
+    byte_offset: 24
+    fieldset: D3CR
+  - name: WKUPCR
+    description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
+    byte_offset: 32
+    fieldset: WKUPCR
+  - name: WKUPFR
+    description: reset only by system reset, not reset by wakeup from Standby mode
+    byte_offset: 36
+    fieldset: WKUPFR
+  - name: WKUPEPR
+    description: Reset only by system reset, not reset by wakeup from Standby mode
+    byte_offset: 40
+    fieldset: WKUPEPR
+fieldset/CPUCR:
+  description: This register allows controlling CPU1 power.
+  fields:
+  - name: PDDS_D1
+    description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDDS_D2
+    description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain.
+    bit_offset: 1
+    bit_size: 1
+  - name: PDDS_D3
+    description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain.
+    bit_offset: 2
+    bit_size: 1
+  - name: STOPF
+    description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit.
+    bit_offset: 5
+    bit_size: 1
+  - name: SBF
+    description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit
+    bit_offset: 6
+    bit_size: 1
+  - name: SBF_D1
+    description: D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode.
+    bit_offset: 7
+    bit_size: 1
+  - name: SBF_D2
+    description: D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode.
+    bit_offset: 8
+    bit_size: 1
+  - name: CSSF
+    description: Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware.
+    bit_offset: 9
+    bit_size: 1
+  - name: RUN_D3
+    description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes
+    bit_offset: 11
+    bit_size: 1
+fieldset/CR1:
+  description: PWR control register 1
+  fields:
+  - name: LPDS
+    description: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)
+    bit_offset: 0
+    bit_size: 1
+  - name: PVDE
+    description: Programmable voltage detector enable
+    bit_offset: 4
+    bit_size: 1
+  - name: PLS
+    description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 5
+    bit_size: 3
+  - name: DBP
+    description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers.
+    bit_offset: 8
+    bit_size: 1
+  - name: FLPS
+    description: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode.
+    bit_offset: 9
+    bit_size: 1
+  - name: SVOS
+    description: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance.
+    bit_offset: 14
+    bit_size: 2
+  - name: AVDEN
+    description: Peripheral voltage monitor on VDDA enable
+    bit_offset: 16
+    bit_size: 1
+  - name: ALS
+    description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD.
+    bit_offset: 17
+    bit_size: 2
+fieldset/CR2:
+  description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
+  fields:
+  - name: BREN
+    description: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes.
+    bit_offset: 0
+    bit_size: 1
+  - name: MONEN
+    description: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled.
+    bit_offset: 4
+    bit_size: 1
+  - name: BRRDY
+    description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready.
+    bit_offset: 16
+    bit_size: 1
+  - name: VBATL
+    description: VBAT level monitoring versus low threshold
+    bit_offset: 20
+    bit_size: 1
+  - name: VBATH
+    description: VBAT level monitoring versus high threshold
+    bit_offset: 21
+    bit_size: 1
+  - name: TEMPL
+    description: Temperature level monitoring versus low threshold
+    bit_offset: 22
+    bit_size: 1
+  - name: TEMPH
+    description: Temperature level monitoring versus high threshold
+    bit_offset: 23
+    bit_size: 1
+fieldset/CR3:
+  description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.'
+  fields:
+  - name: BYPASS
+    description: Power management unit bypass
+    bit_offset: 0
+    bit_size: 1
+  - name: LDOEN
+    description: Low drop-out regulator enable
+    bit_offset: 1
+    bit_size: 1
+  - name: SDEN
+    description: SD converter Enable
+    bit_offset: 2
+    bit_size: 1
+  - name: SDEXTHP
+    description: Step-down converter forced ON and in High Power MR mode
+    bit_offset: 3
+    bit_size: 1
+  - name: SDLEVEL
+    description: Step-down converter voltage output level selection
+    bit_offset: 4
+    bit_size: 2
+  - name: VBE
+    description: VBAT charging enable
+    bit_offset: 8
+    bit_size: 1
+  - name: VBRS
+    description: VBAT charging resistor selection
+    bit_offset: 9
+    bit_size: 1
+  - name: SDEXTRDY
+    description: SMPS step-down converter external supply ready
+    bit_offset: 16
+    bit_size: 1
+  - name: USB33DEN
+    description: VDD33USB voltage level detector enable.
+    bit_offset: 24
+    bit_size: 1
+  - name: USBREGEN
+    description: USB regulator enable.
+    bit_offset: 25
+    bit_size: 1
+  - name: USB33RDY
+    description: USB supply ready.
+    bit_offset: 26
+    bit_size: 1
+fieldset/CSR1:
+  description: PWR control status register 1
+  fields:
+  - name: PVDO
+    description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.'
+    bit_offset: 4
+    bit_size: 1
+  - name: ACTVOSRDY
+    description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3).
+    bit_offset: 13
+    bit_size: 1
+  - name: ACTVOS
+    description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU.
+    bit_offset: 14
+    bit_size: 2
+  - name: AVDO
+    description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.'
+    bit_offset: 16
+    bit_size: 1
+fieldset/D3CR:
+  description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
+  fields:
+  - name: VOSRDY
+    description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3).
+    bit_offset: 13
+    bit_size: 1
+  - name: VOS
+    description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.'
+    bit_offset: 14
+    bit_size: 2
+    enum: VOS
+fieldset/WKUPCR:
+  description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
+  fields:
+  - name: WKUPC
+    description: Clear Wakeup pin flag for WKUP. These bits are always read as 0.
+    bit_offset: 0
+    bit_size: 6
+fieldset/WKUPEPR:
+  description: Reset only by system reset, not reset by wakeup from Standby mode
+  fields:
+  - name: WKUPEN
+    description: 'Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.'
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 6
+      stride: 1
+  - name: WKUPP
+    description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 6
+      stride: 1
+  - name: WKUPPUPD
+    description: Wakeup pin pull configuration
+    bit_offset: 16
+    bit_size: 2
+    array:
+      len: 6
+      stride: 2
+fieldset/WKUPFR:
+  description: reset only by system reset, not reset by wakeup from Standby mode
+  fields:
+  - name: WKUPF
+    description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 6
+      stride: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Scale3
+    value: 0
+  - name: Scale2
+    value: 1
+  - name: Scale1
+    value: 2
+  - name: Scale0
+    value: 3

data/registers/pwr_h7rm0468.yaml

@@ -0,0 +1,275 @@
+block/PWR:
+  description: PWR
+  items:
+  - name: CR1
+    description: PWR control register 1
+    byte_offset: 0
+    fieldset: CR1
+  - name: CSR1
+    description: PWR control status register 1
+    byte_offset: 4
+    access: Read
+    fieldset: CSR1
+  - name: CR2
+    description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
+    byte_offset: 8
+    fieldset: CR2
+  - name: CR3
+    description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.'
+    byte_offset: 12
+    fieldset: CR3
+  - name: CPUCR
+    description: This register allows controlling CPU1 power.
+    byte_offset: 16
+    fieldset: CPUCR
+  - name: D3CR
+    description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
+    byte_offset: 24
+    fieldset: D3CR
+  - name: WKUPCR
+    description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
+    byte_offset: 32
+    fieldset: WKUPCR
+  - name: WKUPFR
+    description: reset only by system reset, not reset by wakeup from Standby mode
+    byte_offset: 36
+    fieldset: WKUPFR
+  - name: WKUPEPR
+    description: Reset only by system reset, not reset by wakeup from Standby mode
+    byte_offset: 40
+    fieldset: WKUPEPR
+fieldset/CPUCR:
+  description: This register allows controlling CPU1 power.
+  fields:
+  - name: PDDS_D1
+    description: D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain.
+    bit_offset: 0
+    bit_size: 1
+  - name: PDDS_D2
+    description: D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain.
+    bit_offset: 1
+    bit_size: 1
+  - name: PDDS_D3
+    description: System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain.
+    bit_offset: 2
+    bit_size: 1
+  - name: STOPF
+    description: STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit.
+    bit_offset: 5
+    bit_size: 1
+  - name: SBF
+    description: System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit
+    bit_offset: 6
+    bit_size: 1
+  - name: SBF_D1
+    description: D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode.
+    bit_offset: 7
+    bit_size: 1
+  - name: SBF_D2
+    description: D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode.
+    bit_offset: 8
+    bit_size: 1
+  - name: CSSF
+    description: Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware.
+    bit_offset: 9
+    bit_size: 1
+  - name: RUN_D3
+    description: Keep system D3 domain in Run mode regardless of the CPU sub-systems modes
+    bit_offset: 11
+    bit_size: 1
+fieldset/CR1:
+  description: PWR control register 1
+  fields:
+  - name: LPDS
+    description: Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)
+    bit_offset: 0
+    bit_size: 1
+  - name: PVDE
+    description: Programmable voltage detector enable
+    bit_offset: 4
+    bit_size: 1
+  - name: PLS
+    description: 'Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details.'
+    bit_offset: 5
+    bit_size: 3
+  - name: DBP
+    description: Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers.
+    bit_offset: 8
+    bit_size: 1
+  - name: FLPS
+    description: Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode.
+    bit_offset: 9
+    bit_size: 1
+  - name: SVOS
+    description: System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance.
+    bit_offset: 14
+    bit_size: 2
+  - name: AVDEN
+    description: Peripheral voltage monitor on VDDA enable
+    bit_offset: 16
+    bit_size: 1
+  - name: ALS
+    description: Analog voltage detector level selection These bits select the voltage threshold detected by the AVD.
+    bit_offset: 17
+    bit_size: 2
+fieldset/CR2:
+  description: This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection.
+  fields:
+  - name: BREN
+    description: Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes.
+    bit_offset: 0
+    bit_size: 1
+  - name: MONEN
+    description: VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled.
+    bit_offset: 4
+    bit_size: 1
+  - name: BRRDY
+    description: Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready.
+    bit_offset: 16
+    bit_size: 1
+  - name: VBATL
+    description: VBAT level monitoring versus low threshold
+    bit_offset: 20
+    bit_size: 1
+  - name: VBATH
+    description: VBAT level monitoring versus high threshold
+    bit_offset: 21
+    bit_size: 1
+  - name: TEMPL
+    description: Temperature level monitoring versus low threshold
+    bit_offset: 22
+    bit_size: 1
+  - name: TEMPH
+    description: Temperature level monitoring versus high threshold
+    bit_offset: 23
+    bit_size: 1
+fieldset/CR3:
+  description: 'Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value.'
+  fields:
+  - name: BYPASS
+    description: Power management unit bypass
+    bit_offset: 0
+    bit_size: 1
+  - name: LDOEN
+    description: Low drop-out regulator enable
+    bit_offset: 1
+    bit_size: 1
+  - name: SDEN
+    description: SD converter Enable
+    bit_offset: 2
+    bit_size: 1
+  - name: SDEXTHP
+    description: Step-down converter forced ON and in High Power MR mode
+    bit_offset: 3
+    bit_size: 1
+  - name: SDLEVEL
+    description: Step-down converter voltage output level selection
+    bit_offset: 4
+    bit_size: 2
+  - name: VBE
+    description: VBAT charging enable
+    bit_offset: 8
+    bit_size: 1
+  - name: VBRS
+    description: VBAT charging resistor selection
+    bit_offset: 9
+    bit_size: 1
+  - name: SDEXTRDY
+    description: SMPS step-down converter external supply ready
+    bit_offset: 16
+    bit_size: 1
+  - name: USB33DEN
+    description: VDD33USB voltage level detector enable.
+    bit_offset: 24
+    bit_size: 1
+  - name: USBREGEN
+    description: USB regulator enable.
+    bit_offset: 25
+    bit_size: 1
+  - name: USB33RDY
+    description: USB supply ready.
+    bit_offset: 26
+    bit_size: 1
+fieldset/CSR1:
+  description: PWR control status register 1
+  fields:
+  - name: PVDO
+    description: 'Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set.'
+    bit_offset: 4
+    bit_size: 1
+  - name: ACTVOSRDY
+    description: Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3).
+    bit_offset: 13
+    bit_size: 1
+  - name: ACTVOS
+    description: VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU.
+    bit_offset: 14
+    bit_size: 2
+  - name: AVDO
+    description: 'Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set.'
+    bit_offset: 16
+    bit_size: 1
+fieldset/D3CR:
+  description: This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software
+  fields:
+  - name: VOSRDY
+    description: VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3).
+    bit_offset: 13
+    bit_size: 1
+  - name: VOS
+    description: 'Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling.'
+    bit_offset: 14
+    bit_size: 2
+    enum: VOS
+fieldset/WKUPCR:
+  description: reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared).
+  fields:
+  - name: WKUPC
+    description: Clear Wakeup pin flag for WKUP. These bits are always read as 0.
+    bit_offset: 0
+    bit_size: 6
+fieldset/WKUPEPR:
+  description: Reset only by system reset, not reset by wakeup from Standby mode
+  fields:
+  - name: WKUPEN
+    description: 'Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge.'
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 6
+      stride: 1
+  - name: WKUPP
+    description: Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin.
+    bit_offset: 8
+    bit_size: 1
+    array:
+      len: 6
+      stride: 1
+  - name: WKUPPUPD
+    description: Wakeup pin pull configuration
+    bit_offset: 16
+    bit_size: 2
+    array:
+      len: 6
+      stride: 2
+fieldset/WKUPFR:
+  description: reset only by system reset, not reset by wakeup from Standby mode
+  fields:
+  - name: WKUPF
+    description: Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR).
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 6
+      stride: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Scale0
+    value: 0
+  - name: Scale3
+    value: 1
+  - name: Scale2
+    value: 2
+  - name: Scale1
+    value: 3

data/registers/pwr_l0.yaml

@@ -164,69 +164,15 @@ enum/PLS:
   - name: External
     description: External input analog voltage (Compare internally to VREFINT)
     value: 7
-enum/PVDOR:
-  bit_size: 1
-  variants:
-  - name: AboveThreshold
-    description: VDD is higher than the PVD threshold selected with the PLS[2:0] bits
-    value: 0
-  - name: BelowThreshold
-    description: VDD is lower than the PVD threshold selected with the PLS[2:0] bits
-    value: 1
-enum/REGLPFR:
-  bit_size: 1
-  variants:
-  - name: Ready
-    description: Regulator is ready in Main mode
-    value: 0
-  - name: NotReady
-    description: Regulator voltage is in low-power mode
-    value: 1
-enum/SBFR:
-  bit_size: 1
-  variants:
-  - name: NoStandbyEvent
-    description: Device has not been in Standby mode
-    value: 0
-  - name: StandbyEvent
-    description: Device has been in Standby mode
-    value: 1
 enum/VOS:
   bit_size: 2
   variants:
-  - name: V1_8
+  - name: Range1
     description: 1.8 V (range 1)
     value: 1
-  - name: V1_5
+  - name: Range2
     description: 1.5 V (range 2)
     value: 2
-  - name: V1_2
+  - name: Range3
     description: 1.2 V (range 3)
     value: 3
-enum/VOSFR:
-  bit_size: 1
-  variants:
-  - name: Ready
-    description: Regulator is ready in the selected voltage range
-    value: 0
-  - name: NotReady
-    description: Regulator voltage output is changing to the required VOS level
-    value: 1
-enum/VREFINTRDYFR:
-  bit_size: 1
-  variants:
-  - name: NotReady
-    description: VREFINT is OFF
-    value: 0
-  - name: Ready
-    description: VREFINT is ready
-    value: 1
-enum/WUFR:
-  bit_size: 1
-  variants:
-  - name: NoWakeupEvent
-    description: No wakeup event occurred
-    value: 0
-  - name: WakeupEvent
-    description: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup)
-    value: 1

data/registers/pwr_l1.yaml

@@ -53,6 +53,7 @@ fieldset/CR:
     description: Voltage scaling range selection
     bit_offset: 11
     bit_size: 2
+    enum: VOS
   - name: LPRUN
     description: Low power run mode
     bit_offset: 14
@@ -100,3 +101,15 @@ enum/PDDS:
   - name: STANDBY_MODE
     description: Enter Standby mode when the CPU enters deepsleep
     value: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Range1
+    description: Range 1
+    value: 1
+  - name: Range2
+    description: Range 2
+    value: 2
+  - name: Range3
+    description: Range 3
+    value: 3

data/registers/pwr_u5.yaml

@@ -823,16 +823,16 @@ enum/VBRS:
 enum/VOS:
   bit_size: 2
   variants:
-  - name: B_0x0
+  - name: Range4
     description: Range 4 (lowest power)
     value: 0
-  - name: B_0x1
+  - name: Range3
     description: Range 3
     value: 1
-  - name: B_0x2
+  - name: Range2
     description: Range 2
     value: 2
-  - name: B_0x3
+  - name: Range1
     description: Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register.
     value: 3
 enum/WUPP:

data/registers/pwr_wb.yaml

@@ -0,0 +1,448 @@
+block/PWR:
+  description: Power control
+  items:
+  - name: CR1
+    description: Power control register 1
+    byte_offset: 0
+    fieldset: CR1
+  - name: CR2
+    description: Power control register 2
+    byte_offset: 4
+    fieldset: CR2
+  - name: CR3
+    description: Power control register 3
+    byte_offset: 8
+    fieldset: CR3
+  - name: CR4
+    description: Power control register 4
+    byte_offset: 12
+    fieldset: CR4
+  - name: SR1
+    description: Power status register 1
+    byte_offset: 16
+    access: Read
+    fieldset: SR1
+  - name: SR2
+    description: Power status register 2
+    byte_offset: 20
+    access: Read
+    fieldset: SR2
+  - name: SCR
+    description: Power status clear register
+    byte_offset: 24
+    access: Write
+    fieldset: SCR
+  - name: CR5
+    description: Power control register 5
+    byte_offset: 28
+    fieldset: CR5
+  - name: PUCRA
+    description: Power Port A pull-up control register
+    byte_offset: 32
+    fieldset: PXCR
+  - name: PDCRA
+    description: Power Port A pull-down control register
+    byte_offset: 36
+    fieldset: PXCR
+  - name: PUCRB
+    description: Power Port B pull-up control register
+    byte_offset: 40
+    fieldset: PXCR
+  - name: PDCRB
+    description: Power Port B pull-down control register
+    byte_offset: 44
+    fieldset: PXCR
+  - name: PUCRC
+    description: Power Port C pull-up control register
+    byte_offset: 48
+    fieldset: PXCR
+  - name: PDCRC
+    description: Power Port C pull-down control register
+    byte_offset: 52
+    fieldset: PXCR
+  - name: PUCRD
+    description: Power Port D pull-up control register
+    byte_offset: 56
+    fieldset: PXCR
+  - name: PDCRD
+    description: Power Port D pull-down control register
+    byte_offset: 60
+    fieldset: PXCR
+  - name: PUCRE
+    description: Power Port E pull-up control register
+    byte_offset: 64
+    fieldset: PXCR
+  - name: PDCRE
+    description: Power Port E pull-down control register
+    byte_offset: 68
+    fieldset: PXCR
+  - name: PUCRH
+    description: Power Port H pull-up control register
+    byte_offset: 88
+    fieldset: PXCR
+  - name: PDCRH
+    description: Power Port H pull-down control register
+    byte_offset: 92
+    fieldset: PXCR
+  - name: C2CR1
+    description: CPU2 Power control register 1
+    byte_offset: 128
+    fieldset: C2CR1
+  - name: C2CR3
+    description: CPU2 Power control register 3
+    byte_offset: 132
+    fieldset: C2CR3
+  - name: EXTSCR
+    description: Power status clear register
+    byte_offset: 136
+    fieldset: EXTSCR
+fieldset/C2CR1:
+  description: CPU2 Power control register 1
+  fields:
+  - name: LPMS
+    description: Low-power mode selection for CPU2
+    bit_offset: 0
+    bit_size: 3
+  - name: FPDR
+    description: Flash power down mode during LPRun for CPU2
+    bit_offset: 4
+    bit_size: 1
+  - name: FPDS
+    description: Flash power down mode during LPSleep for CPU2
+    bit_offset: 5
+    bit_size: 1
+  - name: BLEEWKUP
+    description: BLE external wakeup signal
+    bit_offset: 14
+    bit_size: 1
+  - name: _802EWKUP
+    description: 802.15.4 external wakeup signal
+    bit_offset: 15
+    bit_size: 1
+fieldset/C2CR3:
+  description: CPU2 Power control register 3
+  fields:
+  - name: EWUP
+    description: Enable Wakeup pin
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 5
+      stride: 1
+  - name: EBLEWUP
+    description: Enable BLE host wakeup interrupt for CPU2
+    bit_offset: 9
+    bit_size: 1
+  - name: E802WUP
+    description: Enable 802.15.4 host wakeup interrupt for CPU2
+    bit_offset: 10
+    bit_size: 1
+  - name: APC
+    description: Apply pull-up and pull-down configuration for CPU2
+    bit_offset: 12
+    bit_size: 1
+  - name: EIWUL
+    description: Enable internal wakeup line for CPU2
+    bit_offset: 15
+    bit_size: 1
+fieldset/CR1:
+  description: Power control register 1
+  fields:
+  - name: LPMS
+    description: Low-power mode selection for CPU1
+    bit_offset: 0
+    bit_size: 3
+  - name: FPDR
+    description: Flash power down mode during LPRun for CPU1
+    bit_offset: 4
+    bit_size: 1
+  - name: FPDS
+    description: Flash power down mode during LPsSleep for CPU1
+    bit_offset: 5
+    bit_size: 1
+  - name: DBP
+    description: Disable backup domain write protection
+    bit_offset: 8
+    bit_size: 1
+  - name: LPR
+    description: Low-power run
+    bit_offset: 14
+    bit_size: 1
+fieldset/CR2:
+  description: Power control register 2
+  fields:
+  - name: PVDE
+    description: Power voltage detector enable
+    bit_offset: 0
+    bit_size: 1
+  - name: PLS
+    description: Power voltage detector level selection
+    bit_offset: 1
+    bit_size: 3
+fieldset/CR3:
+  description: Power control register 3
+  fields:
+  - name: EWUP
+    description: Enable Wakeup pin
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 5
+      stride: 1
+  - name: EBORHSDFB
+    description: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1
+    bit_offset: 8
+    bit_size: 1
+  - name: RRS
+    description: SRAM2a retention in Standby mode
+    bit_offset: 9
+    bit_size: 1
+  - name: APC
+    description: Apply pull-up and pull-down configuration
+    bit_offset: 10
+    bit_size: 1
+  - name: EBLEA
+    description: Enable BLE end of activity interrupt for CPU1
+    bit_offset: 11
+    bit_size: 1
+  - name: ECRPE
+    description: Enable critical radio phase end of activity interrupt for CPU1
+    bit_offset: 12
+    bit_size: 1
+  - name: E802A
+    description: Enable end of activity interrupt for CPU1
+    bit_offset: 13
+    bit_size: 1
+  - name: EC2H
+    description: Enable CPU2 Hold interrupt for CPU1
+    bit_offset: 14
+    bit_size: 1
+  - name: EIWUL
+    description: Enable internal wakeup line for CPU1
+    bit_offset: 15
+    bit_size: 1
+fieldset/CR4:
+  description: Power control register 4
+  fields:
+  - name: WP1
+    description: Wakeup pin WKUP1 polarity
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 5
+      stride: 1
+  - name: VBE
+    description: VBAT battery charging enable
+    bit_offset: 8
+    bit_size: 1
+  - name: VBRS
+    description: VBAT battery charging resistor selection
+    bit_offset: 9
+    bit_size: 1
+  - name: C2BOOT
+    description: BOOT CPU2 after reset or wakeup from Stop or Standby modes
+    bit_offset: 15
+    bit_size: 1
+fieldset/CR5:
+  description: Power control register 5
+  fields:
+  - name: SDVOS
+    description: Step Down converter voltage output scaling
+    bit_offset: 0
+    bit_size: 4
+  - name: SDSC
+    description: Step Down converter supplt startup current selection
+    bit_offset: 4
+    bit_size: 3
+  - name: BORHC
+    description: BORH configuration selection
+    bit_offset: 8
+    bit_size: 1
+  - name: SMPSCFG
+    description: VOS configuration selection (non user)
+    bit_offset: 9
+    bit_size: 1
+  - name: SDBEN
+    description: Enable Step Down converter Bypass mode enabled
+    bit_offset: 14
+    bit_size: 1
+  - name: SDEB
+    description: Enable Step Down converter SMPS mode enabled
+    bit_offset: 15
+    bit_size: 1
+fieldset/EXTSCR:
+  description: Power status clear register
+  fields:
+  - name: C1CSSF
+    description: Clear CPU1 Stop Standby flags
+    bit_offset: 0
+    bit_size: 1
+  - name: C2CSSF
+    description: Clear CPU2 Stop Standby flags
+    bit_offset: 1
+    bit_size: 1
+  - name: CCRPF
+    description: Clear Critical Radio system phase
+    bit_offset: 2
+    bit_size: 1
+  - name: C1SBF
+    description: System Standby flag for CPU1
+    bit_offset: 8
+    bit_size: 1
+  - name: C1STOPF
+    description: System Stop flag for CPU1
+    bit_offset: 9
+    bit_size: 1
+  - name: C2SBF
+    description: System Standby flag for CPU2
+    bit_offset: 10
+    bit_size: 1
+  - name: C2STOPF
+    description: System Stop flag for CPU2
+    bit_offset: 11
+    bit_size: 1
+  - name: CRPF
+    description: Critical Radio system phase
+    bit_offset: 13
+    bit_size: 1
+  - name: C1DS
+    description: CPU1 deepsleep mode
+    bit_offset: 14
+    bit_size: 1
+  - name: C2DS
+    description: CPU2 deepsleep mode
+    bit_offset: 15
+    bit_size: 1
+fieldset/PXCR:
+  description: Power Port pull-up/down control register
+  fields:
+  - name: PD
+    description: Port A pull-up/down bit y (y=0..15)
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 16
+      stride: 1
+fieldset/SCR:
+  description: Power status clear register
+  fields:
+  - name: CWUF
+    description: Clear wakeup flag 1
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 5
+      stride: 1
+  - name: CSMPSFBF
+    description: Clear SMPS Step Down converter forced in Bypass interrupt flag
+    bit_offset: 7
+    bit_size: 1
+  - name: CBORHF
+    description: Clear BORH interrupt flag
+    bit_offset: 8
+    bit_size: 1
+  - name: CBLEWUF
+    description: Clear BLE wakeup interrupt flag
+    bit_offset: 9
+    bit_size: 1
+  - name: C802WUF
+    description: Clear 802.15.4 wakeup interrupt flag
+    bit_offset: 10
+    bit_size: 1
+  - name: CCRPEF
+    description: Clear critical radio phase end of activity interrupt flag
+    bit_offset: 11
+    bit_size: 1
+  - name: CBLEAF
+    description: Clear BLE end of activity interrupt flag
+    bit_offset: 12
+    bit_size: 1
+  - name: C802AF
+    description: Clear 802.15.4 end of activity interrupt flag
+    bit_offset: 13
+    bit_size: 1
+  - name: CC2HF
+    description: Clear CPU2 Hold interrupt flag
+    bit_offset: 14
+    bit_size: 1
+fieldset/SR1:
+  description: Power status register 1
+  fields:
+  - name: CWUF
+    description: Wakeup flag 1
+    bit_offset: 0
+    bit_size: 1
+    array:
+      len: 5
+      stride: 1
+  - name: SDFBF
+    description: Step Down converter forced in Bypass interrupt flag
+    bit_offset: 7
+    bit_size: 1
+  - name: BORHF
+    description: BORH interrupt flag
+    bit_offset: 8
+    bit_size: 1
+  - name: BLEWUF
+    description: BLE wakeup interrupt flag
+    bit_offset: 9
+    bit_size: 1
+  - name: _802WUF
+    description: 802.15.4 wakeup interrupt flag
+    bit_offset: 10
+    bit_size: 1
+  - name: CRPEF
+    description: Enable critical radio phase end of activity interrupt flag
+    bit_offset: 11
+    bit_size: 1
+  - name: BLEAF
+    description: BLE end of activity interrupt flag
+    bit_offset: 12
+    bit_size: 1
+  - name: AF802
+    description: 802.15.4 end of activity interrupt flag
+    bit_offset: 13
+    bit_size: 1
+  - name: C2HF
+    description: CPU2 Hold interrupt flag
+    bit_offset: 14
+    bit_size: 1
+  - name: WUFI
+    description: Internal Wakeup interrupt flag
+    bit_offset: 15
+    bit_size: 1
+fieldset/SR2:
+  description: Power status register 2
+  fields:
+  - name: SDBF
+    description: Step Down converter Bypass mode flag
+    bit_offset: 0
+    bit_size: 1
+  - name: SDSMPSF
+    description: Step Down converter SMPS mode flag
+    bit_offset: 1
+    bit_size: 1
+  - name: REGLPS
+    description: Low-power regulator started
+    bit_offset: 8
+    bit_size: 1
+  - name: REGLPF
+    description: Low-power regulator flag
+    bit_offset: 9
+    bit_size: 1
+  - name: VOSF
+    description: Voltage scaling flag
+    bit_offset: 10
+    bit_size: 1
+  - name: PVDO
+    description: Power voltage detector output
+    bit_offset: 11
+    bit_size: 1
+  - name: PVMO1
+    description: 'Peripheral voltage monitoring output: VDDUSB vs. 1.2 V'
+    bit_offset: 12
+    bit_size: 1
+  - name: PVMO3
+    description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V'
+    bit_offset: 14
+    bit_size: 1

data/registers/pwr_wb55.yaml

@@ -39,51 +39,51 @@ block/PWR:
   - name: PUCRA
     description: Power Port A pull-up control register
     byte_offset: 32
-    fieldset: PUCRA
+    fieldset: PXCR
   - name: PDCRA
     description: Power Port A pull-down control register
     byte_offset: 36
-    fieldset: PDCRA
+    fieldset: PXCR
   - name: PUCRB
     description: Power Port B pull-up control register
     byte_offset: 40
-    fieldset: PUCRB
+    fieldset: PXCR
   - name: PDCRB
     description: Power Port B pull-down control register
     byte_offset: 44
-    fieldset: PDCRB
+    fieldset: PXCR
   - name: PUCRC
     description: Power Port C pull-up control register
     byte_offset: 48
-    fieldset: PUCRC
+    fieldset: PXCR
   - name: PDCRC
     description: Power Port C pull-down control register
     byte_offset: 52
-    fieldset: PDCRC
+    fieldset: PXCR
   - name: PUCRD
     description: Power Port D pull-up control register
     byte_offset: 56
-    fieldset: PUCRD
+    fieldset: PXCR
   - name: PDCRD
     description: Power Port D pull-down control register
     byte_offset: 60
-    fieldset: PDCRD
+    fieldset: PXCR
   - name: PUCRE
     description: Power Port E pull-up control register
     byte_offset: 64
-    fieldset: PUCRE
+    fieldset: PXCR
   - name: PDCRE
     description: Power Port E pull-down control register
     byte_offset: 68
-    fieldset: PDCRE
+    fieldset: PXCR
   - name: PUCRH
     description: Power Port H pull-up control register
     byte_offset: 88
-    fieldset: PUCRH
+    fieldset: PXCR
   - name: PDCRH
     description: Power Port H pull-down control register
     byte_offset: 92
-    fieldset: PDCRH
+    fieldset: PXCR
   - name: C2CR1
     description: CPU2 Power control register 1
     byte_offset: 128
@@ -122,26 +122,13 @@ fieldset/C2CR1:
 fieldset/C2CR3:
   description: CPU2 Power control register 3
   fields:
-  - name: EWUP1
+  - name: EWUP
-    description: Enable Wakeup pin WKUP1 for CPU2
+    description: Enable Wakeup pin
     bit_offset: 0
     bit_size: 1
-  - name: EWUP2
+    array:
-    description: Enable Wakeup pin WKUP2 for CPU2
+      len: 5
-    bit_offset: 1
+      stride: 1
-    bit_size: 1
-  - name: EWUP3
-    description: Enable Wakeup pin WKUP3 for CPU2
-    bit_offset: 2
-    bit_size: 1
-  - name: EWUP4
-    description: Enable Wakeup pin WKUP4 for CPU2
-    bit_offset: 3
-    bit_size: 1
-  - name: EWUP5
-    description: Enable Wakeup pin WKUP5 for CPU2
-    bit_offset: 4
-    bit_size: 1
   - name: EBLEWUP
     description: Enable BLE host wakeup interrupt for CPU2
     bit_offset: 9
@@ -181,6 +168,7 @@ fieldset/CR1:
     description: Voltage scaling range selection
     bit_offset: 9
     bit_size: 2
+    enum: VOS
   - name: LPR
     description: Low-power run
     bit_offset: 14
@@ -211,26 +199,13 @@ fieldset/CR2:
 fieldset/CR3:
   description: Power control register 3
   fields:
-  - name: EWUP1
+  - name: EWUP
-    description: Enable Wakeup pin WKUP1
+    description: Enable Wakeup pin
     bit_offset: 0
     bit_size: 1
-  - name: EWUP2
+    array:
-    description: Enable Wakeup pin WKUP2
+      len: 5
-    bit_offset: 1
+      stride: 1
-    bit_size: 1
-  - name: EWUP3
-    description: Enable Wakeup pin WKUP3
-    bit_offset: 2
-    bit_size: 1
-  - name: EWUP4
-    description: Enable Wakeup pin WKUP4
-    bit_offset: 3
-    bit_size: 1
-  - name: EWUP5
-    description: Enable Wakeup pin WKUP5
-    bit_offset: 4
-    bit_size: 1
   - name: EBORHSDFB
     description: Enable BORH and Step Down counverter forced in Bypass interrups for CPU1
     bit_offset: 8
@@ -270,22 +245,9 @@ fieldset/CR4:
     description: Wakeup pin WKUP1 polarity
     bit_offset: 0
     bit_size: 1
-  - name: WP2
+    array:
-    description: Wakeup pin WKUP2 polarity
+      len: 5
-    bit_offset: 1
+      stride: 1
-    bit_size: 1
-  - name: WP3
-    description: Wakeup pin WKUP3 polarity
-    bit_offset: 2
-    bit_size: 1
-  - name: WP4
-    description: Wakeup pin WKUP4 polarity
-    bit_offset: 3
-    bit_size: 1
-  - name: WP5
-    description: Wakeup pin WKUP5 polarity
-    bit_offset: 4
-    bit_size: 1
   - name: VBE
     description: VBAT battery charging enable
     bit_offset: 8
@@ -368,625 +330,26 @@ fieldset/EXTSCR:
     description: CPU2 deepsleep mode
     bit_offset: 15
     bit_size: 1
-fieldset/PDCRA:
+fieldset/PXCR:
-  description: Power Port A pull-down control register
+  description: Power Port pull-up/down control register
   fields:
-  - name: PD0
+  - name: PD
-    description: Port A pull-down bit y (y=0..15)
+    description: Port A pull-up/down bit y (y=0..15)
     bit_offset: 0
     bit_size: 1
-  - name: PD1
+    array:
-    description: Port A pull-down bit y (y=0..15)
+      len: 16
-    bit_offset: 1
+      stride: 1
-    bit_size: 1
-  - name: PD2
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PD3
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PD4
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-  - name: PD5
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PD6
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PD7
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PD8
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PD9
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PD10
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PD11
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PD12
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PD14
-    description: Port A pull-down bit y (y=0..15)
-    bit_offset: 14
-    bit_size: 1
-fieldset/PDCRB:
-  description: Power Port B pull-down control register
-  fields:
-  - name: PD0
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PD1
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PD2
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PD3
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PD5
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PD6
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PD7
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PD8
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PD9
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PD10
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PD11
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PD12
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PD13
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 13
-    bit_size: 1
-  - name: PD14
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 14
-    bit_size: 1
-  - name: PD15
-    description: Port B pull-down bit y (y=0..15)
-    bit_offset: 15
-    bit_size: 1
-fieldset/PDCRC:
-  description: Power Port C pull-down control register
-  fields:
-  - name: PD0
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PD1
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PD2
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PD3
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PD4
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-  - name: PD5
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PD6
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PD7
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PD8
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PD9
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PD10
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PD11
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PD12
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PD13
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 13
-    bit_size: 1
-  - name: PD14
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 14
-    bit_size: 1
-  - name: PD15
-    description: Port C pull-down bit y (y=0..15)
-    bit_offset: 15
-    bit_size: 1
-fieldset/PDCRD:
-  description: Power Port D pull-down control register
-  fields:
-  - name: PD0
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PD1
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PD2
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PD3
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PD4
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-  - name: PD5
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PD6
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PD7
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PD8
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PD9
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PD10
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PD11
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PD12
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PD13
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 13
-    bit_size: 1
-  - name: PD14
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 14
-    bit_size: 1
-  - name: PD15
-    description: Port D pull-down bit y (y=0..15)
-    bit_offset: 15
-    bit_size: 1
-fieldset/PDCRE:
-  description: Power Port E pull-down control register
-  fields:
-  - name: PD0
-    description: Port E pull-down bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PD1
-    description: Port E pull-down bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PD2
-    description: Port E pull-down bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PD3
-    description: Port E pull-down bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PD4
-    description: Port E pull-down bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-fieldset/PDCRH:
-  description: Power Port H pull-down control register
-  fields:
-  - name: PD0
-    description: Port H pull-down bit y (y=0..1)
-    bit_offset: 0
-    bit_size: 1
-  - name: PD1
-    description: Port H pull-down bit y (y=0..1)
-    bit_offset: 1
-    bit_size: 1
-  - name: PD3
-    description: Port H pull-down bit y (y=0..1)
-    bit_offset: 3
-    bit_size: 1
-fieldset/PUCRA:
-  description: Power Port A pull-up control register
-  fields:
-  - name: PU0
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PU1
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PU2
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PU3
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PU4
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-  - name: PU5
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PU6
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PU7
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PU8
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PU9
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PU10
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PU11
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PU12
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PU13
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 13
-    bit_size: 1
-  - name: PU15
-    description: Port A pull-up bit y (y=0..15)
-    bit_offset: 15
-    bit_size: 1
-fieldset/PUCRB:
-  description: Power Port B pull-up control register
-  fields:
-  - name: PU0
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PU1
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PU2
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PU3
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PU4
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-  - name: PU5
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PU6
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PU7
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PU8
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PU9
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PU10
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PU11
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PU12
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PU13
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 13
-    bit_size: 1
-  - name: PU14
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 14
-    bit_size: 1
-  - name: PU15
-    description: Port B pull-up bit y (y=0..15)
-    bit_offset: 15
-    bit_size: 1
-fieldset/PUCRC:
-  description: Power Port C pull-up control register
-  fields:
-  - name: PU0
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PU1
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PU2
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PU3
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PU4
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-  - name: PU5
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PU6
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PU7
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PU8
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PU9
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PU10
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PU11
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PU12
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PU13
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 13
-    bit_size: 1
-  - name: PU14
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 14
-    bit_size: 1
-  - name: PU15
-    description: Port C pull-up bit y (y=0..15)
-    bit_offset: 15
-    bit_size: 1
-fieldset/PUCRD:
-  description: Power Port D pull-up control register
-  fields:
-  - name: PU0
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PU1
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PU2
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PU3
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PU4
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-  - name: PU5
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 5
-    bit_size: 1
-  - name: PU6
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 6
-    bit_size: 1
-  - name: PU7
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 7
-    bit_size: 1
-  - name: PU8
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 8
-    bit_size: 1
-  - name: PU9
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 9
-    bit_size: 1
-  - name: PU10
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 10
-    bit_size: 1
-  - name: PU11
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 11
-    bit_size: 1
-  - name: PU12
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 12
-    bit_size: 1
-  - name: PU13
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 13
-    bit_size: 1
-  - name: PU14
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 14
-    bit_size: 1
-  - name: PU15
-    description: Port D pull-up bit y (y=0..15)
-    bit_offset: 15
-    bit_size: 1
-fieldset/PUCRE:
-  description: Power Port E pull-up control register
-  fields:
-  - name: PU0
-    description: Port E pull-up bit y (y=0..15)
-    bit_offset: 0
-    bit_size: 1
-  - name: PU1
-    description: Port E pull-up bit y (y=0..15)
-    bit_offset: 1
-    bit_size: 1
-  - name: PU2
-    description: Port E pull-up bit y (y=0..15)
-    bit_offset: 2
-    bit_size: 1
-  - name: PU3
-    description: Port E pull-up bit y (y=0..15)
-    bit_offset: 3
-    bit_size: 1
-  - name: PU4
-    description: Port E pull-up bit y (y=0..15)
-    bit_offset: 4
-    bit_size: 1
-fieldset/PUCRH:
-  description: Power Port H pull-up control register
-  fields:
-  - name: PU0
-    description: Port H pull-up bit y (y=0..1)
-    bit_offset: 0
-    bit_size: 1
-  - name: PU1
-    description: Port H pull-up bit y (y=0..1)
-    bit_offset: 1
-    bit_size: 1
-  - name: PU3
-    description: Port H pull-up bit y (y=0..1)
-    bit_offset: 3
-    bit_size: 1
 fieldset/SCR:
   description: Power status clear register
   fields:
-  - name: CWUF1
+  - name: CWUF
     description: Clear wakeup flag 1
     bit_offset: 0
     bit_size: 1
-  - name: CWUF2
+    array:
-    description: Clear wakeup flag 2
+      len: 5
-    bit_offset: 1
+      stride: 1
-    bit_size: 1
-  - name: CWUF3
-    description: Clear wakeup flag 3
-    bit_offset: 2
-    bit_size: 1
-  - name: CWUF4
-    description: Clear wakeup flag 4
-    bit_offset: 3
-    bit_size: 1
-  - name: CWUF5
-    description: Clear wakeup flag 5
-    bit_offset: 4
-    bit_size: 1
   - name: CSMPSFBF
     description: Clear SMPS Step Down converter forced in Bypass interrupt flag
     bit_offset: 7
@@ -1022,26 +385,13 @@ fieldset/SCR:
 fieldset/SR1:
   description: Power status register 1
   fields:
-  - name: CWUF1
+  - name: CWUF
     description: Wakeup flag 1
     bit_offset: 0
     bit_size: 1
-  - name: CWUF2
+    array:
-    description: Wakeup flag 2
+      len: 5
-    bit_offset: 1
+      stride: 1
-    bit_size: 1
-  - name: CWUF3
-    description: Wakeup flag 3
-    bit_offset: 2
-    bit_size: 1
-  - name: CWUF4
-    description: Wakeup flag 4
-    bit_offset: 3
-    bit_size: 1
-  - name: CWUF5
-    description: Wakeup flag 5
-    bit_offset: 4
-    bit_size: 1
   - name: SDFBF
     description: Step Down converter forced in Bypass interrupt flag
     bit_offset: 7
@@ -1113,3 +463,12 @@ fieldset/SR2:
     description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V'
     bit_offset: 14
     bit_size: 1
+enum/VOS:
+  bit_size: 2
+  variants:
+  - name: Range1
+    description: Range 1
+    value: 1
+  - name: Range2
+    description: Range 2
+    value: 2

data/registers/pwr_wl5.yaml

@@ -163,7 +163,6 @@ fieldset/CR2:
     description: Power voltage detector enable
     bit_offset: 0
     bit_size: 1
-    enum: PVDE
   - name: PLS
     description: Power voltage detector level selection.
     bit_offset: 1
@@ -195,7 +194,6 @@ fieldset/CR3:
     description: SRAM2 retention in Standby mode
     bit_offset: 9
     bit_size: 1
-    enum: RRS
   - name: APC
     description: Apply pull-up and pull-down configuration from CPU1
     bit_offset: 10
@@ -204,12 +202,10 @@ fieldset/CR3:
     description: Enable Radio BUSY Wakeup from Standby for CPU1
     bit_offset: 11
     bit_size: 1
-    enum: EWRFBUSY
   - name: EWRFIRQ
-    description: akeup for CPU1
+    description: Wakeup for CPU1
     bit_offset: 13
     bit_size: 1
-    enum: EWRFIRQ
   - name: EC2H
     description: nable CPU2 Hold interrupt for CPU1
     bit_offset: 14
@@ -233,7 +229,6 @@ fieldset/CR4:
     description: VBAT battery charging enable
     bit_offset: 8
     bit_size: 1
-    enum: VBE
   - name: VBRS
     description: VBAT battery charging resistor selection
     bit_offset: 9
@@ -243,7 +238,6 @@ fieldset/CR4:
     description: Wakeup Radio BUSY polarity
     bit_offset: 11
     bit_size: 1
-    enum: WRFBUSYP
   - name: C2BOOT
     description: oot CPU2 after reset or wakeup from Stop or Standby modes.
     bit_offset: 15
@@ -255,12 +249,10 @@ fieldset/CR5:
     description: Enable Radio End Of Life detector enabled
     bit_offset: 14
     bit_size: 1
-    enum: RFEOLEN
   - name: SMPSEN
     description: Enable SMPS Step Down converter SMPS mode enabled.
     bit_offset: 15
     bit_size: 1
-    enum: SMPSEN
 fieldset/EXTSCR:
   description: Power extended status and status clear register
   fields:
@@ -276,17 +268,14 @@ fieldset/EXTSCR:
     description: System Standby flag for CPU1. (no core states retained)
     bit_offset: 8
     bit_size: 1
-    enum: CSBF
   - name: C1STOP2F
     description: System Stop2 flag for CPU1. (partial core states retained)
     bit_offset: 9
     bit_size: 1
-    enum: CSTOPF
   - name: C1STOPF
     description: System Stop0, 1 flag for CPU1. (All core states retained)
     bit_offset: 10
     bit_size: 1
-    enum: CSTOPF
   - name: C2SBF
     description: ystem Standby flag for CPU2. (no core states retained)
     bit_offset: 11
@@ -364,17 +353,14 @@ fieldset/SR1:
     array:
       len: 3
       stride: 1
-    enum: WUF
   - name: WPVDF
     description: Wakeup PVD flag
     bit_offset: 8
     bit_size: 1
-    enum: WPVDF
   - name: WRFBUSYF
     description: Radio BUSY wakeup flag
     bit_offset: 11
     bit_size: 1
-    enum: WRFBUSYF
   - name: C2HF
     description: PU2 Hold interrupt flag
     bit_offset: 14
@@ -383,7 +369,6 @@ fieldset/SR1:
     description: Internal wakeup interrupt flag
     bit_offset: 15
     bit_size: 1
-    enum: WUFI
 fieldset/SR2:
   description: Power status register 2
   fields:
@@ -395,62 +380,50 @@ fieldset/SR2:
     description: Radio BUSY signal status
     bit_offset: 1
     bit_size: 1
-    enum: RFBUSYS
   - name: RFBUSYMS
     description: Radio BUSY masked signal status
     bit_offset: 2
     bit_size: 1
-    enum: RFBUSYMS
   - name: SMPSRDY
     description: SMPS ready flag
     bit_offset: 3
     bit_size: 1
-    enum: SMPSRDY
   - name: LDORDY
     description: LDO ready flag
     bit_offset: 4
     bit_size: 1
-    enum: LDORDY
   - name: RFEOLF
     description: Radio end of life flag
     bit_offset: 5
     bit_size: 1
-    enum: RFEOLF
   - name: REGMRS
     description: regulator2 low power flag
     bit_offset: 6
     bit_size: 1
-    enum: REGMRS
   - name: FLASHRDY
     description: Flash ready
     bit_offset: 7
     bit_size: 1
-    enum: FLASHRDY
   - name: REGLPS
     description: regulator1 started
     bit_offset: 8
     bit_size: 1
-    enum: REGLPS
   - name: REGLPF
     description: regulator1 low power flag
     bit_offset: 9
     bit_size: 1
-    enum: REGLPF
   - name: VOSF
     description: Voltage scaling flag
     bit_offset: 10
     bit_size: 1
-    enum: VOSF
   - name: PVDO
     description: Power voltage detector output
     bit_offset: 11
     bit_size: 1
-    enum: PVDO
   - name: PVMO
     description: 'Peripheral voltage monitoring output: VDDA vs. 1.62 V'
     bit_offset: 14
     bit_size: 1
-    enum: PVMO
 fieldset/SUBGHZSPICR:
   description: Power SPI3 control register
   fields:
@@ -458,7 +431,6 @@ fieldset/SUBGHZSPICR:
     description: sub-GHz SPI NSS control
     bit_offset: 15
     bit_size: 1
-    enum: NSS
 enum/CDS:
   bit_size: 1
   variants:
@@ -468,51 +440,6 @@ enum/CDS:
   - name: DeepSleep
     description: CPU is in Deep-Sleep
     value: 1
-enum/CSBF:
-  bit_size: 1
-  variants:
-  - name: NoStandby
-    description: System has not been in Standby mode
-    value: 0
-  - name: Standby
-    description: System has been in Standby mode
-    value: 1
-enum/CSTOPF:
-  bit_size: 1
-  variants:
-  - name: NoStop
-    description: System has not been in Stop 2 mode
-    value: 0
-  - name: Stop
-    description: System has been in Stop 2 mode
-    value: 1
-enum/EWRFBUSY:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Radio Busy is disabled and does not trigger a wakeup from Standby event to CPUwhen a rising or a falling edge occurs
-    value: 0
-  - name: Enabled
-    description: Radio Busy is enabled and triggers a wakeup from Standby event to CPUwhen a rising or a falling edge occurs. The active edge is configured via the WRFBUSYP bit in PWR_CR4
-    value: 1
-enum/EWRFIRQ:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Radio IRQ[2:0] is disabled and does not trigger a wakeup from Standby event to CPU.
-    value: 0
-  - name: Enabled
-    description: Radio IRQ[2:0] is enabled and triggers a wakeup from Standby event to CPU.
-    value: 1
-enum/FLASHRDY:
-  bit_size: 1
-  variants:
-  - name: NotReady
-    description: Flash memory not ready to be accessed
-    value: 0
-  - name: Ready
-    description: Flash memory ready to be accessed
-    value: 1
 enum/FPDR:
   bit_size: 1
   variants:
@@ -531,15 +458,6 @@ enum/FPDS:
   - name: PowerDown
     description: Flash memory in Power-down mode when system is in LPSleep mode
     value: 1
-enum/LDORDY:
-  bit_size: 1
-  variants:
-  - name: NotReady
-    description: LDO not ready or off
-    value: 0
-  - name: Ready
-    description: LDO ready
-    value: 1
 enum/LPMS:
   bit_size: 3
   variants:
@@ -567,15 +485,6 @@ enum/LPR:
   - name: LowPowerMode
     description: Voltage regulator in low-power mode in Low-power run mode
     value: 1
-enum/NSS:
-  bit_size: 1
-  variants:
-  - name: Low
-    description: Sub-GHz SPI NSS signal at level low
-    value: 0
-  - name: High
-    description: Sub-GHz SPI NSS signal is at level high
-    value: 1
 enum/PLS:
   bit_size: 3
   variants:
@@ -603,123 +512,6 @@ enum/PLS:
   - name: External
     description: External input analog voltage PVD_IN (compared internally to VREFINT)
     value: 7
-enum/PVDE:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: PVD Disabled
-    value: 0
-  - name: Enabled
-    description: PVD Enabled
-    value: 1
-enum/PVDO:
-  bit_size: 1
-  variants:
-  - name: Above
-    description: VDD or voltage level on PVD_IN above the selected PVD threshold
-    value: 0
-  - name: Below
-    description: VDD or voltage level on PVD_IN below the selected PVD threshold
-    value: 1
-enum/PVMO:
-  bit_size: 1
-  variants:
-  - name: Above
-    description: VDDA voltage above PVM3 threshold (around 1.62 V)
-    value: 0
-  - name: Below
-    description: VDDA voltage below PVM3 threshold (around 1.62 V)
-    value: 1
-enum/REGLPF:
-  bit_size: 1
-  variants:
-  - name: Main
-    description: Main regulator (MR) ready and used
-    value: 0
-  - name: LowPower
-    description: Low-power regulator (LPR) used
-    value: 1
-enum/REGLPS:
-  bit_size: 1
-  variants:
-  - name: NotReady
-    description: LPR not ready
-    value: 0
-  - name: Ready
-    description: LPR ready
-    value: 1
-enum/REGMRS:
-  bit_size: 1
-  variants:
-  - name: V_DD
-    description: Main regulator supplied directly from VDD
-    value: 0
-  - name: LDO_SMPS
-    description: Main regulator supplied through LDO or SMPS
-    value: 1
-enum/RFBUSYMS:
-  bit_size: 1
-  variants:
-  - name: NotBusy
-    description: radio busy masked signal low (not busy)
-    value: 0
-  - name: Busy
-    description: radio busy masked signal high (busy)
-    value: 1
-enum/RFBUSYS:
-  bit_size: 1
-  variants:
-  - name: NotBusy
-    description: radio busy signal low (not busy)
-    value: 0
-  - name: Busy
-    description: radio busy signal high (busy)
-    value: 1
-enum/RFEOLEN:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: Radio end-of-life detector disabled
-    value: 0
-  - name: Enabled
-    description: Radio end-of-life detector enabled
-    value: 1
-enum/RFEOLF:
-  bit_size: 1
-  variants:
-  - name: Above
-    description: Supply voltage above radio end-of-life operating low level
-    value: 0
-  - name: Below
-    description: Supply voltage below radio end-of-life operating low level
-    value: 1
-enum/RRS:
-  bit_size: 1
-  variants:
-  - name: PowerOff
-    description: SRAM2 powered off in Standby mode (SRAM2 content lost)
-    value: 0
-  - name: OnLPR
-    description: SRAM2 powered by the low-power regulator in Standby mode (SRAM2 content kept)
-    value: 1
-enum/SMPSEN:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: SMPS step-down converter SMPS mode disabled (LDO mode enabled)
-    value: 0
-  - name: Enabled
-    description: SMPS step-down converter SMPS mode enabled
-    value: 1
-enum/SMPSRDY:
-  bit_size: 1
-  variants:
-  - name: NotReady
-    description: SMPS step-down converter not ready or off
-    value: 0
-  - name: Ready
-    description: SMPS step-down converter ready
-    value: 1
 enum/SUBGHZSPINSSSEL:
   bit_size: 1
   variants:
@@ -729,15 +521,6 @@ enum/SUBGHZSPINSSSEL:
   - name: LPTIM3
     description: sub-GHz SPI NSS signal driven from LPTIM3_OUT (RFBUSYMS functionality disabled)
     value: 1
-enum/VBE:
-  bit_size: 1
-  variants:
-  - name: Disabled
-    description: VBAT battery charging disabled
-    value: 0
-  - name: Enabled
-    description: VBAT battery charging enabled
-    value: 1
 enum/VBRS:
   bit_size: 1
   variants:
@@ -750,21 +533,12 @@ enum/VBRS:
 enum/VOS:
   bit_size: 2
   variants:
-  - name: V1_2
+  - name: Range1
     description: 1.2 V (range 1)
     value: 1
-  - name: V1_0
+  - name: Range2
     description: 1.0 V (range 2)
     value: 2
-enum/VOSF:
-  bit_size: 1
-  variants:
-  - name: Ready
-    description: Regulator ready in the selected voltage range
-    value: 0
-  - name: Change
-    description: Regulator output voltage changed to the required voltage level
-    value: 1
 enum/WP:
   bit_size: 1
   variants:
@@ -774,48 +548,3 @@ enum/WP:
   - name: FallingEdge
     description: Detection on low level (falling edge)
     value: 1
-enum/WPVDF:
-  bit_size: 1
-  variants:
-  - name: Clear
-    description: No wakeup event detected on PVD
-    value: 0
-  - name: Wakeup
-    description: Wakeup event detected on PVD
-    value: 1
-enum/WRFBUSYF:
-  bit_size: 1
-  variants:
-  - name: Clear
-    description: No wakeup event detected on radio busy
-    value: 0
-  - name: Wakeup
-    description: Wakeup event detected on radio busy
-    value: 1
-enum/WRFBUSYP:
-  bit_size: 1
-  variants:
-  - name: RisingEdge
-    description: Detection on high level (rising edge)
-    value: 0
-  - name: FallingEdge
-    description: Detection on low level (falling edge)
-    value: 1
-enum/WUF:
-  bit_size: 1
-  variants:
-  - name: Clear
-    description: No wakeup event detected on WKUP3
-    value: 0
-  - name: Wakeup
-    description: Wakeup event detected on WKUP3
-    value: 1
-enum/WUFI:
-  bit_size: 1
-  variants:
-  - name: Clear
-    description: All internal wakeup sources are cleared
-    value: 0
-  - name: Wakeup
-    description: wakeup is detected on the internal wakeup line
-    value: 1

data/registers/rcc_f0.yaml

@@ -444,7 +444,7 @@ fieldset/CFGR:
     description: System Clock Switch Status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -1043,21 +1043,6 @@ enum/RTCSEL:
     description: HSE oscillator clock divided by a prescaler used as RTC clock
     value: 3
 enum/SW:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as system clock
-    value: 0
-  - name: HSE
-    description: HSE selected as system clock
-    value: 1
-  - name: PLL
-    description: PLL selected as system clock
-    value: 2
-  - name: HSI48
-    description: HSI48 selected as system clock (when available)
-    value: 3
-enum/SWS:
   bit_size: 2
   variants:
   - name: HSI

data/registers/rcc_f1.yaml

@@ -452,7 +452,7 @@ fieldset/CFGR:
     description: System Clock Switch Status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -462,12 +462,12 @@ fieldset/CFGR:
     description: APB Low speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: PPRE2
     description: APB High speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: ADCPRE
     description: ADC prescaler
     bit_offset: 14
@@ -783,7 +783,7 @@ enum/PLLXTPRE:
   - name: Div2
     description: HSE clock divided by 2
     value: 1
-enum/PPRE1:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1
@@ -828,18 +828,6 @@ enum/SW:
   - name: PLL
     description: PLL selected as system clock
     value: 2
-enum/SWS:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI oscillator used as system clock
-    value: 0
-  - name: HSE
-    description: HSE oscillator used as system clock
-    value: 1
-  - name: PLL
-    description: PLL used as system clock
-    value: 2
 enum/USBPRE:
   bit_size: 1
   variants:

data/registers/rcc_f100.yaml

@@ -420,7 +420,7 @@ fieldset/CFGR:
     description: System Clock Switch Status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -430,12 +430,12 @@ fieldset/CFGR:
     description: APB Low speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: PPRE2
     description: APB High speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: ADCPRE
     description: ADC prescaler
     bit_offset: 14
@@ -754,7 +754,7 @@ enum/PLLXTPRE:
   - name: Div2
     description: HSE clock divided by 2
     value: 1
-enum/PPRE1:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1
@@ -850,15 +850,3 @@ enum/SW:
   - name: PLL
     description: PLL selected as system clock
     value: 2
-enum/SWS:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI oscillator used as system clock
-    value: 0
-  - name: HSE
-    description: HSE oscillator used as system clock
-    value: 1
-  - name: PLL
-    description: PLL used as system clock
-    value: 2

data/registers/rcc_f1cl.yaml

@@ -399,7 +399,7 @@ fieldset/CFGR:
     description: System Clock Switch Status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -409,12 +409,12 @@ fieldset/CFGR:
     description: APB Low speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: PPRE2
     description: APB High speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
-    enum: PPRE1
+    enum: PPRE
   - name: ADCPRE
     description: ADC prescaler
     bit_offset: 14
@@ -832,7 +832,7 @@ enum/PLLXTPRE:
   - name: Div2
     description: HSE clock divided by 2
     value: 1
-enum/PPRE1:
+enum/PPRE:
   bit_size: 3
   variants:
   - name: Div1
@@ -926,18 +926,6 @@ enum/RTCSEL:
     description: HSE oscillator clock divided by a prescaler used as RTC clock
     value: 3
 enum/SW:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as system clock
-    value: 0
-  - name: HSE
-    description: HSE selected as system clock
-    value: 1
-  - name: PLL
-    description: PLL selected as system clock
-    value: 2
-enum/SWS:
   bit_size: 2
   variants:
   - name: HSI

data/registers/rcc_f2.yaml

@@ -894,7 +894,7 @@ fieldset/CFGR:
     description: System clock switch status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -1337,15 +1337,3 @@ enum/SW:
   - name: PLL
     description: PLL selected as system clock
     value: 2
-enum/SWS:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI oscillator used as system clock
-    value: 0
-  - name: HSE
-    description: HSE oscillator used as system clock
-    value: 1
-  - name: PLL
-    description: PLL used as system clock
-    value: 2

data/registers/rcc_f3.yaml

@@ -496,7 +496,7 @@ fieldset/CFGR:
     description: System Clock Switch Status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -1236,18 +1236,6 @@ enum/SDPRE:
     description: SYSCLK divided by 48
     value: 31
 enum/SW:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as system clock
-    value: 0
-  - name: HSE
-    description: HSE selected as system clock
-    value: 1
-  - name: PLL
-    description: PLL selected as system clock
-    value: 2
-enum/SWS:
   bit_size: 2
   variants:
   - name: HSI

data/registers/rcc_f3_v2.yaml

@@ -472,7 +472,7 @@ fieldset/CFGR:
     description: System Clock Switch Status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -1212,18 +1212,6 @@ enum/SDPRE:
     description: SYSCLK divided by 48
     value: 31
 enum/SW:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as system clock
-    value: 0
-  - name: HSE
-    description: HSE selected as system clock
-    value: 1
-  - name: PLL
-    description: PLL selected as system clock
-    value: 2
-enum/SWS:
   bit_size: 2
   variants:
   - name: HSI

data/registers/rcc_f4.yaml

@@ -1223,7 +1223,7 @@ fieldset/CFGR:
     description: System clock switch status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -2513,18 +2513,6 @@ enum/SPREADSEL:
     description: Down spread
     value: 1
 enum/SW:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as system clock
-    value: 0
-  - name: HSE
-    description: HSE selected as system clock
-    value: 1
-  - name: PLL
-    description: PLL selected as system clock
-    value: 2
-enum/SWS:
   bit_size: 2
   variants:
   - name: HSI

data/registers/rcc_f410.yaml

@@ -504,7 +504,7 @@ fieldset/CFGR:
     description: System clock switch status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -972,18 +972,6 @@ enum/SPREADSEL:
     description: Down spread
     value: 1
 enum/SW:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as system clock
-    value: 0
-  - name: HSE
-    description: HSE selected as system clock
-    value: 1
-  - name: PLL
-    description: PLL selected as system clock
-    value: 2
-enum/SWS:
   bit_size: 2
   variants:
   - name: HSI

data/registers/rcc_f7.yaml

@@ -1215,7 +1215,7 @@ fieldset/CFGR:
     description: System clock switch status
     bit_offset: 2
     bit_size: 2
-    enum: SWS
+    enum: SW
   - name: HPRE
     description: AHB prescaler
     bit_offset: 4
@@ -2190,18 +2190,6 @@ enum/SPREADSEL:
     description: Down spread
     value: 1
 enum/SW:
-  bit_size: 2
-  variants:
-  - name: HSI
-    description: HSI selected as system clock
-    value: 0
-  - name: HSE
-    description: HSE selected as system clock
-    value: 1
-  - name: PLL
-    description: PLL selected as system clock
-    value: 2
-enum/SWS:
   bit_size: 2
   variants:
   - name: HSI

data/registers/rcc_h7.yaml

@@ -48,14 +48,14 @@ block/RCC:
       len: 3
       stride: 8
     byte_offset: 48
-    fieldset: PLL1DIVR
+    fieldset: PLLDIVR
   - name: PLLFRACR
     description: RCC PLL1 Fractional Divider Register
     array:
       len: 3
       stride: 8
     byte_offset: 52
-    fieldset: PLL1FRACR
+    fieldset: PLLFRACR
   - name: D1CCIPR
     description: RCC Domain 1 Kernel Clock Configuration Register
     byte_offset: 76
@@ -2760,7 +2760,7 @@ fieldset/CFGR:
     description: System clock switch status
     bit_offset: 3
     bit_size: 3
-    enum: SWS
+    enum: SW
   - name: STOPWUCK
     description: System clock selection after a wake up from system Stop
     bit_offset: 6
@@ -3075,7 +3075,7 @@ fieldset/D1CFGR:
     description: D1 domain APB3 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D1CPRE
     description: D1 domain Core prescaler
     bit_offset: 8
@@ -3169,12 +3169,12 @@ fieldset/D2CFGR:
     description: D2 domain APB1 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D2PPRE2
     description: D2 domain APB2 prescaler
     bit_offset: 8
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/D3AMR:
   description: RCC D3 Autonomous mode Register
   fields:
@@ -3304,7 +3304,7 @@ fieldset/D3CFGR:
     description: D3 domain APB4 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/GCR:
   description: Global Control Register
   fields:
@@ -3354,85 +3354,6 @@ fieldset/ICSCR:
     description: CSI clock trimming
     bit_offset: 26
     bit_size: 5
-fieldset/PLL1DIVR:
-  description: RCC PLL1 Dividers Configuration Register
-  fields:
-  - name: DIVN1
-    description: Multiplication factor for PLL1 VCO
-    bit_offset: 0
-    bit_size: 9
-  - name: DIVP1
-    description: PLL1 DIVP division factor
-    bit_offset: 9
-    bit_size: 7
-    enum: DIVP
-  - name: DIVQ1
-    description: PLL1 DIVQ division factor
-    bit_offset: 16
-    bit_size: 7
-  - name: DIVR1
-    description: PLL1 DIVR division factor
-    bit_offset: 24
-    bit_size: 7
-fieldset/PLL1FRACR:
-  description: RCC PLL1 Fractional Divider Register
-  fields:
-  - name: FRACN1
-    description: Fractional part of the multiplication factor for PLL1 VCO
-    bit_offset: 3
-    bit_size: 13
-fieldset/PLL2DIVR:
-  description: RCC PLL2 Dividers Configuration Register
-  fields:
-  - name: DIVN2
-    description: Multiplication factor for PLL1 VCO
-    bit_offset: 0
-    bit_size: 9
-  - name: DIVP2
-    description: PLL1 DIVP division factor
-    bit_offset: 9
-    bit_size: 7
-  - name: DIVQ2
-    description: PLL1 DIVQ division factor
-    bit_offset: 16
-    bit_size: 7
-  - name: DIVR2
-    description: PLL1 DIVR division factor
-    bit_offset: 24
-    bit_size: 7
-fieldset/PLL2FRACR:
-  description: RCC PLL2 Fractional Divider Register
-  fields:
-  - name: FRACN2
-    description: Fractional part of the multiplication factor for PLL VCO
-    bit_offset: 3
-    bit_size: 13
-fieldset/PLL3DIVR:
-  description: RCC PLL3 Dividers Configuration Register
-  fields:
-  - name: DIVN3
-    description: Multiplication factor for PLL1 VCO
-    bit_offset: 0
-    bit_size: 9
-  - name: DIVP3
-    description: PLL DIVP division factor
-    bit_offset: 9
-    bit_size: 7
-  - name: DIVQ3
-    description: PLL DIVQ division factor
-    bit_offset: 16
-    bit_size: 7
-  - name: DIVR3
-    description: PLL DIVR division factor
-    bit_offset: 24
-    bit_size: 7
-fieldset/PLL3FRACR:
-  description: RCC PLL3 Fractional Divider Register
-  fields:
-  - name: FRACN3
-    description: Fractional part of the multiplication factor for PLL3 VCO
-    bit_offset: 3
-    bit_size: 13
 fieldset/PLLCFGR:
   description: RCC PLLs Configuration Register
   fields:
@@ -3495,6 +3416,32 @@ fieldset/PLLCKSELR:
     array:
       len: 3
       stride: 8
+fieldset/PLLDIVR:
+  description: RCC PLL1 Dividers Configuration Register
+  fields:
+  - name: PLLN
+    description: Multiplication factor for PLL1 VCO
+    bit_offset: 0
+    bit_size: 9
+  - name: PLLP
+    description: PLL DIVP division factor
+    bit_offset: 9
+    bit_size: 7
+  - name: PLLQ
+    description: PLL DIVQ division factor
+    bit_offset: 16
+    bit_size: 7
+  - name: PLLR
+    description: PLL DIVR division factor
+    bit_offset: 24
+    bit_size: 7
+fieldset/PLLFRACR:
+  description: RCC PLL Fractional Divider Register
+  fields:
+  - name: FRACN
+    description: Fractional part of the multiplication factor for PLL VCO
+    bit_offset: 3
+    bit_size: 13
 fieldset/RSR:
   description: RCC Reset Status Register
   fields:
@@ -3587,222 +3534,6 @@ enum/DFSDMSEL:
   - name: SYS
     description: System clock selected as peripheral clock
     value: 1
-enum/DIVP:
-  bit_size: 7
-  variants:
-  - name: Div1
-    description: pll_p_ck = vco_ck
-    value: 0
-  - name: Div2
-    description: pll_p_ck = vco_ck / 2
-    value: 1
-  - name: Div4
-    description: pll_p_ck = vco_ck / 4
-    value: 3
-  - name: Div6
-    description: pll_p_ck = vco_ck / 6
-    value: 5
-  - name: Div8
-    description: pll_p_ck = vco_ck / 8
-    value: 7
-  - name: Div10
-    description: pll_p_ck = vco_ck / 10
-    value: 9
-  - name: Div12
-    description: pll_p_ck = vco_ck / 12
-    value: 11
-  - name: Div14
-    description: pll_p_ck = vco_ck / 14
-    value: 13
-  - name: Div16
-    description: pll_p_ck = vco_ck / 16
-    value: 15
-  - name: Div18
-    description: pll_p_ck = vco_ck / 18
-    value: 17
-  - name: Div20
-    description: pll_p_ck = vco_ck / 20
-    value: 19
-  - name: Div22
-    description: pll_p_ck = vco_ck / 22
-    value: 21
-  - name: Div24
-    description: pll_p_ck = vco_ck / 24
-    value: 23
-  - name: Div26
-    description: pll_p_ck = vco_ck / 26
-    value: 25
-  - name: Div28
-    description: pll_p_ck = vco_ck / 28
-    value: 27
-  - name: Div30
-    description: pll_p_ck = vco_ck / 30
-    value: 29
-  - name: Div32
-    description: pll_p_ck = vco_ck / 32
-    value: 31
-  - name: Div34
-    description: pll_p_ck = vco_ck / 34
-    value: 33
-  - name: Div36
-    description: pll_p_ck = vco_ck / 36
-    value: 35
-  - name: Div38
-    description: pll_p_ck = vco_ck / 38
-    value: 37
-  - name: Div40
-    description: pll_p_ck = vco_ck / 40
-    value: 39
-  - name: Div42
-    description: pll_p_ck = vco_ck / 42
-    value: 41
-  - name: Div44
-    description: pll_p_ck = vco_ck / 44
-    value: 43
-  - name: Div46
-    description: pll_p_ck = vco_ck / 46
-    value: 45
-  - name: Div48
-    description: pll_p_ck = vco_ck / 48
-    value: 47
-  - name: Div50
-    description: pll_p_ck = vco_ck / 50
-    value: 49
-  - name: Div52
-    description: pll_p_ck = vco_ck / 52
-    value: 51
-  - name: Div54
-    description: pll_p_ck = vco_ck / 54
-    value: 53
-  - name: Div56
-    description: pll_p_ck = vco_ck / 56
-    value: 55
-  - name: Div58
-    description: pll_p_ck = vco_ck / 58
-    value: 57
-  - name: Div60
-    description: pll_p_ck = vco_ck / 60
-    value: 59
-  - name: Div62
-    description: pll_p_ck = vco_ck / 62
-    value: 61
-  - name: Div64
-    description: pll_p_ck = vco_ck / 64
-    value: 63
-  - name: Div66
-    description: pll_p_ck = vco_ck / 66
-    value: 65
-  - name: Div68
-    description: pll_p_ck = vco_ck / 68
-    value: 67
-  - name: Div70
-    description: pll_p_ck = vco_ck / 70
-    value: 69
-  - name: Div72
-    description: pll_p_ck = vco_ck / 72
-    value: 71
-  - name: Div74
-    description: pll_p_ck = vco_ck / 74
-    value: 73
-  - name: Div76
-    description: pll_p_ck = vco_ck / 76
-    value: 75
-  - name: Div78
-    description: pll_p_ck = vco_ck / 78
-    value: 77
-  - name: Div80
-    description: pll_p_ck = vco_ck / 80
-    value: 79
-  - name: Div82
-    description: pll_p_ck = vco_ck / 82
-    value: 81
-  - name: Div84
-    description: pll_p_ck = vco_ck / 84
-    value: 83
-  - name: Div86
-    description: pll_p_ck = vco_ck / 86
-    value: 85
-  - name: Div88
-    description: pll_p_ck = vco_ck / 88
-    value: 87
-  - name: Div90
-    description: pll_p_ck = vco_ck / 90
-    value: 89
-  - name: Div92
-    description: pll_p_ck = vco_ck / 92
-    value: 91
-  - name: Div94
-    description: pll_p_ck = vco_ck / 94
-    value: 93
-  - name: Div96
-    description: pll_p_ck = vco_ck / 96
-    value: 95
-  - name: Div98
-    description: pll_p_ck = vco_ck / 98
-    value: 97
-  - name: Div100
-    description: pll_p_ck = vco_ck / 100
-    value: 99
-  - name: Div102
-    description: pll_p_ck = vco_ck / 102
-    value: 101
-  - name: Div104
-    description: pll_p_ck = vco_ck / 104
-    value: 103
-  - name: Div106
-    description: pll_p_ck = vco_ck / 106
-    value: 105
-  - name: Div108
-    description: pll_p_ck = vco_ck / 108
-    value: 107
-  - name: Div110
-    description: pll_p_ck = vco_ck / 110
-    value: 109
-  - name: Div112
-    description: pll_p_ck = vco_ck / 112
-    value: 111
-  - name: Div114
-    description: pll_p_ck = vco_ck / 114
-    value: 113
-  - name: Div116
-    description: pll_p_ck = vco_ck / 116
-    value: 115
-  - name: Div118
-    description: pll_p_ck = vco_ck / 118
-    value: 117
-  - name: Div120
-    description: pll_p_ck = vco_ck / 120
-    value: 119
-  - name: Div122
-    description: pll_p_ck = vco_ck / 122
-    value: 121
-  - name: Div124
-    description: pll_p_ck = vco_ck / 124
-    value: 123
-  - name: Div126
-    description: pll_p_ck = vco_ck / 126
-    value: 125
-  - name: Div128
-    description: pll_p_ck = vco_ck / 128
-    value: 127
-enum/DPPRE:
-  bit_size: 3
-  variants:
-  - name: Div1
-    description: rcc_hclk not divided
-    value: 0
-  - name: Div2
-    description: rcc_hclk divided by 2
-    value: 4
-  - name: Div4
-    description: rcc_hclk divided by 4
-    value: 5
-  - name: Div8
-    description: rcc_hclk divided by 8
-    value: 6
-  - name: Div16
-    description: rcc_hclk divided by 16
-    value: 7
 enum/FDCANSEL:
   bit_size: 2
   variants:
@@ -4070,6 +3801,24 @@ enum/PLLVCOSEL:
   - name: MediumVCO
     description: VCO frequency range 150 to 420 MHz
     value: 1
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: rcc_hclk not divided
+    value: 0
+  - name: Div2
+    description: rcc_hclk divided by 2
+    value: 4
+  - name: Div4
+    description: rcc_hclk divided by 4
+    value: 5
+  - name: Div8
+    description: rcc_hclk divided by 8
+    value: 6
+  - name: Div16
+    description: rcc_hclk divided by 16
+    value: 7
 enum/RNGSEL:
   bit_size: 2
   variants:
@@ -4235,21 +3984,6 @@ enum/SWPSEL:
   - name: HSI_KER
     description: hsi_ker selected as peripheral clock
     value: 1
-enum/SWS:
-  bit_size: 3
-  variants:
-  - name: HSI
-    description: HSI oscillator used as system clock
-    value: 0
-  - name: CSI
-    description: CSI oscillator used as system clock
-    value: 1
-  - name: HSE
-    description: HSE oscillator used as system clock
-    value: 2
-  - name: PLL1
-    description: PLL1 used as system clock
-    value: 3
 enum/TIMPRE:
   bit_size: 1
   variants:

data/registers/rcc_h7ab.yaml

@@ -48,14 +48,14 @@ block/RCC:
       len: 3
       stride: 8
     byte_offset: 48
-    fieldset: PLL1DIVR
+    fieldset: PLLDIVR
   - name: PLLFRACR
     description: RCC PLL1 Fractional Divider Register
     array:
       len: 3
       stride: 8
     byte_offset: 52
-    fieldset: PLL1FRACR
+    fieldset: PLLFRACR
   - name: D1CCIPR
     description: RCC Domain 1 Kernel Clock Configuration Register
     byte_offset: 76
@@ -1727,7 +1727,7 @@ fieldset/CFGR:
     description: System clock switch status
     bit_offset: 3
     bit_size: 3
-    enum: SWS
+    enum: SW
   - name: STOPWUCK
     description: System clock selection after a wake up from system Stop
     bit_offset: 6
@@ -2042,7 +2042,7 @@ fieldset/D1CFGR:
     description: D1 domain APB3 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D1CPRE
     description: D1 domain Core prescaler
     bit_offset: 8
@@ -2141,12 +2141,12 @@ fieldset/D2CFGR:
     description: D2 domain APB1 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
   - name: D2PPRE2
     description: D2 domain APB2 prescaler
     bit_offset: 8
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/D3AMR:
   description: RCC D3 Autonomous mode Register
   fields:
@@ -2270,7 +2270,7 @@ fieldset/D3CFGR:
     description: D3 domain APB4 prescaler
     bit_offset: 4
     bit_size: 3
-    enum: DPPRE
+    enum: PPRE
 fieldset/GCR:
   description: Global Control Register
   fields:
@@ -2289,85 +2289,6 @@ fieldset/HSICFGR:
     description: HSI clock trimming
     bit_offset: 24
     bit_size: 7
-fieldset/PLL1DIVR:
-  description: RCC PLL1 Dividers Configuration Register
-  fields:
-  - name: DIVN1
-    description: Multiplication factor for PLL1 VCO
-    bit_offset: 0
-    bit_size: 9
-  - name: DIVP1
-    description: PLL1 DIVP division factor
-    bit_offset: 9
-    bit_size: 7
-    enum: DIVP
-  - name: DIVQ1
-    description: PLL1 DIVQ division factor
-    bit_offset: 16
-    bit_size: 7
-  - name: DIVR1
-    description: PLL1 DIVR division factor
-    bit_offset: 24
-    bit_size: 7
-fieldset/PLL1FRACR:
-  description: RCC PLL1 Fractional Divider Register
-  fields:
-  - name: FRACN1
-    description: Fractional part of the multiplication factor for PLL1 VCO
-    bit_offset: 3
-    bit_size: 13
-fieldset/PLL2DIVR:
-  description: RCC PLL2 Dividers Configuration Register
-  fields:
-  - name: DIVN2
-    description: Multiplication factor for PLL1 VCO
-    bit_offset: 0
-    bit_size: 9
-  - name: DIVP2
-    description: PLL1 DIVP division factor
-    bit_offset: 9
-    bit_size: 7
-  - name: DIVQ2
-    description: PLL1 DIVQ division factor
-    bit_offset: 16
-    bit_size: 7
-  - name: DIVR2
-    description: PLL1 DIVR division factor
-    bit_offset: 24
-    bit_size: 7
-fieldset/PLL2FRACR:
-  description: RCC PLL2 Fractional Divider Register
-  fields:
-  - name: FRACN2
-    description: Fractional part of the multiplication factor for PLL VCO
-    bit_offset: 3
-    bit_size: 13
-fieldset/PLL3DIVR:
-  description: RCC PLL3 Dividers Configuration Register
-  fields:
-  - name: DIVN3
-    description: Multiplication factor for PLL1 VCO
-    bit_offset: 0
-    bit_size: 9
-  - name: DIVP3
-    description: PLL DIVP division factor
-    bit_offset: 9
-    bit_size: 7
-  - name: DIVQ3
-    description: PLL DIVQ division factor
-    bit_offset: 16
-    bit_size: 7
-  - name: DIVR3
-    description: PLL DIVR division factor
-    bit_offset: 24
-    bit_size: 7
-fieldset/PLL3FRACR:
-  description: RCC PLL3 Fractional Divider Register
-  fields:
-  - name: FRACN3
-    description: Fractional part of the multiplication factor for PLL3 VCO
-    bit_offset: 3
-    bit_size: 13
 fieldset/PLLCFGR:
   description: RCC PLLs Configuration Register
   fields:
@@ -2430,6 +2351,32 @@ fieldset/PLLCKSELR:
     array:
       len: 3
       stride: 8
+fieldset/PLLDIVR:
+  description: RCC PLL1 Dividers Configuration Register
+  fields:
+  - name: PLLN
+    description: Multiplication factor for PLL1 VCO
+    bit_offset: 0
+    bit_size: 9
+  - name: PLLP
+    description: PLL DIVP division factor
+    bit_offset: 9
+    bit_size: 7
+  - name: PLLQ
+    description: PLL DIVQ division factor
+    bit_offset: 16
+    bit_size: 7
+  - name: PLLR
+    description: PLL DIVR division factor
+    bit_offset: 24
+    bit_size: 7
+fieldset/PLLFRACR:
+  description: RCC PLL Fractional Divider Register
+  fields:
+  - name: FRACN
+    description: Fractional part of the multiplication factor for PLL VCO
+    bit_offset: 3
+    bit_size: 13
 fieldset/RSR:
   description: RCC Reset Status Register
   fields:
@@ -2522,222 +2469,6 @@ enum/DFSDMSEL:
   - name: SYS
     description: System clock selected as peripheral clock
     value: 1
-enum/DIVP:
-  bit_size: 7
-  variants:
-  - name: Div1
-    description: pll_p_ck = vco_ck
-    value: 0
-  - name: Div2
-    description: pll_p_ck = vco_ck / 2
-    value: 1
-  - name: Div4
-    description: pll_p_ck = vco_ck / 4
-    value: 3
-  - name: Div6
-    description: pll_p_ck = vco_ck / 6
-    value: 5
-  - name: Div8
-    description: pll_p_ck = vco_ck / 8
-    value: 7
-  - name: Div10
-    description: pll_p_ck = vco_ck / 10
-    value: 9
-  - name: Div12
-    description: pll_p_ck = vco_ck / 12
-    value: 11
-  - name: Div14
-    description: pll_p_ck = vco_ck / 14
-    value: 13
-  - name: Div16
-    description: pll_p_ck = vco_ck / 16
-    value: 15
-  - name: Div18
-    description: pll_p_ck = vco_ck / 18
-    value: 17
-  - name: Div20
-    description: pll_p_ck = vco_ck / 20
-    value: 19
-  - name: Div22
-    description: pll_p_ck = vco_ck / 22
-    value: 21
-  - name: Div24
-    description: pll_p_ck = vco_ck / 24
-    value: 23
-  - name: Div26
-    description: pll_p_ck = vco_ck / 26
-    value: 25
-  - name: Div28
-    description: pll_p_ck = vco_ck / 28
-    value: 27
-  - name: Div30
-    description: pll_p_ck = vco_ck / 30
-    value: 29
-  - name: Div32
-    description: pll_p_ck = vco_ck / 32
-    value: 31
-  - name: Div34
-    description: pll_p_ck = vco_ck / 34
-    value: 33
-  - name: Div36
-    description: pll_p_ck = vco_ck / 36
-    value: 35
-  - name: Div38
-    description: pll_p_ck = vco_ck / 38
-    value: 37
-  - name: Div40
-    description: pll_p_ck = vco_ck / 40
-    value: 39
-  - name: Div42
-    description: pll_p_ck = vco_ck / 42
-    value: 41
-  - name: Div44
-    description: pll_p_ck = vco_ck / 44
-    value: 43
-  - name: Div46
-    description: pll_p_ck = vco_ck / 46
-    value: 45
-  - name: Div48
-    description: pll_p_ck = vco_ck / 48
-    value: 47
-  - name: Div50
-    description: pll_p_ck = vco_ck / 50
-    value: 49
-  - name: Div52
-    description: pll_p_ck = vco_ck / 52
-    value: 51
-  - name: Div54
-    description: pll_p_ck = vco_ck / 54
-    value: 53
-  - name: Div56
-    description: pll_p_ck = vco_ck / 56
-    value: 55
-  - name: Div58
-    description: pll_p_ck = vco_ck / 58
-    value: 57
-  - name: Div60
-    description: pll_p_ck = vco_ck / 60
-    value: 59
-  - name: Div62
-    description: pll_p_ck = vco_ck / 62
-    value: 61
-  - name: Div64
-    description: pll_p_ck = vco_ck / 64
-    value: 63
-  - name: Div66
-    description: pll_p_ck = vco_ck / 66
-    value: 65
-  - name: Div68
-    description: pll_p_ck = vco_ck / 68
-    value: 67
-  - name: Div70
-    description: pll_p_ck = vco_ck / 70
-    value: 69
-  - name: Div72
-    description: pll_p_ck = vco_ck / 72
-    value: 71
-  - name: Div74
-    description: pll_p_ck = vco_ck / 74
-    value: 73
-  - name: Div76
-    description: pll_p_ck = vco_ck / 76
-    value: 75
-  - name: Div78
-    description: pll_p_ck = vco_ck / 78
-    value: 77
-  - name: Div80
-    description: pll_p_ck = vco_ck / 80
-    value: 79
-  - name: Div82
-    description: pll_p_ck = vco_ck / 82
-    value: 81
-  - name: Div84
-    description: pll_p_ck = vco_ck / 84
-    value: 83
-  - name: Div86
-    description: pll_p_ck = vco_ck / 86
-    value: 85
-  - name: Div88
-    description: pll_p_ck = vco_ck / 88
-    value: 87
-  - name: Div90
-    description: pll_p_ck = vco_ck / 90
-    value: 89
-  - name: Div92
-    description: pll_p_ck = vco_ck / 92
-    value: 91
-  - name: Div94
-    description: pll_p_ck = vco_ck / 94
-    value: 93
-  - name: Div96
-    description: pll_p_ck = vco_ck / 96
-    value: 95
-  - name: Div98
-    description: pll_p_ck = vco_ck / 98
-    value: 97
-  - name: Div100
-    description: pll_p_ck = vco_ck / 100
-    value: 99
-  - name: Div102
-    description: pll_p_ck = vco_ck / 102
-    value: 101
-  - name: Div104
-    description: pll_p_ck = vco_ck / 104
-    value: 103
-  - name: Div106
-    description: pll_p_ck = vco_ck / 106
-    value: 105
-  - name: Div108
-    description: pll_p_ck = vco_ck / 108
-    value: 107
-  - name: Div110
-    description: pll_p_ck = vco_ck / 110
-    value: 109
-  - name: Div112
-    description: pll_p_ck = vco_ck / 112
-    value: 111
-  - name: Div114
-    description: pll_p_ck = vco_ck / 114
-    value: 113
-  - name: Div116
-    description: pll_p_ck = vco_ck / 116
-    value: 115
-  - name: Div118
-    description: pll_p_ck = vco_ck / 118
-    value: 117
-  - name: Div120
-    description: pll_p_ck = vco_ck / 120
-    value: 119
-  - name: Div122
-    description: pll_p_ck = vco_ck / 122
-    value: 121
-  - name: Div124
-    description: pll_p_ck = vco_ck / 124
-    value: 123
-  - name: Div126
-    description: pll_p_ck = vco_ck / 126
-    value: 125
-  - name: Div128
-    description: pll_p_ck = vco_ck / 128
-    value: 127
-enum/DPPRE:
-  bit_size: 3
-  variants:
-  - name: Div1
-    description: rcc_hclk not divided
-    value: 0
-  - name: Div2
-    description: rcc_hclk divided by 2
-    value: 4
-  - name: Div4
-    description: rcc_hclk divided by 4
-    value: 5
-  - name: Div8
-    description: rcc_hclk divided by 8
-    value: 6
-  - name: Div16
-    description: rcc_hclk divided by 16
-    value: 7
 enum/FDCANSEL:
   bit_size: 2
   variants:
@@ -3005,6 +2736,24 @@ enum/PLLVCOSEL:
   - name: MediumVCO
     description: VCO frequency range 150 to 420 MHz
     value: 1
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: rcc_hclk not divided
+    value: 0
+  - name: Div2
+    description: rcc_hclk divided by 2
+    value: 4
+  - name: Div4
+    description: rcc_hclk divided by 4
+    value: 5
+  - name: Div8
+    description: rcc_hclk divided by 8
+    value: 6
+  - name: Div16
+    description: rcc_hclk divided by 16
+    value: 7
 enum/RNGSEL:
   bit_size: 2
   variants:
@@ -3170,21 +2919,6 @@ enum/SWPSEL:
   - name: HSI_KER
     description: hsi_ker selected as peripheral clock
     value: 1
-enum/SWS:
-  bit_size: 3
-  variants:
-  - name: HSI
-    description: HSI oscillator used as system clock
-    value: 0
-  - name: CSI
-    description: CSI oscillator used as system clock
-    value: 1
-  - name: HSE
-    description: HSE oscillator used as system clock
-    value: 2
-  - name: PLL1
-    description: PLL1 used as system clock
-    value: 3
 enum/TIMPRE:
   bit_size: 1
   variants:

data/registers/rcc_wb.yaml

@@ -1160,14 +1160,17 @@ fieldset/CFGR:
     description: AHB prescaler
     bit_offset: 4
     bit_size: 4
+    enum: HPRE
   - name: PPRE1
     description: PB low-speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
+    enum: PPRE
   - name: PPRE2
     description: APB high-speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
+    enum: PPRE
   - name: STOPWUCK
     description: Wakeup from Stop and CSS backup clock selection
     bit_offset: 15
@@ -1636,6 +1639,69 @@ fieldset/SMPSCR:
     description: Step Down converter clock switch status
     bit_offset: 8
     bit_size: 2
+enum/HPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: DCLK not divided
+    value: 0
+  - name: Div3
+    description: hclk = SYSCLK divided by 3
+    value: 1
+  - name: Div5
+    description: hclk = SYSCLK divided by 5
+    value: 2
+  - name: Div6
+    description: hclk = SYSCLK divided by 6
+    value: 5
+  - name: Div10
+    description: hclk = SYSCLK divided by 8
+    value: 6
+  - name: Div32
+    description: hclk = SYSCLK divided by 32
+    value: 7
+  - name: Div2
+    description: hclk = SYSCLK divided by 2
+    value: 8
+  - name: Div4
+    description: hclk = SYSCLK divided by 4
+    value: 9
+  - name: Div8
+    description: hclk = SYSCLK divided by 8
+    value: 10
+  - name: Div16
+    description: hclk = SYSCLK divided by 16
+    value: 11
+  - name: Div64
+    description: hclk = SYSCLK divided by 64
+    value: 12
+  - name: Div128
+    description: hclk = SYSCLK divided by 128
+    value: 13
+  - name: Div256
+    description: hclk = SYSCLK divided by 256
+    value: 14
+  - name: Div512
+    description: hclk = SYSCLK divided by 256
+    value: 15
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: HCLK not divided
+    value: 0
+  - name: Div2
+    description: HCLK divided by 2
+    value: 4
+  - name: Div4
+    description: HCLK divided by 4
+    value: 5
+  - name: Div8
+    description: HCLK divided by 8
+    value: 6
+  - name: Div16
+    description: HCLK divided by 16
+    value: 7
 enum/RTCSEL:
   bit_size: 2
   variants:

data/registers/rcc_wl5.yaml

@@ -1079,14 +1079,17 @@ fieldset/CFGR:
     description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
     bit_offset: 4
     bit_size: 4
+    enum: HPRE
   - name: PPRE1
     description: PCLK1 low-speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
+    enum: PPRE
   - name: PPRE2
     description: PCLK2 high-speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
+    enum: PPRE
   - name: STOPWUCK
     description: Wakeup from Stop and CSS backup clock selection
     bit_offset: 15
@@ -1435,6 +1438,69 @@ enum/ADCSEL:
   - name: SYSCLK
     description: SYSCLK used as ADC clock source
     value: 3
+enum/HPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: DCLK not divided
+    value: 0
+  - name: Div3
+    description: hclk = SYSCLK divided by 3
+    value: 1
+  - name: Div5
+    description: hclk = SYSCLK divided by 5
+    value: 2
+  - name: Div6
+    description: hclk = SYSCLK divided by 6
+    value: 5
+  - name: Div10
+    description: hclk = SYSCLK divided by 8
+    value: 6
+  - name: Div32
+    description: hclk = SYSCLK divided by 32
+    value: 7
+  - name: Div2
+    description: hclk = SYSCLK divided by 2
+    value: 8
+  - name: Div4
+    description: hclk = SYSCLK divided by 4
+    value: 9
+  - name: Div8
+    description: hclk = SYSCLK divided by 8
+    value: 10
+  - name: Div16
+    description: hclk = SYSCLK divided by 16
+    value: 11
+  - name: Div64
+    description: hclk = SYSCLK divided by 64
+    value: 12
+  - name: Div128
+    description: hclk = SYSCLK divided by 128
+    value: 13
+  - name: Div256
+    description: hclk = SYSCLK divided by 256
+    value: 14
+  - name: Div512
+    description: hclk = SYSCLK divided by 256
+    value: 15
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: HCLK not divided
+    value: 0
+  - name: Div2
+    description: HCLK divided by 2
+    value: 4
+  - name: Div4
+    description: HCLK divided by 4
+    value: 5
+  - name: Div8
+    description: HCLK divided by 8
+    value: 6
+  - name: Div16
+    description: HCLK divided by 16
+    value: 7
 enum/RTCSEL:
   bit_size: 2
   variants:

data/registers/rcc_wle.yaml

@@ -709,14 +709,17 @@ fieldset/CFGR:
     description: HCLK1 prescaler (CPU1, AHB1, AHB2, and SRAM1.)
     bit_offset: 4
     bit_size: 4
+    enum: HPRE
   - name: PPRE1
     description: PCLK1 low-speed prescaler (APB1)
     bit_offset: 8
     bit_size: 3
+    enum: PPRE
   - name: PPRE2
     description: PCLK2 high-speed prescaler (APB2)
     bit_offset: 11
     bit_size: 3
+    enum: PPRE
   - name: STOPWUCK
     description: Wakeup from Stop and CSS backup clock selection
     bit_offset: 15
@@ -1057,6 +1060,69 @@ enum/ADCSEL:
   - name: SYSCLK
     description: SYSCLK used as ADC clock source
     value: 3
+enum/HPRE:
+  bit_size: 4
+  variants:
+  - name: Div1
+    description: DCLK not divided
+    value: 0
+  - name: Div3
+    description: hclk = SYSCLK divided by 3
+    value: 1
+  - name: Div5
+    description: hclk = SYSCLK divided by 5
+    value: 2
+  - name: Div6
+    description: hclk = SYSCLK divided by 6
+    value: 5
+  - name: Div10
+    description: hclk = SYSCLK divided by 8
+    value: 6
+  - name: Div32
+    description: hclk = SYSCLK divided by 32
+    value: 7
+  - name: Div2
+    description: hclk = SYSCLK divided by 2
+    value: 8
+  - name: Div4
+    description: hclk = SYSCLK divided by 4
+    value: 9
+  - name: Div8
+    description: hclk = SYSCLK divided by 8
+    value: 10
+  - name: Div16
+    description: hclk = SYSCLK divided by 16
+    value: 11
+  - name: Div64
+    description: hclk = SYSCLK divided by 64
+    value: 12
+  - name: Div128
+    description: hclk = SYSCLK divided by 128
+    value: 13
+  - name: Div256
+    description: hclk = SYSCLK divided by 256
+    value: 14
+  - name: Div512
+    description: hclk = SYSCLK divided by 256
+    value: 15
+enum/PPRE:
+  bit_size: 3
+  variants:
+  - name: Div1
+    description: HCLK not divided
+    value: 0
+  - name: Div2
+    description: HCLK divided by 2
+    value: 4
+  - name: Div4
+    description: HCLK divided by 4
+    value: 5
+  - name: Div8
+    description: HCLK divided by 8
+    value: 6
+  - name: Div16
+    description: HCLK divided by 16
+    value: 7
 enum/RTCSEL:
   bit_size: 2
   variants:

data/registers/syscfg_h7.yaml

@@ -25,10 +25,6 @@ block/SYSCFG:
     description: SYSCFG compensation cell code register
     byte_offset: 40
     fieldset: CCCR
-  - name: PWRCR
-    description: SYSCFG power control register
-    byte_offset: 44
-    fieldset: PWRCR
   - name: PKGR
     description: SYSCFG package register
     byte_offset: 292
@@ -237,13 +233,6 @@ fieldset/PMCR:
     description: PC3 Switch Open
     bit_offset: 27
     bit_size: 1
-fieldset/PWRCR:
-  description: SYSCFG power control register
-  fields:
-  - name: ODEN
-    description: Overdrive enable
-    bit_offset: 0
-    bit_size: 4
 fieldset/UR0:
   description: SYSCFG user register 0
   fields:

data/registers/syscfg_h7od.yaml

@@ -0,0 +1,409 @@
+block/SYSCFG:
+  description: System configuration controller
+  items:
+  - name: PMCR
+    description: peripheral mode configuration register
+    byte_offset: 4
+    fieldset: PMCR
+  - name: EXTICR
+    description: external interrupt configuration register
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 8
+    fieldset: EXTICR
+  - name: CCCSR
+    description: compensation cell control/status register
+    byte_offset: 32
+    fieldset: CCCSR
+  - name: CCVR
+    description: SYSCFG compensation cell value register
+    byte_offset: 36
+    access: Read
+    fieldset: CCVR
+  - name: CCCR
+    description: SYSCFG compensation cell code register
+    byte_offset: 40
+    fieldset: CCCR
+  - name: PWRCR
+    description: SYSCFG power control register
+    byte_offset: 44
+    fieldset: PWRCR
+  - name: PKGR
+    description: SYSCFG package register
+    byte_offset: 292
+    access: Read
+    fieldset: PKGR
+  - name: UR0
+    description: SYSCFG user register 0
+    byte_offset: 768
+    access: Read
+    fieldset: UR0
+  - name: UR2
+    description: SYSCFG user register 2
+    byte_offset: 776
+    fieldset: UR2
+  - name: UR3
+    description: SYSCFG user register 3
+    byte_offset: 780
+    fieldset: UR3
+  - name: UR4
+    description: SYSCFG user register 4
+    byte_offset: 784
+    access: Read
+    fieldset: UR4
+  - name: UR5
+    description: SYSCFG user register 5
+    byte_offset: 788
+    access: Read
+    fieldset: UR5
+  - name: UR6
+    description: SYSCFG user register 6
+    byte_offset: 792
+    access: Read
+    fieldset: UR6
+  - name: UR7
+    description: SYSCFG user register 7
+    byte_offset: 796
+    access: Read
+    fieldset: UR7
+  - name: UR8
+    description: SYSCFG user register 8
+    byte_offset: 800
+    access: Read
+    fieldset: UR8
+  - name: UR9
+    description: SYSCFG user register 9
+    byte_offset: 804
+    access: Read
+    fieldset: UR9
+  - name: UR10
+    description: SYSCFG user register 10
+    byte_offset: 808
+    access: Read
+    fieldset: UR10
+  - name: UR11
+    description: SYSCFG user register 11
+    byte_offset: 812
+    access: Read
+    fieldset: UR11
+  - name: UR12
+    description: SYSCFG user register 12
+    byte_offset: 816
+    access: Read
+    fieldset: UR12
+  - name: UR13
+    description: SYSCFG user register 13
+    byte_offset: 820
+    access: Read
+    fieldset: UR13
+  - name: UR14
+    description: SYSCFG user register 14
+    byte_offset: 824
+    fieldset: UR14
+  - name: UR15
+    description: SYSCFG user register 15
+    byte_offset: 828
+    access: Read
+    fieldset: UR15
+  - name: UR16
+    description: SYSCFG user register 16
+    byte_offset: 832
+    access: Read
+    fieldset: UR16
+  - name: UR17
+    description: SYSCFG user register 17
+    byte_offset: 836
+    access: Read
+    fieldset: UR17
+fieldset/CCCR:
+  description: SYSCFG compensation cell code register
+  fields:
+  - name: NCC
+    description: NMOS compensation code
+    bit_offset: 0
+    bit_size: 4
+  - name: PCC
+    description: PMOS compensation code
+    bit_offset: 4
+    bit_size: 4
+fieldset/CCCSR:
+  description: compensation cell control/status register
+  fields:
+  - name: EN
+    description: enable
+    bit_offset: 0
+    bit_size: 1
+  - name: CS
+    description: Code selection
+    bit_offset: 1
+    bit_size: 1
+  - name: READY
+    description: Compensation cell ready flag
+    bit_offset: 8
+    bit_size: 1
+  - name: HSLV
+    description: High-speed at low-voltage
+    bit_offset: 16
+    bit_size: 1
+fieldset/CCVR:
+  description: SYSCFG compensation cell value register
+  fields:
+  - name: NCV
+    description: NMOS compensation value
+    bit_offset: 0
+    bit_size: 4
+  - name: PCV
+    description: PMOS compensation value
+    bit_offset: 4
+    bit_size: 4
+fieldset/EXTICR:
+  description: external interrupt configuration register 2
+  fields:
+  - name: EXTI
+    description: EXTI x configuration (x = 4 to 7)
+    bit_offset: 0
+    bit_size: 4
+    array:
+      len: 4
+      stride: 4
+fieldset/PKGR:
+  description: SYSCFG package register
+  fields:
+  - name: PKG
+    description: Package
+    bit_offset: 0
+    bit_size: 4
+fieldset/PMCR:
+  description: peripheral mode configuration register
+  fields:
+  - name: I2C1FMP
+    description: I2C1 Fm+
+    bit_offset: 0
+    bit_size: 1
+  - name: I2C2FMP
+    description: I2C2 Fm+
+    bit_offset: 1
+    bit_size: 1
+  - name: I2C3FMP
+    description: I2C3 Fm+
+    bit_offset: 2
+    bit_size: 1
+  - name: I2C4FMP
+    description: I2C4 Fm+
+    bit_offset: 3
+    bit_size: 1
+  - name: PB6FMP
+    description: PB(6) Fm+
+    bit_offset: 4
+    bit_size: 1
+  - name: PB7FMP
+    description: PB(7) Fast Mode Plus
+    bit_offset: 5
+    bit_size: 1
+  - name: PB8FMP
+    description: PB(8) Fast Mode Plus
+    bit_offset: 6
+    bit_size: 1
+  - name: PB9FMP
+    description: PB(9) Fm+
+    bit_offset: 7
+    bit_size: 1
+  - name: BOOSTE
+    description: Booster Enable
+    bit_offset: 8
+    bit_size: 1
+  - name: BOOSTVDDSEL
+    description: Analog switch supply voltage selection
+    bit_offset: 9
+    bit_size: 1
+  - name: EPIS
+    description: Ethernet PHY Interface Selection
+    bit_offset: 21
+    bit_size: 3
+  - name: PA0SO
+    description: PA0 Switch Open
+    bit_offset: 24
+    bit_size: 1
+  - name: PA1SO
+    description: PA1 Switch Open
+    bit_offset: 25
+    bit_size: 1
+  - name: PC2SO
+    description: PC2 Switch Open
+    bit_offset: 26
+    bit_size: 1
+  - name: PC3SO
+    description: PC3 Switch Open
+    bit_offset: 27
+    bit_size: 1
+fieldset/PWRCR:
+  description: SYSCFG power control register
+  fields:
+  - name: ODEN
+    description: Overdrive enable
+    bit_offset: 0
+    bit_size: 4
+fieldset/UR0:
+  description: SYSCFG user register 0
+  fields:
+  - name: BKS
+    description: Bank Swap
+    bit_offset: 0
+    bit_size: 1
+  - name: RDP
+    description: Readout protection
+    bit_offset: 16
+    bit_size: 8
+fieldset/UR10:
+  description: SYSCFG user register 10
+  fields:
+  - name: PA_END_2
+    description: Protected area end address for bank 2
+    bit_offset: 0
+    bit_size: 12
+  - name: SA_BEG_2
+    description: Secured area start address for bank 2
+    bit_offset: 16
+    bit_size: 12
+fieldset/UR11:
+  description: SYSCFG user register 11
+  fields:
+  - name: SA_END_2
+    description: Secured area end address for bank 2
+    bit_offset: 0
+    bit_size: 12
+  - name: IWDG1M
+    description: Independent Watchdog 1 mode
+    bit_offset: 16
+    bit_size: 1
+fieldset/UR12:
+  description: SYSCFG user register 12
+  fields:
+  - name: SECURE
+    description: Secure mode
+    bit_offset: 16
+    bit_size: 1
+fieldset/UR13:
+  description: SYSCFG user register 13
+  fields:
+  - name: SDRS
+    description: Secured DTCM RAM Size
+    bit_offset: 0
+    bit_size: 2
+  - name: D1SBRST
+    description: D1 Standby reset
+    bit_offset: 16
+    bit_size: 1
+fieldset/UR14:
+  description: SYSCFG user register 14
+  fields:
+  - name: D1STPRST
+    description: D1 Stop Reset
+    bit_offset: 0
+    bit_size: 1
+fieldset/UR15:
+  description: SYSCFG user register 15
+  fields:
+  - name: FZIWDGSTB
+    description: Freeze independent watchdog in Standby mode
+    bit_offset: 16
+    bit_size: 1
+fieldset/UR16:
+  description: SYSCFG user register 16
+  fields:
+  - name: FZIWDGSTP
+    description: Freeze independent watchdog in Stop mode
+    bit_offset: 0
+    bit_size: 1
+  - name: PKP
+    description: Private key programmed
+    bit_offset: 16
+    bit_size: 1
+fieldset/UR17:
+  description: SYSCFG user register 17
+  fields:
+  - name: IO_HSLV
+    description: I/O high speed / low voltage
+    bit_offset: 0
+    bit_size: 1
+fieldset/UR2:
+  description: SYSCFG user register 2
+  fields:
+  - name: BORH
+    description: BOR_LVL Brownout Reset Threshold Level
+    bit_offset: 0
+    bit_size: 2
+  - name: BOOT_ADD0
+    description: Boot Address 0
+    bit_offset: 16
+    bit_size: 16
+fieldset/UR3:
+  description: SYSCFG user register 3
+  fields:
+  - name: BOOT_ADD1
+    description: Boot Address 1
+    bit_offset: 16
+    bit_size: 16
+fieldset/UR4:
+  description: SYSCFG user register 4
+  fields:
+  - name: MEPAD_1
+    description: Mass Erase Protected Area Disabled for bank 1
+    bit_offset: 16
+    bit_size: 1
+fieldset/UR5:
+  description: SYSCFG user register 5
+  fields:
+  - name: MESAD_1
+    description: Mass erase secured area disabled for bank 1
+    bit_offset: 0
+    bit_size: 1
+  - name: WRPN_1
+    description: Write protection for flash bank 1
+    bit_offset: 16
+    bit_size: 8
+fieldset/UR6:
+  description: SYSCFG user register 6
+  fields:
+  - name: PA_BEG_1
+    description: Protected area start address for bank 1
+    bit_offset: 0
+    bit_size: 12
+  - name: PA_END_1
+    description: Protected area end address for bank 1
+    bit_offset: 16
+    bit_size: 12
+fieldset/UR7:
+  description: SYSCFG user register 7
+  fields:
+  - name: SA_BEG_1
+    description: Secured area start address for bank 1
+    bit_offset: 0
+    bit_size: 12
+  - name: SA_END_1
+    description: Secured area end address for bank 1
+    bit_offset: 16
+    bit_size: 12
+fieldset/UR8:
+  description: SYSCFG user register 8
+  fields:
+  - name: MEPAD_2
+    description: Mass erase protected area disabled for bank 2
+    bit_offset: 0
+    bit_size: 1
+  - name: MESAD_2
+    description: Mass erase secured area disabled for bank 2
+    bit_offset: 16
+    bit_size: 1
+fieldset/UR9:
+  description: SYSCFG user register 9
+  fields:
+  - name: WRPN_2
+    description: Write protection for flash bank 2
+    bit_offset: 0
+    bit_size: 8
+  - name: PA_BEG_2
+    description: Protected area start address for bank 2
+    bit_offset: 16
+    bit_size: 12

stm32-data-gen/src/chips.rs

@@ -214,6 +214,10 @@ impl PeriMatcher {
             ("STM32L5.*:SYSCFG:.*", ("syscfg", "l5", "SYSCFG")),
             ("STM32G0.*:SYSCFG:.*", ("syscfg", "g0", "SYSCFG")),
             ("STM32G4.*:SYSCFG:.*", ("syscfg", "g4", "SYSCFG")),
+            (
+                "STM32H7(45|47|55|57|42|43|53|50).*:SYSCFG:.*",
+                ("syscfg", "h7od", "SYSCFG"),
+            ),
             ("STM32H7.*:SYSCFG:.*", ("syscfg", "h7", "SYSCFG")),
             ("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")),
             ("STM32WBA.*:SYSCFG:.*", ("syscfg", "wba", "SYSCFG")),
@@ -328,8 +332,13 @@ impl PeriMatcher {
             ("STM32C0.*:PWR:.*", ("pwr", "c0", "PWR")),
             ("STM32G0.*:PWR:.*", ("pwr", "g0", "PWR")),
             ("STM32G4.*:PWR:.*", ("pwr", "g4", "PWR")),
-            ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7", "PWR")),
+            ("STM32H7(45|47|55|57).*:PWR:.*", ("pwr", "h7rm0399", "PWR")),
-            ("STM32H7.*:PWR:.*", ("pwr", "h7smps", "PWR")),
+            ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7rm0433", "PWR")),
+            ("STM32H7(23|25|33|35|30).*:PWR:.*", ("pwr", "h7rm0468", "PWR")),
+            ("STM32H7(A3|B0|B3).*:PWR:.*", ("pwr", "h7rm0455", "PWR")),
+            ("STM32F0.0.*:PWR:.*", ("pwr", "f0x0", "PWR")),
+            ("STM32F0.*:PWR:.*", ("pwr", "f0", "PWR")),
+            ("STM32F1.*:PWR:.*", ("pwr", "f1", "PWR")),
             ("STM32F2.*:PWR:.*", ("pwr", "f2", "PWR")),
             ("STM32F3.*:PWR:.*", ("pwr", "f3", "PWR")),
             ("STM32F4.*:PWR:.*", ("pwr", "f4", "PWR")),
@@ -341,7 +350,8 @@ impl PeriMatcher {
             ("STM32U5.*:PWR:.*", ("pwr", "u5", "PWR")),
             ("STM32WL.*:PWR:.*", ("pwr", "wl5", "PWR")),
             ("STM32WBA.*:PWR:.*", ("pwr", "wba", "PWR")),
-            ("STM32WB.*:PWR:.*", ("pwr", "wb55", "PWR")),
+            ("STM32WB55.*:PWR:.*", ("pwr", "wb55", "PWR")),
+            ("STM32WB.*:PWR:.*", ("pwr", "wb", "PWR")),
             ("STM32H50.*:PWR:.*", ("pwr", "h50", "PWR")),
             ("STM32H5.*:PWR:.*", ("pwr", "h5", "PWR")),
             ("STM32H7(A3|B3|B0).*:FLASH:.*", ("flash", "h7ab", "FLASH")),

stm32-metapac-gen/res/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "stm32-metapac"
-version = "13.0.0"
+version = "14.0.0"
 edition = "2021"
 license = "MIT OR Apache-2.0"
 repository = "https://github.com/embassy-rs/stm32-data"

stm32-metapac-gen/res/build.rs

@@ -13,6 +13,7 @@ fn main() {
         .to_ascii_lowercase()
         .replace('_', "-");
 
+    #[cfg(feature = "rt")]
     println!(
         "cargo:rustc-link-search={}/src/chips/{}",
         crate_dir.display(),