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fdcan: arraify

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xoviat 2023-07-04 13:20:24 -05:00
parent 1e9103cd22
commit b91dd597d3
1 changed files with 71 additions and 105 deletions
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176
data/registers/can_fdcan.yaml
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@ -90,23 +90,23 @@ block/FDCAN:
byte_offset: 136 byte_offset: 136
access: Read access: Read
fieldset: HPMS fieldset: HPMS
- name: RXF0S - name: RXFS
description: FDCAN Rx FIFO 0 Status Register description: FDCAN Rx FIFO X Status Register
byte_offset: 144 byte_offset: 144
fieldset: RXF0S fieldset: RXFS
- name: RXF0A access: Read
array:
offsets:
- 0
- 8
- name: RXFA
description: CAN Rx FIFO 0 Acknowledge Register description: CAN Rx FIFO 0 Acknowledge Register
byte_offset: 148 byte_offset: 148
fieldset: RXF0A fieldset: RXFA
- name: RXF1S array:
description: FDCAN Rx FIFO 1 Status Register offsets:
byte_offset: 152 - 0
access: Read - 8
fieldset: RXF1S
- name: RXF1A
description: FDCAN Rx FIFO 1 Acknowledge Register
byte_offset: 156
fieldset: RXF1A
- name: TXBC - name: TXBC
description: FDCAN Tx Buffer Configuration Register description: FDCAN Tx Buffer Configuration Register
byte_offset: 192 byte_offset: 192
@ -324,30 +324,31 @@ fieldset/HPMS:
fieldset/IE: fieldset/IE:
description: The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line. description: The settings in the Interrupt Enable register determine which status changes in the Interrupt Register will be signaled on an interrupt line.
fields: fields:
- name: RF0NE - name: RFNE
description: Rx FIFO 0 new message enable description: Rx FIFO X new message enable
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RF0FE array:
description: Rx FIFO 0 full enable offsets:
- 0
- 3
- name: RFFE
description: Rx FIFO X full enable
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: RF0LE array:
description: Rx FIFO 0 message lost enable offsets:
- 0
- 3
- name: RFLE
description: Rx FIFO X message lost enable
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: RF1NE array:
description: Rx FIFO 1 new message enable offsets:
bit_offset: 3 - 0
bit_size: 1 - 3
- name: RF1FE
description: Rx FIFO 1 full enable
bit_offset: 4
bit_size: 1
- name: RF1LE
description: Rx FIFO 1 message lost enable
bit_offset: 5
bit_size: 1
- name: HPME - name: HPME
description: High-priority message enable description: High-priority message enable
bit_offset: 6 bit_offset: 6
@ -434,14 +435,13 @@ fieldset/ILE:
fieldset/ILS: fieldset/ILS:
description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]." description: "The Interrupt Line Select register assigns an interrupt generated by a specific interrupt flag from the Interrupt Register to one of the two module interrupt lines. For interrupt generation the respective interrupt line has to be enabled via ILE[EINT0] and ILE[EINT1]."
fields: fields:
- name: RXFIFO0 - name: RXFIFO
description: RX FIFO bit grouping the following interruption description: RX FIFO bit grouping the following interruption
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RXFIFO1 array:
description: RX FIFO bit grouping the following interruption len: 2
bit_offset: 1 stride: 1
bit_size: 1
- name: SMSG - name: SMSG
description: Status message bit grouping the following interruption description: Status message bit grouping the following interruption
bit_offset: 2 bit_offset: 2
@ -465,30 +465,30 @@ fieldset/ILS:
fieldset/IR: fieldset/IR:
description: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled. description: The flags are set when one of the listed conditions is detected (edge-sensitive). The flags remain set until the Host clears them. A flag is cleared by writing a 1 to the corresponding bit position. Writing a 0 has no effect. A hard reset will clear the register. The configuration of IE controls whether an interrupt is generated. The configuration of ILS controls on which interrupt line an interrupt is signaled.
fields: fields:
- name: RF0N - name: RFN
description: Rx FIFO 0 new message description: Rx FIFO X new message
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
- name: RF0F array:
description: Rx FIFO 0 full offsets:
- 0
- 3
- name: RFF
description: Rx FIFO X full
bit_offset: 1 bit_offset: 1
bit_size: 1 bit_size: 1
- name: RF0L array:
description: Rx FIFO 0 message lost offsets:
- 0
- 3
- name: RFL
description: Rx FIFO X message lost
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
- name: RF1N array:
description: Rx FIFO 1 new message offsets:
bit_offset: 3 - 0
bit_size: 1 - 3
- name: RF1F
description: Rx FIFO 1 full
bit_offset: 4
bit_size: 1
- name: RF1L
description: Rx FIFO 1 message lost
bit_offset: 5
bit_size: 1
- name: HPM - name: HPM
description: High-priority message description: High-priority message
bit_offset: 6 bit_offset: 6
@ -638,70 +638,36 @@ fieldset/RWD:
description: WDV description: WDV
bit_offset: 8 bit_offset: 8
bit_size: 8 bit_size: 8
fieldset/RXF0A: fieldset/RXFA:
description: CAN Rx FIFO 0 Acknowledge Register description: CAN Rx FIFO X Acknowledge Register
fields: fields:
- name: F0AI - name: FAI
description: F0AI description: FAI
bit_offset: 0 bit_offset: 0
bit_size: 6 bit_size: 6
fieldset/RXF0S: fieldset/RXFS:
description: FDCAN Rx FIFO 0 Status Register description: FDCAN Rx FIFO X Status Register
fields: fields:
- name: F0FL - name: FFL
description: F0FL description: FFL
bit_offset: 0 bit_offset: 0
bit_size: 7 bit_size: 7
- name: F0GI - name: FGI
description: F0GI description: FGI
bit_offset: 8 bit_offset: 8
bit_size: 6 bit_size: 6
- name: F0PI - name: FPI
description: F0PI description: FPI
bit_offset: 16 bit_offset: 16
bit_size: 6 bit_size: 6
- name: F0F - name: FF
description: F0F description: FF
bit_offset: 24 bit_offset: 24
bit_size: 1 bit_size: 1
- name: RF0L - name: RFL
description: RF0L description: RFL
bit_offset: 25 bit_offset: 25
bit_size: 1 bit_size: 1
fieldset/RXF1A:
description: FDCAN Rx FIFO 1 Acknowledge Register
fields:
- name: F1AI
description: F1AI
bit_offset: 0
bit_size: 6
fieldset/RXF1S:
description: FDCAN Rx FIFO 1 Status Register
fields:
- name: F1FL
description: F1FL
bit_offset: 0
bit_size: 7
- name: F1GI
description: F1GI
bit_offset: 8
bit_size: 6
- name: F1PI
description: F1PI
bit_offset: 16
bit_size: 6
- name: F1F
description: F1F
bit_offset: 24
bit_size: 1
- name: RF1L
description: RF1L
bit_offset: 25
bit_size: 1
- name: DMS
description: DMS
bit_offset: 30
bit_size: 2
fieldset/RXGFC: fieldset/RXGFC:
description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path." description: "Global settings for Message ID filtering. The Global Filter Configuration controls the filter path for standard and extended messages as described in Figure706: Standard Message ID filter path and Figure707: Extended Message ID filter path."
fields: fields: