tailoring timer_v1 from timer_v2
This commit is contained in:
eZio Pan
parent
81d09e5782
commit
abb0f63c4a
@ -45,30 +45,19 @@ block/TIM_1CH:
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byte_offset: 40
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fieldset: PSC_BASIC
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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description: auto-reload register
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byte_offset: 44
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fieldset: ARR_BASIC
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_BASIC
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- name: CCR
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description: capture/compare register x (x=1) (Dither mode disabled)
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description: capture/compare register x (x=1)
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array:
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len: 1
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stride: 4
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byte_offset: 52
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fieldset: CCR_GP16
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- name: CCR_DITHER
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description: capture/compare register x (x=1) (Dither mode enabled)
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array:
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len: 1
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_GP16
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- name: TISEL
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description: input selection register
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byte_offset: 92
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byte_offset: 104
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fieldset: TISEL_1CH
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block/TIM_1CH_CMP:
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extends: TIM_1CH
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@ -103,6 +92,14 @@ block/TIM_1CH_CMP:
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description: break and dead-time register
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byte_offset: 68
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fieldset: BDTR_1CH_CMP
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- name: DCR
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description: DMA control register
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byte_offset: 72
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fieldset: DCR_1CH_CMP
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 76
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fieldset: DMAR_GP16
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- name: DTR2
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description: break and dead-time register
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byte_offset: 84
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@ -111,18 +108,6 @@ block/TIM_1CH_CMP:
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description: alternate function register 1
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byte_offset: 96
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fieldset: AF1_1CH_CMP
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- name: AF2
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_GP16
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- name: DCR
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description: DMA control register
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byte_offset: 988
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fieldset: DCR_GP16
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 992
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fieldset: DMAR_GP16
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block/TIM_2CH:
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extends: TIM_1CH
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description: 2-channel timers
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@ -167,22 +152,15 @@ block/TIM_2CH:
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byte_offset: 32
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fieldset: CCER_2CH
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- name: CCR
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description: capture/compare register x (x=1-2) (Dither mode disabled)
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description: capture/compare register x (x=1-2)
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array:
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len: 2
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stride: 4
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byte_offset: 52
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fieldset: CCR_GP16
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- name: CCR_DITHER
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description: capture/compare register x (x=1-2) (Dither mode enabled)
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array:
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len: 2
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_GP16
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- name: TISEL
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description: input selection register
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byte_offset: 92
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byte_offset: 104
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fieldset: TISEL_2CH
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block/TIM_2CH_CMP:
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extends: TIM_2CH
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@ -195,7 +173,7 @@ block/TIM_2CH_CMP:
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- name: SMCR
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description: slave mode control register
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byte_offset: 8
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fieldset: SMCR_2CH_CMP
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fieldset: SMCR_2CH
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- name: DIER
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description: DMA/Interrupt enable register
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byte_offset: 12
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@ -221,30 +199,26 @@ block/TIM_2CH_CMP:
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description: break and dead-time register
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byte_offset: 68
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fieldset: BDTR_1CH_CMP
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- name: DCR
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description: DMA control register
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byte_offset: 72
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fieldset: DCR_1CH_CMP
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 76
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fieldset: DMAR_GP16
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- name: DTR2
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description: break and dead-time register
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byte_offset: 84
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fieldset: DTR2_ADV
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- name: TISEL
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description: input selection register
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byte_offset: 92
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fieldset: TISEL_2CH
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- name: AF1
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description: alternate function register 1
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byte_offset: 96
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fieldset: AF1_1CH_CMP
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- name: AF2
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_GP16
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- name: DCR
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description: DMA control register
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byte_offset: 988
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fieldset: DCR_GP16
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 992
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fieldset: DMAR_GP16
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- name: TISEL
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description: input selection register
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byte_offset: 104
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fieldset: TISEL_2CH
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block/TIM_ADV:
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extends: TIM_GP16
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description: Advanced Control timers
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@ -282,22 +256,10 @@ block/TIM_ADV:
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description: break and dead-time register
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byte_offset: 68
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fieldset: BDTR_ADV
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- name: CCR5
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description: capture/compare register 5 (Dither mode disabled)
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byte_offset: 72
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fieldset: CCR5_ADV
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- name: CCR5_DITHER
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description: capture/compare register 5 (Dither mode enabled)
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byte_offset: 72
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fieldset: CCR5_DITHER_ADV
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- name: CCR6
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description: capture/compare register 6 (Dither mode disabled)
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 76
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fieldset: CCR_GP16
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- name: CCR6_DITHER
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description: capture/compare register 6 (Dither mode enabled)
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byte_offset: 76
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fieldset: CCR_DITHER_GP16
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fieldset: DMAR_ADV
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- name: CCMR3
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description: capture/compare mode register 3
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byte_offset: 80
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@ -306,6 +268,14 @@ block/TIM_ADV:
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description: break and dead-time register
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byte_offset: 84
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fieldset: DTR2_ADV
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- name: CCR5
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description: capture/compare register 5
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byte_offset: 88
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fieldset: CCR5_ADV
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- name: CCR6
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description: capture/compare register 6
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byte_offset: 92
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fieldset: CCR_GP16
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- name: AF1
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description: alternate function register 1
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byte_offset: 96
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@ -347,13 +317,9 @@ block/TIM_BASIC:
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byte_offset: 40
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fieldset: PSC_BASIC
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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description: auto-reload register
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byte_offset: 44
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fieldset: ARR_BASIC
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_BASIC
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block/TIM_GP16:
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extends: TIM_BASIC
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description: General purpose 16-bit timers
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@ -402,77 +368,55 @@ block/TIM_GP16:
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byte_offset: 32
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fieldset: CCER_GP16
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- name: CCR
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description: capture/compare register x (x=1-4) (Dither mode disabled)
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description: capture/compare register x (x=1-4)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_GP16
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- name: CCR_DITHER
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description: capture/compare register x (x=1-4) (Dither mode enabled)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_GP16
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- name: DCR
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description: DMA control register
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byte_offset: 72
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fieldset: DCR_GP16
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 76
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fieldset: DMAR_GP16
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- name: ECR
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description: encoder control register
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byte_offset: 88
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fieldset: ECR_GP16
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- name: TISEL
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description: input selection register
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byte_offset: 92
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fieldset: TISEL_GP16
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- name: AF1
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description: alternate function register 1
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byte_offset: 96
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fieldset: AF1_GP16
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- name: AF2
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description: alternate function register 2
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byte_offset: 100
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fieldset: AF2_GP16
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- name: DCR
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description: DMA control register
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byte_offset: 988
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fieldset: DCR_GP16
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- name: DMAR
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description: DMA address for full transfer
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byte_offset: 992
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fieldset: DMAR_GP16
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- name: TISEL
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description: input selection register
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byte_offset: 104
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fieldset: TISEL_GP16
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block/TIM_GP32:
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extends: TIM_GP16
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description: General purpose 32-bit timers
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items:
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- name: CNT
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description: counter (Dither mode disabled)
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description: counter
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byte_offset: 36
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fieldset: CNT_GP32
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- name: CNT_DITHER
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description: counter (Dither mode enbled)
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byte_offset: 36
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fieldset: CNT_DITHER_GP32
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- name: ARR
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description: auto-reload register (Dither mode disabled)
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description: auto-reload register
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byte_offset: 44
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fieldset: ARR_GP32
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- name: ARR_DITHER
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description: auto-reload register (Dither mode enabled)
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byte_offset: 44
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fieldset: ARR_DITHER_GP32
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- name: CCR
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description: capture/compare register x (x=1-4) (Dither mode disabled)
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description: capture/compare register x (x=1-4)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_GP32
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- name: CCR_DITHER
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description: capture/compare register x (x=1-4) (Dither mode enabled)
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array:
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len: 4
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stride: 4
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byte_offset: 52
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fieldset: CCR_DITHER_GP32
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- name: DCR
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description: DMA control register
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byte_offset: 72
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fieldset: DCR_1CH_CMP
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fieldset/AF1_1CH_CMP:
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description: alternate function register 1
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fields:
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@ -481,23 +425,27 @@ fieldset/AF1_1CH_CMP:
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bit_offset: 0
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bit_size: 1
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- name: BKCMPE
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description: TIM_BRK_CMPx (x=1-8) enable
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description: TIM_BRK_CMPx (x=1-2) enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 8
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len: 2
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stride: 1
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- name: BKDF1BKE
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description: BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17)
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bit_offset: 8
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bit_size: 1
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- name: BKINP
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description: TIMx_BKIN input polarity
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bit_offset: 9
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bit_size: 1
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enum: BKINP
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- name: BKCMPP
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description: TIM_BRK_CMPx (x=1-4) input polarity
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description: TIM_BRK_CMPx (x=1-2) input polarity
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bit_offset: 10
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bit_size: 1
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array:
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len: 4
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len: 2
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stride: 1
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enum: BKINP
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fieldset/AF1_ADV:
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@ -509,23 +457,27 @@ fieldset/AF1_ADV:
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bit_offset: 0
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bit_size: 1
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- name: BKCMPE
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description: TIM_BRK_CMPx (x=1-8) enable
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description: TIM_BRK_CMPx (x=1-2) enable
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bit_offset: 1
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bit_size: 1
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array:
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len: 8
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len: 2
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stride: 1
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- name: BKDF1BK0E
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description: BRK1 DFSDM1_BREAK0 enable
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bit_offset: 8
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bit_size: 1
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- name: BKINP
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description: TIMx_BKIN input polarity
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bit_offset: 9
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bit_size: 1
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enum: BKINP
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- name: BKCMPP
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description: TIM_BRK_CMPx (x=1-4) input polarity
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description: TIM_BRK_CMPx (x=1-2) input polarity
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bit_offset: 10
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bit_size: 1
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array:
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len: 4
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len: 2
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stride: 1
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enum: BKINP
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fieldset/AF1_GP16:
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@ -550,6 +502,10 @@ fieldset/AF2_ADV:
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array:
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len: 1
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stride: 8
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- name: BK2DF1BK1E
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description: BRK2 DFSDM1_BREAK1 enable
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bit_offset: 8
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bit_size: 1
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- name: BK2INP
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description: TIMx_BK2IN input polarity
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bit_offset: 9
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@ -560,47 +516,18 @@ fieldset/AF2_ADV:
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bit_offset: 10
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bit_size: 1
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array:
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len: 1
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stride: 4
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len: 2
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stride: 1
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enum: BKINP
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fieldset/AF2_GP16:
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description: alternate function register 2
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fields:
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- name: OCRSEL
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description: ocref_clr source selection
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bit_offset: 16
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bit_size: 3
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fieldset/ARR_BASIC:
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description: auto-reload register (Dither mode disabled)
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description: auto-reload register
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fields:
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- name: ARR
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description: Auto-reload value
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bit_offset: 0
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bit_size: 16
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fieldset/ARR_DITHER_BASIC:
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description: auto-reload register (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: ARR
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description: Auto-reload value
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bit_offset: 4
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bit_size: 16
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fieldset/ARR_DITHER_GP32:
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description: auto-reload register (Dither mode enabled)
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fields:
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- name: DITHER
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description: Dither value
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bit_offset: 0
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bit_size: 4
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- name: ARR
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description: Auto-reload value
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bit_offset: 4
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bit_size: 28
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fieldset/ARR_GP32:
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description: auto-reload register (Dither mode disabled)
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description: auto-reload register
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fields:
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- name: ARR
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description: Auto-reload value
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@ -659,22 +586,6 @@ fieldset/BDTR_1CH_CMP:
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len: 1
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stride: 4
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enum: FilterValue
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- name: BKDSRM
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description: Break x (x=1) Disarm
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bit_offset: 26
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bit_size: 1
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array:
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len: 1
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stride: 1
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enum: BKDSRM
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- name: BKBID
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description: Break x (x=1) bidirectional
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bit_offset: 28
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bit_size: 1
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array:
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len: 1
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stride: 1
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enum: BKBID
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fieldset/BDTR_ADV:
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description: break and dead-time register
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fields:
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@ -834,11 +745,11 @@ fieldset/CCER_ADV:
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len: 6
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stride: 4
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- name: CCNE
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description: Capture/Compare x (x=1-4) complementary output enable
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description: Capture/Compare x (x=1-3) complementary output enable
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bit_offset: 2
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bit_size: 1
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array:
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len: 4
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len: 3
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stride: 4
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fieldset/CCER_GP16:
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description: capture/compare enable register
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@ -1084,7 +995,7 @@ fieldset/CCMR_Output_GP16:
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stride: 8
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fieldset/CCR5_ADV:
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extends: CCR_GP16
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description: capture/compare register 5 (Dither mode disabled)
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description: capture/compare register 5
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fields:
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- name: GC5C
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description: Group channel 5 and channel x (x=1-3)
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@ -1094,49 +1005,15 @@ fieldset/CCR5_ADV:
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len: 3
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stride: 1
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enum: GC5C
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fieldset/CCR5_DITHER_ADV:
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extends: CCR_DITHER_GP16
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description: capture/compare register 5 (Dither mode enabled)
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fields:
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- name: GC5C
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description: Group channel 5 and channel x (x=1-3)
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bit_offset: 29
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bit_size: 1
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array:
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len: 3
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stride: 1
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enum: GC5C
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fieldset/CCR_DITHER_GP16:
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description: capture/compare register x (x=1-4,6) (Dither mode enabled)
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fields:
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- name: DITHER
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description: capture/compare x (x=1-4,6) value
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bit_offset: 0
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bit_size: 4
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- name: CCR
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description: capture/compare x (x=1-4,6) value
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bit_offset: 4
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bit_size: 16
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fieldset/CCR_DITHER_GP32:
|
||||
description: capture/compare register x (x=1-4,6) (Dither mode enabled)
|
||||
fields:
|
||||
- name: DITHER
|
||||
description: Dither value
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
- name: CCR
|
||||
description: capture/compare x (x=1-4,6) value
|
||||
bit_offset: 4
|
||||
bit_size: 28
|
||||
fieldset/CCR_GP16:
|
||||
description: capture/compare register x (x=1-4,6) (Dither mode disabled)
|
||||
description: capture/compare register x (x=1-4,6)
|
||||
fields:
|
||||
- name: CCR
|
||||
description: capture/compare x (x=1-4,6) value
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/CCR_GP32:
|
||||
description: capture/compare register x (x=1-4,6) (Dither mode disabled)
|
||||
description: capture/compare register x (x=1-4,6)
|
||||
fields:
|
||||
- name: CCR
|
||||
description: capture/compare x (x=1-4,6) value
|
||||
@ -1153,19 +1030,8 @@ fieldset/CNT_BASIC:
|
||||
description: UIF copy
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CNT_DITHER_GP32:
|
||||
description: counter (Dither mode enabled)
|
||||
fields:
|
||||
- name: CNT
|
||||
description: counter value
|
||||
bit_offset: 0
|
||||
bit_size: 31
|
||||
- name: UIFCPY
|
||||
description: UIF copy
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CNT_GP32:
|
||||
description: counter (Dither mode disabled)
|
||||
description: counter
|
||||
fields:
|
||||
- name: CNT
|
||||
description: counter value
|
||||
@ -1204,10 +1070,6 @@ fieldset/CR1_1CH:
|
||||
description: UIF status bit remapping enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DITHEN
|
||||
description: Dithering enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CR1_BASIC:
|
||||
description: control register 1
|
||||
fields:
|
||||
@ -1236,10 +1098,6 @@ fieldset/CR1_BASIC:
|
||||
description: UIF status bit remapping enable
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DITHEN
|
||||
description: Dithering enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
fieldset/CR1_GP16:
|
||||
extends: CR1_BASIC
|
||||
description: control register 1
|
||||
@ -1386,7 +1244,7 @@ fieldset/CR2_GP16:
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: TI1S
|
||||
fieldset/DCR_GP16:
|
||||
fieldset/DCR_1CH_CMP:
|
||||
description: DMA control register
|
||||
fields:
|
||||
- name: DBA
|
||||
@ -1397,6 +1255,10 @@ fieldset/DCR_GP16:
|
||||
description: DMA burst length
|
||||
bit_offset: 8
|
||||
bit_size: 5
|
||||
fieldset/DCR_GP16:
|
||||
extends: DCR_1CH_CMP
|
||||
description: DMA control register
|
||||
fields:
|
||||
- name: DBSS
|
||||
description: DMA burst source selection
|
||||
bit_offset: 16
|
||||
@ -1523,29 +1385,20 @@ fieldset/DIER_GP16:
|
||||
description: Trigger DMA request enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: IDXIE
|
||||
description: Index interrupt enable
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DIRIE
|
||||
description: Direction change interrupt enable
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: IERRIE
|
||||
description: Index error interrupt enable
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TERRIE
|
||||
description: Transition error interrupt enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/DMAR_GP16:
|
||||
fieldset/DMAR_ADV:
|
||||
description: DMA address for full transfer
|
||||
fields:
|
||||
- name: DMAB
|
||||
description: DMA register for burst accesses
|
||||
bit_offset: 0
|
||||
bit_size: 32
|
||||
fieldset/DMAR_GP16:
|
||||
description: DMA address for full transfer
|
||||
fields:
|
||||
- name: DMAB
|
||||
description: DMA register for burst accesses
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
fieldset/DTR2_ADV:
|
||||
description: deadtime register 2
|
||||
fields:
|
||||
@ -1716,14 +1569,6 @@ fieldset/SMCR_2CH:
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum: MSM
|
||||
fieldset/SMCR_2CH_CMP:
|
||||
extends: SMCR_2CH
|
||||
description: slave mode control register
|
||||
fields:
|
||||
- name: SMSPE
|
||||
description: SMS preload enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
fieldset/SMCR_ADV:
|
||||
extends: SMCR_GP16
|
||||
description: slave mode control register
|
||||
@ -1770,15 +1615,6 @@ fieldset/SMCR_GP16:
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
enum: ETP
|
||||
- name: SMSPE
|
||||
description: SMS preload enable
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: SMSPS
|
||||
description: SMS preload source
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
enum: SMSPS
|
||||
fieldset/SR_1CH:
|
||||
description: status register
|
||||
fields:
|
||||
@ -1889,22 +1725,6 @@ fieldset/SR_GP16:
|
||||
array:
|
||||
len: 4
|
||||
stride: 1
|
||||
- name: IDXIF
|
||||
description: Index interrupt flag
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: DIRIF
|
||||
description: Direction change interrupt flag
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: IERRIF
|
||||
description: Index error interrupt flag
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TERRIF
|
||||
description: Transition error interrupt flag
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/TISEL_1CH:
|
||||
description: input selection register
|
||||
fields:
|
||||
@ -2368,15 +2188,6 @@ enum/SMS:
|
||||
- name: Ext_Clock_Mode
|
||||
description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter.
|
||||
value: 7
|
||||
enum/SMSPS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Update
|
||||
description: The transfer is triggered by the Timer’s Update event
|
||||
value: 0
|
||||
- name: Index
|
||||
description: The transfer is triggered by the Index event
|
||||
value: 1
|
||||
enum/TI1S:
|
||||
bit_size: 1
|
||||
variants:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user