diff --git a/data/registers/timer_v1.yaml b/data/registers/timer_v1.yaml index 28db16d..67b66f9 100644 --- a/data/registers/timer_v1.yaml +++ b/data/registers/timer_v1.yaml @@ -45,30 +45,19 @@ block/TIM_1CH: byte_offset: 40 fieldset: PSC_BASIC - name: ARR - description: auto-reload register (Dither mode disabled) + description: auto-reload register byte_offset: 44 fieldset: ARR_BASIC - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_BASIC - name: CCR - description: capture/compare register x (x=1) (Dither mode disabled) + description: capture/compare register x (x=1) array: len: 1 stride: 4 byte_offset: 52 fieldset: CCR_GP16 - - name: CCR_DITHER - description: capture/compare register x (x=1) (Dither mode enabled) - array: - len: 1 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP16 - name: TISEL description: input selection register - byte_offset: 92 + byte_offset: 104 fieldset: TISEL_1CH block/TIM_1CH_CMP: extends: TIM_1CH @@ -103,6 +92,14 @@ block/TIM_1CH_CMP: description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 - name: DTR2 description: break and dead-time register byte_offset: 84 @@ -111,18 +108,6 @@ block/TIM_1CH_CMP: description: alternate function register 1 byte_offset: 96 fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 block/TIM_2CH: extends: TIM_1CH description: 2-channel timers @@ -167,22 +152,15 @@ block/TIM_2CH: byte_offset: 32 fieldset: CCER_2CH - name: CCR - description: capture/compare register x (x=1-2) (Dither mode disabled) + description: capture/compare register x (x=1-2) array: len: 2 stride: 4 byte_offset: 52 fieldset: CCR_GP16 - - name: CCR_DITHER - description: capture/compare register x (x=1-2) (Dither mode enabled) - array: - len: 2 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP16 - name: TISEL description: input selection register - byte_offset: 92 + byte_offset: 104 fieldset: TISEL_2CH block/TIM_2CH_CMP: extends: TIM_2CH @@ -195,7 +173,7 @@ block/TIM_2CH_CMP: - name: SMCR description: slave mode control register byte_offset: 8 - fieldset: SMCR_2CH_CMP + fieldset: SMCR_2CH - name: DIER description: DMA/Interrupt enable register byte_offset: 12 @@ -221,30 +199,26 @@ block/TIM_2CH_CMP: description: break and dead-time register byte_offset: 68 fieldset: BDTR_1CH_CMP + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 - name: DTR2 description: break and dead-time register byte_offset: 84 fieldset: DTR2_ADV - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_2CH - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_1CH_CMP - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_2CH block/TIM_ADV: extends: TIM_GP16 description: Advanced Control timers @@ -282,22 +256,10 @@ block/TIM_ADV: description: break and dead-time register byte_offset: 68 fieldset: BDTR_ADV - - name: CCR5 - description: capture/compare register 5 (Dither mode disabled) - byte_offset: 72 - fieldset: CCR5_ADV - - name: CCR5_DITHER - description: capture/compare register 5 (Dither mode enabled) - byte_offset: 72 - fieldset: CCR5_DITHER_ADV - - name: CCR6 - description: capture/compare register 6 (Dither mode disabled) + - name: DMAR + description: DMA address for full transfer byte_offset: 76 - fieldset: CCR_GP16 - - name: CCR6_DITHER - description: capture/compare register 6 (Dither mode enabled) - byte_offset: 76 - fieldset: CCR_DITHER_GP16 + fieldset: DMAR_ADV - name: CCMR3 description: capture/compare mode register 3 byte_offset: 80 @@ -306,6 +268,14 @@ block/TIM_ADV: description: break and dead-time register byte_offset: 84 fieldset: DTR2_ADV + - name: CCR5 + description: capture/compare register 5 + byte_offset: 88 + fieldset: CCR5_ADV + - name: CCR6 + description: capture/compare register 6 + byte_offset: 92 + fieldset: CCR_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 @@ -347,13 +317,9 @@ block/TIM_BASIC: byte_offset: 40 fieldset: PSC_BASIC - name: ARR - description: auto-reload register (Dither mode disabled) + description: auto-reload register byte_offset: 44 fieldset: ARR_BASIC - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_BASIC block/TIM_GP16: extends: TIM_BASIC description: General purpose 16-bit timers @@ -402,77 +368,55 @@ block/TIM_GP16: byte_offset: 32 fieldset: CCER_GP16 - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) + description: capture/compare register x (x=1-4) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_GP16 - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP16 + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_GP16 + - name: DMAR + description: DMA address for full transfer + byte_offset: 76 + fieldset: DMAR_GP16 - name: ECR description: encoder control register byte_offset: 88 fieldset: ECR_GP16 - - name: TISEL - description: input selection register - byte_offset: 92 - fieldset: TISEL_GP16 - name: AF1 description: alternate function register 1 byte_offset: 96 fieldset: AF1_GP16 - - name: AF2 - description: alternate function register 2 - byte_offset: 100 - fieldset: AF2_GP16 - - name: DCR - description: DMA control register - byte_offset: 988 - fieldset: DCR_GP16 - - name: DMAR - description: DMA address for full transfer - byte_offset: 992 - fieldset: DMAR_GP16 + - name: TISEL + description: input selection register + byte_offset: 104 + fieldset: TISEL_GP16 block/TIM_GP32: extends: TIM_GP16 description: General purpose 32-bit timers items: - name: CNT - description: counter (Dither mode disabled) + description: counter byte_offset: 36 fieldset: CNT_GP32 - - name: CNT_DITHER - description: counter (Dither mode enbled) - byte_offset: 36 - fieldset: CNT_DITHER_GP32 - name: ARR - description: auto-reload register (Dither mode disabled) + description: auto-reload register byte_offset: 44 fieldset: ARR_GP32 - - name: ARR_DITHER - description: auto-reload register (Dither mode enabled) - byte_offset: 44 - fieldset: ARR_DITHER_GP32 - name: CCR - description: capture/compare register x (x=1-4) (Dither mode disabled) + description: capture/compare register x (x=1-4) array: len: 4 stride: 4 byte_offset: 52 fieldset: CCR_GP32 - - name: CCR_DITHER - description: capture/compare register x (x=1-4) (Dither mode enabled) - array: - len: 4 - stride: 4 - byte_offset: 52 - fieldset: CCR_DITHER_GP32 + - name: DCR + description: DMA control register + byte_offset: 72 + fieldset: DCR_1CH_CMP fieldset/AF1_1CH_CMP: description: alternate function register 1 fields: @@ -481,23 +425,27 @@ fieldset/AF1_1CH_CMP: bit_offset: 0 bit_size: 1 - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable + description: TIM_BRK_CMPx (x=1-2) enable bit_offset: 1 bit_size: 1 array: - len: 8 + len: 2 stride: 1 + - name: BKDF1BKE + description: BRK DFSDM1_BREAKx enable (x=0 if TIM15, x=1 if TIM16, x=2 if TIM17) + bit_offset: 8 + bit_size: 1 - name: BKINP description: TIMx_BKIN input polarity bit_offset: 9 bit_size: 1 enum: BKINP - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity + description: TIM_BRK_CMPx (x=1-2) input polarity bit_offset: 10 bit_size: 1 array: - len: 4 + len: 2 stride: 1 enum: BKINP fieldset/AF1_ADV: @@ -509,23 +457,27 @@ fieldset/AF1_ADV: bit_offset: 0 bit_size: 1 - name: BKCMPE - description: TIM_BRK_CMPx (x=1-8) enable + description: TIM_BRK_CMPx (x=1-2) enable bit_offset: 1 bit_size: 1 array: - len: 8 + len: 2 stride: 1 + - name: BKDF1BK0E + description: BRK1 DFSDM1_BREAK0 enable + bit_offset: 8 + bit_size: 1 - name: BKINP description: TIMx_BKIN input polarity bit_offset: 9 bit_size: 1 enum: BKINP - name: BKCMPP - description: TIM_BRK_CMPx (x=1-4) input polarity + description: TIM_BRK_CMPx (x=1-2) input polarity bit_offset: 10 bit_size: 1 array: - len: 4 + len: 2 stride: 1 enum: BKINP fieldset/AF1_GP16: @@ -550,6 +502,10 @@ fieldset/AF2_ADV: array: len: 1 stride: 8 + - name: BK2DF1BK1E + description: BRK2 DFSDM1_BREAK1 enable + bit_offset: 8 + bit_size: 1 - name: BK2INP description: TIMx_BK2IN input polarity bit_offset: 9 @@ -560,47 +516,18 @@ fieldset/AF2_ADV: bit_offset: 10 bit_size: 1 array: - len: 1 - stride: 4 + len: 2 + stride: 1 enum: BKINP -fieldset/AF2_GP16: - description: alternate function register 2 - fields: - - name: OCRSEL - description: ocref_clr source selection - bit_offset: 16 - bit_size: 3 fieldset/ARR_BASIC: - description: auto-reload register (Dither mode disabled) + description: auto-reload register fields: - name: ARR description: Auto-reload value bit_offset: 0 bit_size: 16 -fieldset/ARR_DITHER_BASIC: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 16 -fieldset/ARR_DITHER_GP32: - description: auto-reload register (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: ARR - description: Auto-reload value - bit_offset: 4 - bit_size: 28 fieldset/ARR_GP32: - description: auto-reload register (Dither mode disabled) + description: auto-reload register fields: - name: ARR description: Auto-reload value @@ -659,22 +586,6 @@ fieldset/BDTR_1CH_CMP: len: 1 stride: 4 enum: FilterValue - - name: BKDSRM - description: Break x (x=1) Disarm - bit_offset: 26 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKDSRM - - name: BKBID - description: Break x (x=1) bidirectional - bit_offset: 28 - bit_size: 1 - array: - len: 1 - stride: 1 - enum: BKBID fieldset/BDTR_ADV: description: break and dead-time register fields: @@ -834,11 +745,11 @@ fieldset/CCER_ADV: len: 6 stride: 4 - name: CCNE - description: Capture/Compare x (x=1-4) complementary output enable + description: Capture/Compare x (x=1-3) complementary output enable bit_offset: 2 bit_size: 1 array: - len: 4 + len: 3 stride: 4 fieldset/CCER_GP16: description: capture/compare enable register @@ -1084,7 +995,7 @@ fieldset/CCMR_Output_GP16: stride: 8 fieldset/CCR5_ADV: extends: CCR_GP16 - description: capture/compare register 5 (Dither mode disabled) + description: capture/compare register 5 fields: - name: GC5C description: Group channel 5 and channel x (x=1-3) @@ -1094,49 +1005,15 @@ fieldset/CCR5_ADV: len: 3 stride: 1 enum: GC5C -fieldset/CCR5_DITHER_ADV: - extends: CCR_DITHER_GP16 - description: capture/compare register 5 (Dither mode enabled) - fields: - - name: GC5C - description: Group channel 5 and channel x (x=1-3) - bit_offset: 29 - bit_size: 1 - array: - len: 3 - stride: 1 - enum: GC5C -fieldset/CCR_DITHER_GP16: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) - fields: - - name: DITHER - description: capture/compare x (x=1-4,6) value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 4 - bit_size: 16 -fieldset/CCR_DITHER_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode enabled) - fields: - - name: DITHER - description: Dither value - bit_offset: 0 - bit_size: 4 - - name: CCR - description: capture/compare x (x=1-4,6) value - bit_offset: 4 - bit_size: 28 fieldset/CCR_GP16: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) + description: capture/compare register x (x=1-4,6) fields: - name: CCR description: capture/compare x (x=1-4,6) value bit_offset: 0 bit_size: 16 fieldset/CCR_GP32: - description: capture/compare register x (x=1-4,6) (Dither mode disabled) + description: capture/compare register x (x=1-4,6) fields: - name: CCR description: capture/compare x (x=1-4,6) value @@ -1153,19 +1030,8 @@ fieldset/CNT_BASIC: description: UIF copy bit_offset: 31 bit_size: 1 -fieldset/CNT_DITHER_GP32: - description: counter (Dither mode enabled) - fields: - - name: CNT - description: counter value - bit_offset: 0 - bit_size: 31 - - name: UIFCPY - description: UIF copy - bit_offset: 31 - bit_size: 1 fieldset/CNT_GP32: - description: counter (Dither mode disabled) + description: counter fields: - name: CNT description: counter value @@ -1204,10 +1070,6 @@ fieldset/CR1_1CH: description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 fieldset/CR1_BASIC: description: control register 1 fields: @@ -1236,10 +1098,6 @@ fieldset/CR1_BASIC: description: UIF status bit remapping enable bit_offset: 11 bit_size: 1 - - name: DITHEN - description: Dithering enable - bit_offset: 12 - bit_size: 1 fieldset/CR1_GP16: extends: CR1_BASIC description: control register 1 @@ -1386,7 +1244,7 @@ fieldset/CR2_GP16: bit_offset: 7 bit_size: 1 enum: TI1S -fieldset/DCR_GP16: +fieldset/DCR_1CH_CMP: description: DMA control register fields: - name: DBA @@ -1397,6 +1255,10 @@ fieldset/DCR_GP16: description: DMA burst length bit_offset: 8 bit_size: 5 +fieldset/DCR_GP16: + extends: DCR_1CH_CMP + description: DMA control register + fields: - name: DBSS description: DMA burst source selection bit_offset: 16 @@ -1523,29 +1385,20 @@ fieldset/DIER_GP16: description: Trigger DMA request enable bit_offset: 14 bit_size: 1 - - name: IDXIE - description: Index interrupt enable - bit_offset: 20 - bit_size: 1 - - name: DIRIE - description: Direction change interrupt enable - bit_offset: 21 - bit_size: 1 - - name: IERRIE - description: Index error interrupt enable - bit_offset: 22 - bit_size: 1 - - name: TERRIE - description: Transition error interrupt enable - bit_offset: 23 - bit_size: 1 -fieldset/DMAR_GP16: +fieldset/DMAR_ADV: description: DMA address for full transfer fields: - name: DMAB description: DMA register for burst accesses bit_offset: 0 bit_size: 32 +fieldset/DMAR_GP16: + description: DMA address for full transfer + fields: + - name: DMAB + description: DMA register for burst accesses + bit_offset: 0 + bit_size: 16 fieldset/DTR2_ADV: description: deadtime register 2 fields: @@ -1716,14 +1569,6 @@ fieldset/SMCR_2CH: bit_offset: 7 bit_size: 1 enum: MSM -fieldset/SMCR_2CH_CMP: - extends: SMCR_2CH - description: slave mode control register - fields: - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 fieldset/SMCR_ADV: extends: SMCR_GP16 description: slave mode control register @@ -1770,15 +1615,6 @@ fieldset/SMCR_GP16: bit_offset: 15 bit_size: 1 enum: ETP - - name: SMSPE - description: SMS preload enable - bit_offset: 24 - bit_size: 1 - - name: SMSPS - description: SMS preload source - bit_offset: 25 - bit_size: 1 - enum: SMSPS fieldset/SR_1CH: description: status register fields: @@ -1889,22 +1725,6 @@ fieldset/SR_GP16: array: len: 4 stride: 1 - - name: IDXIF - description: Index interrupt flag - bit_offset: 20 - bit_size: 1 - - name: DIRIF - description: Direction change interrupt flag - bit_offset: 21 - bit_size: 1 - - name: IERRIF - description: Index error interrupt flag - bit_offset: 22 - bit_size: 1 - - name: TERRIF - description: Transition error interrupt flag - bit_offset: 23 - bit_size: 1 fieldset/TISEL_1CH: description: input selection register fields: @@ -2368,15 +2188,6 @@ enum/SMS: - name: Ext_Clock_Mode description: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. value: 7 -enum/SMSPS: - bit_size: 1 - variants: - - name: Update - description: The transfer is triggered by the Timer’s Update event - value: 0 - - name: Index - description: The transfer is triggered by the Index event - value: 1 enum/TI1S: bit_size: 1 variants: