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rcc: fix h5 fdcan inconsistency.

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This commit is contained in:
Dario Nieuwenhuis 2024-01-30 02:22:27 +01:00
parent 65bf109bd4
commit ab2bc2a739
1 changed files with 4 additions and 4 deletions
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8
data/registers/rcc_h50.yaml
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@ -379,7 +379,7 @@ fieldset/APB1HENR:
description: "LPTIM2 clock enable\r Set and reset by software."
bit_offset: 5
bit_size: 1
- name: FDCAN1EN
- name: FDCAN12EN
description: "FDCAN1 peripheral clock enable\r Set and reset by software."
bit_offset: 9
bit_size: 1
@ -394,7 +394,7 @@ fieldset/APB1HLPENR:
description: "LPTIM2 clock enable during sleep mode\r Set and reset by software."
bit_offset: 5
bit_size: 1
- name: FDCAN1LPEN
- name: FDCAN12LPEN
description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software."
bit_offset: 9
bit_size: 1
@ -409,7 +409,7 @@ fieldset/APB1HRSTR:
description: "LPTIM2 block reset\r Set and reset by software."
bit_offset: 5
bit_size: 1
- name: FDCAN1RST
- name: FDCAN12RST
description: "FDCAN1 block reset\r Set and reset by software."
bit_offset: 9
bit_size: 1
@ -905,7 +905,7 @@ fieldset/CCIPR5:
bit_offset: 4
bit_size: 2
enum: RNGSEL
- name: FDCAN1SEL
- name: FDCAN12SEL
description: FDCAN1 kernel clock source selection
bit_offset: 8
bit_size: 2