From ab2bc2a739324793656ca1640e1caee2d88df72d Mon Sep 17 00:00:00 2001
From: Dario Nieuwenhuis <dirbaio@dirbaio.net>
Date: Tue, 30 Jan 2024 02:22:27 +0100
Subject: [PATCH] rcc: fix h5 fdcan inconsistency.

---
 data/registers/rcc_h50.yaml | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml
index ae5d726..38dfa38 100644
--- a/data/registers/rcc_h50.yaml
+++ b/data/registers/rcc_h50.yaml
@@ -379,7 +379,7 @@ fieldset/APB1HENR:
     description: "LPTIM2 clock enable\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1EN
+  - name: FDCAN12EN
     description: "FDCAN1 peripheral clock enable\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -394,7 +394,7 @@ fieldset/APB1HLPENR:
     description: "LPTIM2 clock enable during sleep mode\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1LPEN
+  - name: FDCAN12LPEN
     description: "FDCAN1 peripheral clock enable during sleep mode\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -409,7 +409,7 @@ fieldset/APB1HRSTR:
     description: "LPTIM2 block reset\r Set and reset by software."
     bit_offset: 5
     bit_size: 1
-  - name: FDCAN1RST
+  - name: FDCAN12RST
     description: "FDCAN1 block reset\r Set and reset by software."
     bit_offset: 9
     bit_size: 1
@@ -905,7 +905,7 @@ fieldset/CCIPR5:
     bit_offset: 4
     bit_size: 2
     enum: RNGSEL
-  - name: FDCAN1SEL
+  - name: FDCAN12SEL
     description: FDCAN1 kernel clock source selection
     bit_offset: 8
     bit_size: 2