pwr_u5: cleanup enums.
This commit is contained in:
Dario Nieuwenhuis
parent
7530607864
commit
a4892a4f77
@ -148,7 +148,7 @@ fieldset/CR1:
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description: PWR control register 1
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fields:
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- name: LPMS
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description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS = 11X in CR1\r with BREN = 1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1"
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description: "Low-power mode selection\r These bits select the low-power mode entered when the CPU enters the Deepsleep mode.\r 10x: Standby mode (Standby mode also entered if LPMS=11X in CR1\r with BREN=1 in BDCR1)\r 11x: Shutdown mode if BREN = 0 in BDCR1"
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bit_offset: 0
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bit_size: 3
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enum: LPMS
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@ -193,57 +193,57 @@ fieldset/CR2:
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description: "SRAM1 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 0
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM1PDS2
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description: "SRAM1 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 1
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM1PDS3
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description: "SRAM1 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 2
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM2PDS1
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description: "SRAM2 page 1 (8 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 1 retention in Stop 3 is controlled by RRSB1 bit in CR1."
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bit_offset: 4
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM2PDS2
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description: "SRAM2 page 2 (56 Kbytes) power-down in Stop modes (Stop 0, 1, 2)\r Note: The SRAM2 page 2 retention in Stop 3 is controlled by RRSB2 bit in CR1."
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bit_offset: 5
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM4PDS
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description: "SRAM4 power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 6
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: ICRAMPDS
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description: "ICACHE SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 8
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bit_size: 1
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enum: ICRAMPDS
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enum: PDS
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- name: DC1RAMPDS
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description: "DCACHE1 SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 9
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bit_size: 1
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enum: DCRAMPDS
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enum: PDS
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- name: DMA2DRAMPDS
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description: "DMA2D SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 10
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bit_size: 1
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enum: DMADRAMPDS
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enum: PDS
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- name: PRAMPDS
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description: "FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop 0, 1, 2, 3)"
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description: "FMAC, FDCAN and USB peripherals SRAM power-down in Stop modes (Stop0,1,2,3)"
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bit_offset: 11
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bit_size: 1
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enum: PRAMPDS
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enum: PDS
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- name: PKARAMPDS
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description: PKA SRAM power-down
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bit_offset: 12
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bit_size: 1
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enum: PKARAMPDS
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enum: PDS
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- name: SRAM4FWU
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description: "SRAM4 fast wakeup from Stop 0, Stop 1 and Stop 2 modes\r This bit is used to obtain the best trade-off between low-power consumption and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting Stop 0, 1 and 2 modes, and also increases the LPDMA access time to SRAM4 during Stop modes."
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bit_offset: 13
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@ -258,47 +258,46 @@ fieldset/CR2:
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description: "SRAM3 page 1 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 16
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM3PDS2
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description: "SRAM3 page 2 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 17
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM3PDS3
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description: "SRAM3 page 3 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 18
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM3PDS4
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description: "SRAM3 page 4 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 19
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM3PDS5
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description: "SRAM3 page 5 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 20
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM3PDS6
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description: "SRAM3 page 6 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 21
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM3PDS7
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description: "SRAM3 page 7 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 22
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRAM3PDS8
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description: "SRAM3 page 8 (64 Kbytes) power-down in Stop modes (Stop 0, 1, 2, 3)"
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bit_offset: 23
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bit_size: 1
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enum: SRAMPDS
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enum: PDS
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- name: SRDRUN
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description: SmartRun domain in Run mode
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bit_offset: 31
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bit_size: 1
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enum: SRDRUN
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fieldset/CR3:
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description: PWR control register 3
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fields:
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@ -336,12 +335,12 @@ fieldset/PRIVCFGR:
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description: "PWR secure functions privilege configuration\r This bit is set and reset by software. It can be written only by a secure privileged access."
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bit_offset: 0
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bit_size: 1
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enum: SPRIV
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enum: PRIV
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- name: NSPRIV
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description: "PWR non-secure functions privilege configuration\r This bit is set and reset by software. It can be written only by privileged access, secure or non-secure."
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bit_offset: 1
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bit_size: 1
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enum: NSPRIV
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enum: PRIV
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fieldset/SECCFGR:
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description: PWR security configuration register
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fields:
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@ -349,79 +348,77 @@ fieldset/SECCFGR:
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description: WUP1 secure protection
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bit_offset: 0
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: WUP2SEC
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description: WUP2 secure protection
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bit_offset: 1
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: WUP3SEC
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description: WUP3 secure protection
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bit_offset: 2
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: WUP4SEC
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description: WUP4 secure protection
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bit_offset: 3
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: WUP5SEC
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description: WUP5 secure protection
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bit_offset: 4
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: WUP6SEC
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description: WUP6 secure protection
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bit_offset: 5
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: WUP7SEC
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description: WUP7 secure protection
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bit_offset: 6
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: WUP8SEC
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description: WUP8 secure protection
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bit_offset: 7
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bit_size: 1
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enum: WUPSEC
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enum: SEC
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- name: LPMSEC
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description: Low-power modes secure protection
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bit_offset: 12
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bit_size: 1
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enum: LPMSEC
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enum: SEC
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- name: VDMSEC
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description: Voltage detection and monitoring secure protection
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bit_offset: 13
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bit_size: 1
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enum: VDMSEC
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enum: SEC
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- name: VBSEC
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description: Backup domain secure protection
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bit_offset: 14
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bit_size: 1
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enum: VBSEC
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enum: SEC
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- name: APCSEC
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description: Pull-up/pull-down secure protection
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bit_offset: 15
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bit_size: 1
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enum: APCSEC
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enum: SEC
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fieldset/SR:
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description: PWR status register
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fields:
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- name: CSSF
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description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC = 1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC = 1 and SPRIV = 1 in PRIVCFGR, or when LPMSEC = 0 and NSPRIV = 1.\r Writing 1 to this bit clears the STOPF and SBF flags."
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description: "Clear Stop and Standby flags\r This bit is protected against non-secure access when LPMSEC=1 in SECCFGR.\r This bit is protected against unprivileged access when LPMSEC=1 and SPRIV=1 in PRIVCFGR, or when LPMSEC=0 and NSPRIV=1.\r Writing 1 to this bit clears the STOPF and SBF flags."
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bit_offset: 0
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bit_size: 1
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- name: STOPF
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description: "Stop flag\r This bit is set by hardware when the device enters a Stop mode, and is cleared by software by writing 1 to the CSSF bit."
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bit_offset: 1
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bit_size: 1
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enum: STOPF
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- name: SBF
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description: "Standby flag\r This bit is set by hardware when the device enters the Standby mode, and is cleared by writing 1 to the CSSF bit, or by a power-on reset. It is not cleared by the system reset."
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bit_offset: 2
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bit_size: 1
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enum: SBF
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fieldset/SVMCR:
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description: PWR supply voltage monitoring control register
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fields:
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@ -429,7 +426,6 @@ fieldset/SVMCR:
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description: Power voltage detector enable
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bit_offset: 4
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bit_size: 1
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enum: PVDE
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- name: PVDLS
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description: "Power voltage detector level selection\r These bits select the voltage threshold detected by the power voltage detector:"
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bit_offset: 5
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@ -444,35 +440,32 @@ fieldset/SVMCR:
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bit_offset: 25
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bit_size: 1
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- name: AVM1EN
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description: VDDA independent analog supply voltage monitor 1 enable (1.6 V threshold)
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description: VDDA independent analog supply voltage monitor 1 enable (1.6V threshold)
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bit_offset: 26
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bit_size: 1
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- name: AVM2EN
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description: VDDA independent analog supply voltage monitor 2 enable (1.8 V threshold)
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description: VDDA independent analog supply voltage monitor 2 enable (1.8V threshold)
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bit_offset: 27
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bit_size: 1
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- name: USV
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description: VDDUSB independent USB supply valid
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bit_offset: 28
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bit_size: 1
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enum: USV
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- name: IO2SV
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description: "VDDIO2 independent I/Os supply valid\r This bit is used to validate the VDDIO2 supply for electrical and logical isolation purpose.\r Setting this bit is mandatory to use PG[15:2]. If VDDIO2 is not always present in the application, the VDDIO2 voltage monitor can be used to determine whether this supply is ready or not."
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bit_offset: 29
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bit_size: 1
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enum: IOSV
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- name: ASV
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description: VDDA independent analog supply valid
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bit_offset: 30
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bit_size: 1
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enum: ASV
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fieldset/SVMSR:
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fields:
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- name: REGS
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description: Regulator selection
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bit_offset: 1
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bit_size: 1
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enum: REGS
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enum: REGSEL
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- name: PVDO
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description: VDD voltage detector output
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bit_offset: 4
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@ -482,7 +475,6 @@ fieldset/SVMSR:
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description: Voltage level ready for currently used VOS
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bit_offset: 15
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bit_size: 1
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enum: ACTVOSRDY
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- name: ACTVOS
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description: "VOS currently applied to VCORE\r This field provides the last VOS value."
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bit_offset: 16
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@ -492,22 +484,18 @@ fieldset/SVMSR:
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description: VDDUSB ready
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bit_offset: 24
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bit_size: 1
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enum: VDDUSBRDY
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- name: VDDIO2RDY
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description: VDDIO2 ready
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bit_offset: 25
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bit_size: 1
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enum: VDDIORDY
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- name: VDDA1RDY
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description: VDDA ready versus 1.6V voltage monitor
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bit_offset: 26
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bit_size: 1
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enum: VDDARDY
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- name: VDDA2RDY
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description: VDDA ready versus 1.8 V voltage monitor
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description: VDDA ready versus 1.8V voltage monitor
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bit_offset: 27
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bit_size: 1
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enum: VDDARDY
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fieldset/UCPDR:
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description: PWR USB Type-C™ and Power Delivery register
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fields:
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@ -515,7 +503,6 @@ fieldset/UCPDR:
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description: "UCPD dead battery disable\r After exiting reset, the USB Type-C “dead battery” behavior is enabled, which may have a pull-down effect on CC1 and CC2 pins. It is recommended to disable it in all cases, either to stop this pull-down or to handover control to the UCPD (the UCPD must be initialized before doing the disable)."
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bit_offset: 0
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bit_size: 1
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enum: UCPD_DBDIS
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- name: UCPD_STBY
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description: "UCPD Standby mode\r When set, this bit is used to memorize the UCPD configuration in Standby mode.\r This bit must be written to 1 just before entering Standby mode when using UCPD.\r It must be written to 0 after exiting the Standby mode and before writing any UCPD registers."
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bit_offset: 1
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@ -527,14 +514,12 @@ fieldset/VOSR:
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description: "EPOD booster ready\r This bit is set to 1 by hardware when the power booster startup time is reached. The system clock frequency can be switched higher than 50 MHz only after this bit is set."
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bit_offset: 14
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bit_size: 1
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enum: BOOSTRDY
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- name: VOSRDY
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description: Ready bit for VCORE voltage scaling output selection
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bit_offset: 15
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bit_size: 1
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enum: VOSRDY
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- name: VOS
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description: "Voltage scaling range selection\r This field is protected against non-secure access when SYSCLKSEC = 1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC = 1 in RCC_SECCFGR and SPRIV = 1 in PRIVCFGR, or when SYSCLKSEC = 0 and NSPRIV = 1."
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description: "Voltage scaling range selection\r This field is protected against non-secure access when SYSCLKSEC=1 in RCC_SECCFGR. It is protected against unprivileged access when SYSCLKSEC=1 in RCC_SECCFGR and SPRIV=1 in PRIVCFGR, or when SYSCLKSEC=0 and NSPRIV=1."
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bit_offset: 16
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bit_size: 2
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enum: VOS
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@ -616,7 +601,7 @@ fieldset/WUCR2:
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bit_size: 1
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enum: WUPP
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- name: WUPP8
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description: "Wakeup pin WKUP8 polarity\r This bit must be configured when WUPEN8 = 0."
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description: "Wakeup pin WKUP8 polarity\r This bit must be configured when WUPEN8=0."
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bit_offset: 7
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bit_size: 1
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enum: WUPP
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@ -702,202 +687,103 @@ fieldset/WUSR:
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description: PWR wakeup status register
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fields:
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- name: WUF1
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description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1 = 0."
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description: "Wakeup flag 1\r This bit is set when a wakeup event is detected on WKUP1 pin. This bit is cleared by writing 1 in the CWUF1 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN1=0."
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bit_offset: 0
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bit_size: 1
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- name: WUF2
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description: "Wakeup flag 2\r This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2 = 0."
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description: "Wakeup flag 2\r This bit is set when a wakeup event is detected on WKUP2 pin. This bit is cleared by writing 1 in the CWUF2 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN2=0."
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bit_offset: 1
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bit_size: 1
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- name: WUF3
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description: "Wakeup flag 3\r This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3 = 0."
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description: "Wakeup flag 3\r This bit is set when a wakeup event is detected on WKUP3 pin. This bit is cleared by writing 1 in the CWUF3 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN3=0."
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bit_offset: 2
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bit_size: 1
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- name: WUF4
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description: "Wakeup flag 4\r This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4 = 0."
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description: "Wakeup flag 4\r This bit is set when a wakeup event is detected on WKUP4 pin. This bit is cleared by writing 1 in the CWUF4 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN4=0."
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bit_offset: 3
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bit_size: 1
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- name: WUF5
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description: "Wakeup flag 5\r This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5 = 0."
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description: "Wakeup flag 5\r This bit is set when a wakeup event is detected on WKUP5 pin. This bit is cleared by writing 1 in the CWUF5 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN5=0."
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bit_offset: 4
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bit_size: 1
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- name: WUF6
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description: "Wakeup flag 6\r This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6 = 0.\r If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared."
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description: "Wakeup flag 6\r This bit is set when a wakeup event is detected on WKUP6 pin. This bit is cleared by writing 1 in the CWUF6 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN6=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared."
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bit_offset: 5
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bit_size: 1
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- name: WUF7
|
||||
description: "Wakeup flag 7\r This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7 = 0.\r If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared."
|
||||
description: "Wakeup flag 7\r This bit is set when a wakeup event is detected on WKUP7 pin. This bit is cleared by writing 1 in the CWUF7 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN7=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared."
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: WUF8
|
||||
description: "Wakeup flag 8\r This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8 = 0.\r If WUSEL = 11, this bit is cleared by hardware when all internal wakeup source are cleared."
|
||||
description: "Wakeup flag 8\r This bit is set when a wakeup event is detected on WKUP8 pin. This bit is cleared by writing 1 in the CWUF8 bit of WUSCR when WUSEL ≠ 11, or by hardware when WUPEN8=0.\r If WUSEL=11, this bit is cleared by hardware when all internal wakeup source are cleared."
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
enum/ACTVOS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: Range4
|
||||
description: Range 4 (lowest power)
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: Range3
|
||||
description: Range 3
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
- name: Range2
|
||||
description: Range 2
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
- name: Range1
|
||||
description: Range 1 (highest frequency)
|
||||
value: 3
|
||||
enum/ACTVOSRDY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "VCORE is above or below the current voltage scaling provided by ACTVOS[1:0]."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "VCORE is equal to the current voltage scaling provided by ACTVOS[1:0]"
|
||||
value: 1
|
||||
enum/APCSEC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: APCR can be read and written with secure or non-secure access.
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: APCR can be read and written only with secure access.
|
||||
value: 1
|
||||
enum/ASV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "VDDA not present: logical and electrical isolation is applied to ignore this supply."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: VDDA valid
|
||||
value: 1
|
||||
enum/BOOSTRDY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: Power booster not ready
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: Power booster ready
|
||||
value: 1
|
||||
enum/DBP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: Disabled
|
||||
description: Write access to Backup domain disabled
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: Enabled
|
||||
description: Write access to Backup domain enabled
|
||||
value: 1
|
||||
enum/DCRAMPDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: DCACHE1 SRAM content retained in Stop modes
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: DCACHE1 SRAM content lost in Stop modes
|
||||
value: 1
|
||||
enum/DMADRAMPDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: DMA2D SRAM content retained in Stop modes
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: DMA2D SRAM content lost in Stop modes
|
||||
value: 1
|
||||
enum/FLASHFWU:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: LowPower
|
||||
description: Flash memory enters low-power mode in Stop 0 and Stop 1 modes (lower-power consumption).
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: Normal
|
||||
description: Flash memory remains in normal mode in Stop 0 and Stop 1 modes (faster wakeup time).
|
||||
value: 1
|
||||
enum/ICRAMPDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: ICACHE SRAM content retained in Stop modes
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: ICACHE SRAM content lost in Stop modes
|
||||
value: 1
|
||||
enum/IOSV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "VDDIO2 not present: logical and electrical isolation is applied to ignore this supply."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: VDDIO2 valid
|
||||
value: 1
|
||||
enum/LPMS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: Stop0
|
||||
description: Stop 0 mode
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: Stop1
|
||||
description: Stop 1 mode
|
||||
value: 1
|
||||
- name: B_0x2
|
||||
- name: Stop2
|
||||
description: Stop 2 mode
|
||||
value: 2
|
||||
- name: B_0x3
|
||||
- name: Stop3
|
||||
description: Stop 3 mode
|
||||
value: 3
|
||||
enum/LPMSEC:
|
||||
enum/PDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "CR1, CR2 and CSSF in the SR can be read and written with secure or non-secure access."
|
||||
- name: Retained
|
||||
description: Content retained in Stop modes
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "CR1, CR2, and CSSF in the SR can be read and written only with secure access."
|
||||
- name: Lost
|
||||
description: Content lost in Stop modes
|
||||
value: 1
|
||||
enum/NSPRIV:
|
||||
enum/PRIV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: Unprivileged
|
||||
description: Read and write to PWR non-secure functions can be done by privileged or unprivileged access.
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: Privileged
|
||||
description: Read and write to PWR non-secure functions can be done by privileged access only.
|
||||
value: 1
|
||||
enum/PKARAMPDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: PKA SRAM content retained in Stop modes
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: PKA SRAM content lost in Stop modes
|
||||
value: 1
|
||||
enum/PRAMPDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "FMAC, FDCAN and USB peripherals SRAM content retained in Stop modes"
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "FMAC, FDCAN and USB peripherals SRAM content lost in Stop modes"
|
||||
value: 1
|
||||
enum/PVDE:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: Power voltage detector disabled
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: Power voltage detector enabled
|
||||
value: 1
|
||||
enum/PVDLS:
|
||||
bit_size: 3
|
||||
variants:
|
||||
@ -928,56 +814,38 @@ enum/PVDLS:
|
||||
enum/PVDO:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: AboveOrEqual
|
||||
description: "VDD is equal or above the PVD threshold selected by PVDLS[2:0]."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: Below
|
||||
description: "VDD is below the PVD threshold selected by PVDLS[2:0]."
|
||||
value: 1
|
||||
enum/REGS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: LDO selected
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: SMPS selected
|
||||
value: 1
|
||||
enum/REGSEL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: LDO
|
||||
description: LDO selected
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: SMPS
|
||||
description: SMPS selected
|
||||
value: 1
|
||||
enum/RRSB:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: NotRetained
|
||||
description: SRAM2 page1 content not retained in Stop 3 and Standby modes
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: Retained
|
||||
description: SRAM2 page1 content retained in Stop 3 and Standby modes
|
||||
value: 1
|
||||
enum/SBF:
|
||||
enum/SEC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: The device did not enter Standby mode.
|
||||
- name: NonSecure
|
||||
description: "CR1, CR2 and CSSF in the SR can be read and written with secure or non-secure access."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: The device entered Standby mode.
|
||||
value: 1
|
||||
enum/SPRIV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: Read and write to PWR secure functions can be done by privileged or unprivileged access.
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: Read and write to PWR secure functions can be done by privileged access only.
|
||||
- name: Secure
|
||||
description: "CR1, CR2, and CSSF in the SR can be read and written only with secure access."
|
||||
value: 1
|
||||
enum/SRAMFWU:
|
||||
bit_size: 1
|
||||
@ -991,39 +859,12 @@ enum/SRAMFWU:
|
||||
enum/SRAMPD:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
- name: PoweredOn
|
||||
description: SRAM1 powered on
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
- name: PoweredOff
|
||||
description: SRAM1 powered off
|
||||
value: 1
|
||||
enum/SRAMPDS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: SRAM3 page 1 content retained in Stop modes
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: SRAM3 page 1 content lost in Stop modes
|
||||
value: 1
|
||||
enum/SRDRUN:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "SmartRun domain AHB3 and APB3 clocks disabled by default in Stop 0,1, 2 modes"
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "SmartRun domain AHB3 and APB3 clocks kept enabled in Stop 0,1, 2 modes"
|
||||
value: 1
|
||||
enum/STOPF:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: The device did not enter any Stop mode.
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: The device entered a Stop mode.
|
||||
value: 1
|
||||
enum/TEMPH:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -1042,24 +883,6 @@ enum/TEMPL:
|
||||
- name: B_0x1
|
||||
description: Temperature ≤ low threshold
|
||||
value: 1
|
||||
enum/UCPD_DBDIS:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: UCPD dead battery pull-down behavior enabled on UCPDx_CC1 and UCPDx_CC2 pins
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: UCPD dead battery pull-down behavior disabled on UCPDx_CC1 and UCPDx_CC2 pins
|
||||
value: 1
|
||||
enum/USV:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "VDDUSB not present: logical and electrical isolation is applied to ignore this supply."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: VDDUSB valid
|
||||
value: 1
|
||||
enum/VBATH:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -1087,51 +910,6 @@ enum/VBRS:
|
||||
- name: B_0x1
|
||||
description: Charge VBAT through a 1.5 kΩ resistor
|
||||
value: 1
|
||||
enum/VBSEC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "BDCR1, BDCR2 and DBPR can be read and written with secure or non-secure access."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "BDCR1, BDCR2 and DBPR can be read and written only with secure access."
|
||||
value: 1
|
||||
enum/VDDARDY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: VDDA is below the threshold of the VDDA voltage monitor 2 (around 1.8 V).
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: VDDA is equal or above the threshold of the VDDA voltage monitor 2 (around 1.8 V).
|
||||
value: 1
|
||||
enum/VDDIORDY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: VDDIO2 is below the threshold of the VDDIO2 voltage monitor.
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: VDDIO2 is equal or above the threshold of the VDDIO2 voltage monitor.
|
||||
value: 1
|
||||
enum/VDDUSBRDY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: VDDUSB is below the threshold of the VDDUSB voltage monitor.
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: VDDUSB is equal or above the threshold of the VDDUSB voltage monitor.
|
||||
value: 1
|
||||
enum/VDMSEC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: SVMCR and CR3 can be read and written with secure or non-secure access.
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: SVMCR and CR3 can be read and written only with secure access.
|
||||
value: 1
|
||||
enum/VOS:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -1147,15 +925,6 @@ enum/VOS:
|
||||
- name: B_0x3
|
||||
description: Range 1 (highest frequency). This value cannot be written when VCOREMEN = 1 in TAMP_OR register.
|
||||
value: 3
|
||||
enum/VOSRDY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "Not ready, voltage level < VOS selected level"
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "Ready, voltage level ≥ VOS selected level"
|
||||
value: 1
|
||||
enum/WUPP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -1165,15 +934,6 @@ enum/WUPP:
|
||||
- name: B_0x1
|
||||
description: Detection on low level (falling edge)
|
||||
value: 1
|
||||
enum/WUPSEC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: B_0x0
|
||||
description: "Bits related to the WKUP3 pin in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written with secure or non-secure access."
|
||||
value: 0
|
||||
- name: B_0x1
|
||||
description: "Bits related to the WKUP3 pin in WUCR1, WUCR2, WUCR3 and WUSCR can be read and written only with secure access."
|
||||
value: 1
|
||||
enum/WUSEL:
|
||||
bit_size: 2
|
||||
variants:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user