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STM32G4: Add enum for CLK48SEL

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This commit is contained in:
Kevin Lannen 2023-06-19 16:23:06 -06:00
parent ca29cf87d5
commit a1189407f7
1 changed files with 10 additions and 0 deletions
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10
data/registers/rcc_g4.yaml
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@ -1022,6 +1022,7 @@ fieldset/CCIPR:
description: 48 MHz clock source selection description: 48 MHz clock source selection
bit_offset: 26 bit_offset: 26
bit_size: 2 bit_size: 2
enum: CLK48SEL
- name: ADC12SEL - name: ADC12SEL
description: ADCs clock source selection description: ADCs clock source selection
bit_offset: 28 bit_offset: 28
@ -1479,3 +1480,12 @@ enum/SW:
- name: PLLRCLK - name: PLLRCLK
description: PLLRCLK selected as system clock description: PLLRCLK selected as system clock
value: 3 value: 3
enum/CLK48SEL:
bit_size: 2
variants:
- name: HSI48
description: HSI48 oscillator clock selected as 48 MHz clock
value: 0
- name: PLLQCLK
description: PLLQCLK selected as 48 MHz clock
value: 2