From a1189407f75056ba6081f51a3fec876c396738c1 Mon Sep 17 00:00:00 2001
From: Kevin Lannen <kevin@luci.com>
Date: Mon, 19 Jun 2023 16:23:06 -0600
Subject: [PATCH] STM32G4: Add enum for CLK48SEL

---
 data/registers/rcc_g4.yaml | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/data/registers/rcc_g4.yaml b/data/registers/rcc_g4.yaml
index ac07c3c..14d00f3 100644
--- a/data/registers/rcc_g4.yaml
+++ b/data/registers/rcc_g4.yaml
@@ -1022,6 +1022,7 @@ fieldset/CCIPR:
       description: 48 MHz clock source selection
       bit_offset: 26
       bit_size: 2
+      enum: CLK48SEL
     - name: ADC12SEL
       description: ADCs clock source selection
       bit_offset: 28
@@ -1479,3 +1480,12 @@ enum/SW:
     - name: PLLRCLK
       description: PLLRCLK selected as system clock
       value: 3
+enum/CLK48SEL:
+  bit_size: 2
+  variants:
+    - name: HSI48
+      description: HSI48 oscillator clock selected as 48 MHz clock
+      value: 0
+    - name: PLLQCLK
+      description: PLLQCLK selected as 48 MHz clock
+      value: 2