Support STM32WL5x ADC peripheral

data/registers/rcc_wl5.yaml

@@ -1059,6 +1059,7 @@ fieldset/CCIPR:
       description: ADC clock source selection
       bit_offset: 28
       bit_size: 2
+      enum: ADCSEL
     - name: RNGSEL
       description: RNG clock source selection
       bit_offset: 30
@@ -1422,3 +1423,15 @@ fieldset/PLLCFGR:
       description: Main PLL division factor for PLLRCLK
       bit_offset: 29
       bit_size: 3
+enum/ADCSEL:
+  bit_size: 2
+  variants:
+    - name: HSI16
+      description: HSI16 used as ADC clock source
+      value: 1
+    - name: PLLPCLK
+      description: PLLPCLK used as ADC clock source
+      value: 2
+    - name: SYSCLK
+      description: SYSCLK used as ADC clock source
+      value: 3

stm32-data-gen/src/chips.rs

@@ -207,6 +207,7 @@ impl PeriMatcher {
             ("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")),
             ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")),
             ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")),
+            ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")),
             ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")),
             ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")),
             ("STM32H50.*:SBS:.*", ("sbs", "h50", "SBS")),