From 9c71725bf20190c452fa030fdf11160ef2b65240 Mon Sep 17 00:00:00 2001 From: Olle Sandberg Date: Tue, 5 Sep 2023 12:20:52 +0200 Subject: [PATCH] Support STM32WL5x ADC peripheral --- data/registers/rcc_wl5.yaml | 13 +++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 14 insertions(+) diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index 828c986..9b9fee8 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -1059,6 +1059,7 @@ fieldset/CCIPR: description: ADC clock source selection bit_offset: 28 bit_size: 2 + enum: ADCSEL - name: RNGSEL description: RNG clock source selection bit_offset: 30 @@ -1422,3 +1423,15 @@ fieldset/PLLCFGR: description: Main PLL division factor for PLLRCLK bit_offset: 29 bit_size: 3 +enum/ADCSEL: + bit_size: 2 + variants: + - name: HSI16 + description: HSI16 used as ADC clock source + value: 1 + - name: PLLPCLK + description: PLLPCLK used as ADC clock source + value: 2 + - name: SYSCLK + description: SYSCLK used as ADC clock source + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index dda3ed6..5271317 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -207,6 +207,7 @@ impl PeriMatcher { ("STM32U5.*:SYSCFG:.*", ("syscfg", "u5", "SYSCFG")), ("STM32WB.*:SYSCFG:.*", ("syscfg", "wb", "SYSCFG")), ("STM32WL5.*:SYSCFG:.*", ("syscfg", "wl5", "SYSCFG")), + ("STM32WL5.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32WLE.*:SYSCFG:.*", ("syscfg", "wle", "SYSCFG")), ("STM32WLE.*:ADC:.*", ("adc", "g0", "ADC")), ("STM32H50.*:SBS:.*", ("sbs", "h50", "SBS")),