DMA cleanup
This commit is contained in:
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91cee0d1fd
commit
9a5ac3abce
@ -60,20 +60,17 @@ fieldset/CR:
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bit_size: 1
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enum: DIR
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- name: CIRC
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description: Circular mode
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description: Circular mode enabled
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bit_offset: 5
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bit_size: 1
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enum: CIRC
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- name: PINC
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description: Peripheral increment mode
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description: Peripheral increment mode enabled
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bit_offset: 6
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bit_size: 1
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enum: INC
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- name: MINC
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description: Memory increment mode
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description: Memory increment mode enabled
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bit_offset: 7
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bit_size: 1
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enum: INC
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- name: PSIZE
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description: Peripheral size
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bit_offset: 8
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@ -90,10 +87,9 @@ fieldset/CR:
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bit_size: 2
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enum: PL
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- name: MEM2MEM
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description: Memory to memory mode
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description: Memory to memory mode enabled
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bit_offset: 14
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bit_size: 1
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enum: MEMMEM
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fieldset/ISR:
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description: DMA interrupt status register (DMA_ISR)
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fields:
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@ -132,15 +128,6 @@ fieldset/NDTR:
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description: Number of data to transfer
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bit_offset: 0
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bit_size: 16
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enum/CIRC:
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bit_size: 1
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variants:
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- name: Disabled
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description: Circular buffer disabled
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value: 0
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- name: Enabled
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description: Circular buffer enabled
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value: 1
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enum/DIR:
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bit_size: 1
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variants:
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@ -150,24 +137,6 @@ enum/DIR:
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- name: FromMemory
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description: Read from memory
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value: 1
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enum/INC:
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bit_size: 1
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variants:
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- name: Disabled
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description: Increment mode disabled
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value: 0
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- name: Enabled
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description: Increment mode enabled
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value: 1
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enum/MEMMEM:
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bit_size: 1
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variants:
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- name: Disabled
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description: Memory to memory mode disabled
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value: 0
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- name: Enabled
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description: Memory to memory mode enabled
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value: 1
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enum/PL:
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bit_size: 2
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variants:
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@ -64,20 +64,17 @@ fieldset/CR:
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bit_size: 1
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enum: DIR
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- name: CIRC
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description: Circular mode
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description: Circular mode enabled
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bit_offset: 5
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bit_size: 1
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enum: CIRC
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- name: PINC
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description: Peripheral increment mode
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description: Peripheral increment mode enabled
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bit_offset: 6
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bit_size: 1
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enum: INC
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- name: MINC
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description: Memory increment mode
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description: Memory increment mode enabled
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bit_offset: 7
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bit_size: 1
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enum: INC
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- name: PSIZE
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description: Peripheral size
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bit_offset: 8
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@ -94,10 +91,9 @@ fieldset/CR:
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bit_size: 2
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enum: PL
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- name: MEM2MEM
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description: Memory to memory mode
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description: Memory to memory mode enabled
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bit_offset: 14
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bit_size: 1
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enum: MEMMEM
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fieldset/CSELR:
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description: channel selection register
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fields:
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@ -146,15 +142,6 @@ fieldset/NDTR:
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description: Number of data to transfer
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bit_offset: 0
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bit_size: 16
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enum/CIRC:
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bit_size: 1
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variants:
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- name: Disabled
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description: Circular buffer disabled
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value: 0
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- name: Enabled
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description: Circular buffer enabled
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value: 1
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enum/DIR:
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bit_size: 1
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variants:
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@ -164,24 +151,6 @@ enum/DIR:
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- name: FromMemory
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description: Read from memory
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value: 1
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enum/INC:
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bit_size: 1
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variants:
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- name: Disabled
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description: Increment mode disabled
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value: 0
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- name: Enabled
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description: Increment mode enabled
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value: 1
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enum/MEMMEM:
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bit_size: 1
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variants:
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- name: Disabled
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description: Memory to memory mode disabled
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value: 0
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- name: Enabled
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description: Memory to memory mode enabled
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value: 1
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enum/PL:
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bit_size: 2
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variants:
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@ -97,7 +97,6 @@ fieldset/AMTCR:
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description: Enable
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bit_offset: 0
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bit_size: 1
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enum: EN
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- name: DT
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description: Dead Time
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bit_offset: 8
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@ -200,7 +199,6 @@ fieldset/CR:
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description: Suspend
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bit_offset: 1
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bit_size: 1
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enum: SUSP
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- name: ABORT
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description: Abort
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bit_offset: 2
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@ -210,32 +208,26 @@ fieldset/CR:
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description: Transfer error interrupt enable
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bit_offset: 8
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bit_size: 1
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enum: TEIE
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- name: TCIE
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description: Transfer complete interrupt enable
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bit_offset: 9
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bit_size: 1
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enum: TCIE
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- name: TWIE
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description: Transfer watermark interrupt enable
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bit_offset: 10
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bit_size: 1
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enum: TWIE
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- name: CAEIE
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description: CLUT access error interrupt enable
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bit_offset: 11
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bit_size: 1
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enum: CAEIE
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- name: CTCIE
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description: CLUT transfer complete interrupt enable
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bit_offset: 12
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bit_size: 1
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enum: CTCIE
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- name: CEIE
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description: Configuration Error Interrupt Enable
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bit_offset: 13
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bit_size: 1
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enum: CEIE
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- name: MODE
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description: DMA2D mode
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bit_offset: 16
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@ -521,15 +513,6 @@ enum/CAECIF:
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- name: Clear
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description: Clear the CAEIF flag in the ISR register
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value: 1
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enum/CAEIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: CAE interrupt disabled
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value: 0
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- name: Enabled
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description: CAE interrupt enabled
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value: 1
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enum/CCEIF:
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bit_size: 1
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variants:
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@ -542,30 +525,12 @@ enum/CCTCIF:
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- name: Clear
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description: Clear the CTCIF flag in the ISR register
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value: 1
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enum/CEIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: CE interrupt disabled
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value: 0
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- name: Enabled
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description: CE interrupt enabled
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value: 1
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enum/CR_START:
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bit_size: 1
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variants:
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- name: Start
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description: Launch the DMA2D
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value: 1
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enum/CTCIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: CTC interrupt disabled
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value: 0
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- name: Enabled
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description: CTC interrupt enabled
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value: 1
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enum/CTCIF:
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bit_size: 1
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variants:
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@ -584,15 +549,6 @@ enum/CTWIF:
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- name: Clear
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description: Clear the TWIF flag in the ISR register
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value: 1
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enum/EN:
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bit_size: 1
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variants:
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- name: Disabled
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description: Disabled AHB/AXI dead-time functionality
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value: 0
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- name: Enabled
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description: Enabled AHB/AXI dead-time functionality
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value: 1
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enum/FGPFCCR_AM:
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bit_size: 2
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variants:
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@ -689,39 +645,3 @@ enum/OPFCCR_CM:
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- name: ARGB4444
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description: ARGB4444
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value: 4
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enum/SUSP:
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bit_size: 1
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variants:
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- name: NotSuspended
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description: Transfer not suspended
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value: 0
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- name: Suspended
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description: Transfer suspended
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value: 1
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enum/TCIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: TC interrupt disabled
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value: 0
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- name: Enabled
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description: TC interrupt enabled
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value: 1
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enum/TEIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: TE interrupt disabled
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value: 0
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- name: Enabled
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description: TE interrupt enabled
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value: 1
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enum/TWIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: TW interrupt disabled
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value: 0
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- name: Enabled
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description: TW interrupt enabled
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value: 1
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@ -89,7 +89,6 @@ fieldset/AMTCR:
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description: Enable Enables the dead time functionality.
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bit_offset: 0
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bit_size: 1
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enum: EN
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- name: DT
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description: Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses.
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bit_offset: 8
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@ -183,7 +182,6 @@ fieldset/CR:
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description: Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset.
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bit_offset: 1
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bit_size: 1
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enum: SUSP
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- name: ABORT
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description: Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset.
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bit_offset: 2
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@ -193,32 +191,26 @@ fieldset/CR:
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description: Transfer error interrupt enable This bit is set and cleared by software.
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bit_offset: 8
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bit_size: 1
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enum: TEIE
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- name: TCIE
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description: Transfer complete interrupt enable This bit is set and cleared by software.
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bit_offset: 9
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bit_size: 1
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enum: TCIE
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- name: TWIE
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description: Transfer watermark interrupt enable This bit is set and cleared by software.
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bit_offset: 10
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bit_size: 1
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enum: TWIE
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- name: CAEIE
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description: CLUT access error interrupt enable This bit is set and cleared by software.
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bit_offset: 11
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bit_size: 1
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enum: CAEIE
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- name: CTCIE
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description: CLUT transfer complete interrupt enable This bit is set and cleared by software.
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bit_offset: 12
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bit_size: 1
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enum: CTCIE
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- name: CEIE
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description: Configuration Error Interrupt Enable This bit is set and cleared by software.
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bit_offset: 13
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bit_size: 1
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enum: CEIE
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- name: MODE
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description: DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing.
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bit_offset: 16
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@ -532,15 +524,6 @@ enum/CAECIF:
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- name: Clear
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description: Clear the CAEIF flag in the ISR register
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value: 1
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enum/CAEIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: CAE interrupt disabled
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value: 0
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- name: Enabled
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description: CAE interrupt enabled
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value: 1
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enum/CCEIF:
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bit_size: 1
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variants:
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@ -553,30 +536,12 @@ enum/CCTCIF:
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- name: Clear
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description: Clear the CTCIF flag in the ISR register
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value: 1
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enum/CEIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: CE interrupt disabled
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value: 0
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- name: Enabled
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description: CE interrupt enabled
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value: 1
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enum/CR_START:
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bit_size: 1
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variants:
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- name: Start
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description: Launch the DMA2D
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value: 1
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enum/CTCIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: CTC interrupt disabled
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value: 0
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- name: Enabled
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description: CTC interrupt enabled
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value: 1
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enum/CTCIF:
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bit_size: 1
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variants:
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@ -595,15 +560,6 @@ enum/CTWIF:
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- name: Clear
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description: Clear the TWIF flag in the ISR register
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value: 1
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enum/EN:
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bit_size: 1
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variants:
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- name: Disabled
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description: Disabled AHB/AXI dead-time functionality
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value: 0
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- name: Enabled
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description: Enabled AHB/AXI dead-time functionality
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value: 1
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enum/FGPFCCR_AI:
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bit_size: 1
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variants:
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@ -748,39 +704,3 @@ enum/SB:
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- name: SwapBytes
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description: Bytes are swapped two by two
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value: 1
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enum/SUSP:
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bit_size: 1
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variants:
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- name: NotSuspended
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description: Transfer not suspended
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value: 0
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- name: Suspended
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description: Transfer suspended
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value: 1
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enum/TCIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: TC interrupt disabled
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value: 0
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- name: Enabled
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description: TC interrupt enabled
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value: 1
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enum/TEIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: TE interrupt disabled
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value: 0
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- name: Enabled
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description: TE interrupt enabled
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value: 1
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enum/TWIE:
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bit_size: 1
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variants:
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- name: Disabled
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description: TW interrupt disabled
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value: 0
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- name: Enabled
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description: TW interrupt enabled
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value: 1
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@ -82,20 +82,17 @@ fieldset/CR:
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bit_size: 2
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enum: DIR
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- name: CIRC
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description: Circular mode
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description: Circular mode enabled
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bit_offset: 8
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bit_size: 1
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enum: CIRC
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- name: PINC
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description: Peripheral increment mode
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description: Peripheral increment mode enabled
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bit_offset: 9
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bit_size: 1
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enum: INC
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- name: MINC
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description: Memory increment mode
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description: Memory increment mode enabled
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bit_offset: 10
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bit_size: 1
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enum: INC
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- name: PSIZE
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description: Peripheral data size
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bit_offset: 11
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@ -117,10 +114,9 @@ fieldset/CR:
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bit_size: 2
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enum: PL
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- name: DBM
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description: Double buffer mode
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description: Double buffer mode enabled
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bit_offset: 18
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bit_size: 1
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enum: DBM
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- name: CT
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description: Current target (only in double buffer mode)
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bit_offset: 19
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@ -237,15 +233,6 @@ enum/BURST:
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- name: INCR16
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description: Incremental burst of 16 beats
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value: 3
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enum/CIRC:
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bit_size: 1
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variants:
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- name: Disabled
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description: Circular mode disabled
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value: 0
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- name: Enabled
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description: Circular mode enabled
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value: 1
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enum/CT:
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bit_size: 1
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variants:
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@ -255,15 +242,6 @@ enum/CT:
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- name: Memory1
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description: The current target memory is Memory 1
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value: 1
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enum/DBM:
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bit_size: 1
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variants:
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- name: Disabled
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description: No buffer switching at the end of transfer
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value: 0
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- name: Enabled
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description: Memory target switched at the end of the DMA transfer
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value: 1
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enum/DIR:
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bit_size: 2
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variants:
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@ -321,15 +299,6 @@ enum/FTH:
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- name: Full
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description: Full FIFO
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value: 3
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enum/INC:
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bit_size: 1
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variants:
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- name: Fixed
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description: Address pointer is fixed
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value: 0
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- name: Incremented
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description: Address pointer is incremented after each data transfer
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value: 1
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enum/PFCTRL:
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bit_size: 1
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variants:
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@ -82,20 +82,17 @@ fieldset/CR:
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bit_size: 2
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enum: DIR
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- name: CIRC
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description: Circular mode
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description: Circular mode enabled
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bit_offset: 8
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bit_size: 1
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enum: CIRC
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- name: PINC
|
||||
description: Peripheral increment mode
|
||||
description: Peripheral increment mode enabled
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: MINC
|
||||
description: Memory increment mode
|
||||
description: Memory increment mode enabled
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: INC
|
||||
- name: PSIZE
|
||||
description: Peripheral data size
|
||||
bit_offset: 11
|
||||
@ -117,10 +114,9 @@ fieldset/CR:
|
||||
bit_size: 2
|
||||
enum: PL
|
||||
- name: DBM
|
||||
description: Double buffer mode
|
||||
description: Double buffer mode enabled
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
enum: DBM
|
||||
- name: CT
|
||||
description: Current target (only in double buffer mode)
|
||||
bit_offset: 19
|
||||
@ -237,15 +233,6 @@ enum/BURST:
|
||||
- name: INCR16
|
||||
description: Incremental burst of 16 beats
|
||||
value: 3
|
||||
enum/CIRC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Circular mode disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Circular mode enabled
|
||||
value: 1
|
||||
enum/CT:
|
||||
bit_size: 1
|
||||
variants:
|
||||
@ -255,15 +242,6 @@ enum/CT:
|
||||
- name: Memory1
|
||||
description: The current target memory is Memory 1
|
||||
value: 1
|
||||
enum/DBM:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: No buffer switching at the end of transfer
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Memory target switched at the end of the DMA transfer
|
||||
value: 1
|
||||
enum/DIR:
|
||||
bit_size: 2
|
||||
variants:
|
||||
@ -321,15 +299,6 @@ enum/FTH:
|
||||
- name: Full
|
||||
description: Full FIFO
|
||||
value: 3
|
||||
enum/INC:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Fixed
|
||||
description: Address pointer is fixed
|
||||
value: 0
|
||||
- name: Incremented
|
||||
description: Address pointer is incremented after each data transfer
|
||||
value: 1
|
||||
enum/PFCTRL:
|
||||
bit_size: 1
|
||||
variants:
|
||||
|
Loading…
x
Reference in New Issue
Block a user