181 lines
3.9 KiB
YAML
181 lines
3.9 KiB
YAML
block/CH:
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description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
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items:
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- name: CR
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description: DMA channel configuration register (DMA_CCR)
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byte_offset: 0
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fieldset: CR
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- name: NDTR
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description: DMA channel 1 number of data register
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byte_offset: 4
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fieldset: NDTR
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- name: PAR
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description: DMA channel 1 peripheral address register
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byte_offset: 8
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- name: MAR
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description: DMA channel 1 memory address register
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byte_offset: 12
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block/DMA:
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description: DMA controller
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items:
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- name: ISR
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description: DMA interrupt status register (DMA_ISR)
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byte_offset: 0
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access: Read
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fieldset: ISR
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- name: IFCR
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description: DMA interrupt flag clear register (DMA_IFCR)
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byte_offset: 4
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access: Write
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fieldset: ISR
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- name: CH
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description: 'Channel cluster: CCR?, CNDTR?, CPAR?, and CMAR? registers'
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array:
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len: 8
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stride: 20
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byte_offset: 8
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block: CH
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- name: CSELR
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description: channel selection register
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byte_offset: 168
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fieldset: CSELR
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fieldset/CR:
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description: DMA channel configuration register (DMA_CCR)
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fields:
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- name: EN
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description: Channel enable
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bit_offset: 0
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bit_size: 1
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- name: TCIE
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description: Transfer complete interrupt enable
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bit_offset: 1
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bit_size: 1
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- name: HTIE
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description: Half Transfer interrupt enable
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bit_offset: 2
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bit_size: 1
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- name: TEIE
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description: Transfer error interrupt enable
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bit_offset: 3
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bit_size: 1
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- name: DIR
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description: Data transfer direction
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bit_offset: 4
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bit_size: 1
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enum: DIR
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- name: CIRC
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description: Circular mode enabled
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bit_offset: 5
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bit_size: 1
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- name: PINC
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description: Peripheral increment mode enabled
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bit_offset: 6
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bit_size: 1
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- name: MINC
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description: Memory increment mode enabled
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bit_offset: 7
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bit_size: 1
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- name: PSIZE
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description: Peripheral size
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bit_offset: 8
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bit_size: 2
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enum: SIZE
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- name: MSIZE
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description: Memory size
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bit_offset: 10
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bit_size: 2
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enum: SIZE
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- name: PL
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description: Channel Priority level
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bit_offset: 12
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bit_size: 2
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enum: PL
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- name: MEM2MEM
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description: Memory to memory mode enabled
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bit_offset: 14
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bit_size: 1
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fieldset/CSELR:
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description: channel selection register
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fields:
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- name: CS
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description: DMA channel selection
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bit_offset: 0
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bit_size: 4
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array:
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len: 8
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stride: 4
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fieldset/ISR:
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description: DMA interrupt status register (DMA_ISR)
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fields:
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- name: GIF
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description: Channel 1 Global interrupt flag
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bit_offset: 0
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bit_size: 1
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array:
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len: 8
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stride: 4
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- name: TCIF
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description: Channel 1 Transfer Complete flag
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bit_offset: 1
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bit_size: 1
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array:
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len: 8
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stride: 4
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- name: HTIF
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description: Channel 1 Half Transfer Complete flag
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bit_offset: 2
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bit_size: 1
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array:
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len: 8
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stride: 4
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- name: TEIF
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description: Channel 1 Transfer Error flag
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bit_offset: 3
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bit_size: 1
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array:
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len: 8
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stride: 4
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fieldset/NDTR:
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description: DMA channel 1 number of data register
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fields:
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- name: NDT
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description: Number of data to transfer
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bit_offset: 0
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bit_size: 16
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enum/DIR:
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bit_size: 1
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variants:
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- name: FromPeripheral
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description: Read from peripheral
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value: 0
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- name: FromMemory
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description: Read from memory
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value: 1
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enum/PL:
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bit_size: 2
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variants:
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- name: Low
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description: Low priority
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value: 0
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- name: Medium
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description: Medium priority
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value: 1
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- name: High
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description: High priority
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value: 2
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- name: VeryHigh
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description: Very high priority
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value: 3
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enum/SIZE:
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bit_size: 2
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variants:
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- name: Bits8
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description: 8-bit size
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value: 0
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- name: Bits16
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description: 16-bit size
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value: 1
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- name: Bits32
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description: 32-bit size
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value: 2
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