rcc: more accurate f3 versions.

data/registers/rcc_f37.yaml

@@ -495,11 +495,11 @@ fieldset/CFGR:
     enum: ADCPRE
   - name: PLLSRC
     description: PLL entry clock source
-    bit_offset: 15
+    bit_offset: 16
-    bit_size: 2
+    bit_size: 1
     enum: PLLSRC
   - name: PLLXTPRE
-    description: HSE divider for PLL entry
+    description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products."
     bit_offset: 17
     bit_size: 1
     enum: PLLXTPRE
@@ -528,16 +528,6 @@ fieldset/CFGR:
     bit_offset: 27
     bit_size: 5
     enum: SDPRE
-  - name: MCOPRE
-    description: Microcontroller Clock Output Prescaler
-    bit_offset: 28
-    bit_size: 3
-    enum: MCOPRE
-  - name: PLLMCODIV
-    description: Do not divide PLL to MCO
-    bit_offset: 31
-    bit_size: 1
-    enum: PLLMCODIV
 fieldset/CFGR2:
   description: Clock configuration register 2
   fields:
@@ -941,33 +931,6 @@ enum/LSEDRV:
   - name: High
     description: High driving capability
     value: 3
-enum/MCOPRE:
-  bit_size: 3
-  variants:
-  - name: Div1
-    description: MCO is divided by 1
-    value: 0
-  - name: Div2
-    description: MCO is divided by 2
-    value: 1
-  - name: Div4
-    description: MCO is divided by 4
-    value: 2
-  - name: Div8
-    description: MCO is divided by 8
-    value: 3
-  - name: Div16
-    description: MCO is divided by 16
-    value: 4
-  - name: Div32
-    description: MCO is divided by 32
-    value: 5
-  - name: Div64
-    description: MCO is divided by 64
-    value: 6
-  - name: Div128
-    description: MCO is divided by 128
-    value: 7
 enum/MCOSEL:
   bit_size: 3
   variants:
@@ -989,18 +952,9 @@ enum/MCOSEL:
   - name: HSE
     description: External 4-32 MHz (HSE) oscillator clock selected
     value: 6
-  - name: PLL
+  - name: PLL_DIV_2
-    description: PLL clock selected (divided by 1 or 2, depending en PLLMCODIV)
+    description: PLL clock divided by 2
     value: 7
-enum/PLLMCODIV:
-  bit_size: 1
-  variants:
-  - name: Div2
-    description: PLL is divided by 2 for MCO
-    value: 0
-  - name: Div1
-    description: PLL is not divided for MCO
-    value: 1
 enum/PLLMUL:
   bit_size: 4
   variants:
@@ -1050,17 +1004,14 @@ enum/PLLMUL:
     description: PLL input clock x16
     value: 14
 enum/PLLSRC:
-  bit_size: 2
+  bit_size: 1
   variants:
   - name: HSI_Div2
     description: HSI divided by 2 selected as PLL input clock
     value: 0
-  - name: HSI_Div_PREDIV
-    description: HSI divided by PREDIV selected as PLL input clock
-    value: 1
   - name: HSE_Div_PREDIV
     description: HSE divided by PREDIV selected as PLL input clock
-    value: 2
+    value: 1
 enum/PLLXTPRE:
   bit_size: 1
   variants:

data/registers/rcc_f3v3.yaml

@@ -523,7 +523,7 @@ fieldset/CFGR:
     bit_size: 2
     enum: PLLSRC
   - name: PLLXTPRE
-    description: HSE divider for PLL entry
+    description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products."
     bit_offset: 17
     bit_size: 1
     enum: PLLXTPRE
@@ -547,11 +547,6 @@ fieldset/CFGR:
     bit_offset: 24
     bit_size: 3
     enum: MCOSEL
-  - name: SDPRE
-    description: SDADC prescaler
-    bit_offset: 27
-    bit_size: 5
-    enum: SDPRE
   - name: MCOPRE
     description: Microcontroller Clock Output Prescaler
     bit_offset: 28
@@ -1178,57 +1173,6 @@ enum/RTCSEL:
   - name: HSE
     description: HSE oscillator clock divided by a prescaler used as RTC clock
     value: 3
-enum/SDPRE:
-  bit_size: 5
-  variants:
-  - name: Div2
-    description: SYSCLK divided by 2
-    value: 0
-  - name: Div4
-    description: SYSCLK divided by 4
-    value: 17
-  - name: Div6
-    description: SYSCLK divided by 6
-    value: 18
-  - name: Div8
-    description: SYSCLK divided by 8
-    value: 19
-  - name: Div10
-    description: SYSCLK divided by 10
-    value: 20
-  - name: Div12
-    description: SYSCLK divided by 12
-    value: 21
-  - name: Div14
-    description: SYSCLK divided by 14
-    value: 22
-  - name: Div16
-    description: SYSCLK divided by 16
-    value: 23
-  - name: Div20
-    description: SYSCLK divided by 20
-    value: 24
-  - name: Div24
-    description: SYSCLK divided by 24
-    value: 25
-  - name: Div28
-    description: SYSCLK divided by 28
-    value: 26
-  - name: Div32
-    description: SYSCLK divided by 32
-    value: 27
-  - name: Div36
-    description: SYSCLK divided by 36
-    value: 28
-  - name: Div40
-    description: SYSCLK divided by 40
-    value: 29
-  - name: Div44
-    description: SYSCLK divided by 44
-    value: 30
-  - name: Div48
-    description: SYSCLK divided by 48
-    value: 31
 enum/SW:
   bit_size: 2
   variants:

stm32-data-gen/src/chips.rs

@@ -301,8 +301,12 @@ impl PeriMatcher {
             ("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")),
             ("STM32F10[57].*:RCC:.*", ("rcc", "f1cl", "RCC")),
             ("STM32F2.*:RCC:.*", ("rcc", "f2", "RCC")),
-            ("STM32F37.*:RCC:.*", ("rcc", "f3_v2", "RCC")),
+            ("STM32F37.*:RCC:.*", ("rcc", "f37", "RCC")),
-            ("STM32F3.*:RCC:.*", ("rcc", "f3", "RCC")),
+            ("STM32F30[23].[BC].*:RCC:.*", ("rcc", "f3v1", "RCC")),
+            ("STM32F358.C.*:RCC:.*", ("rcc", "f3v1", "RCC")),
+            ("STM32F30[23].[DE].*:RCC:.*", ("rcc", "f3v3", "RCC")),
+            ("STM32F398.E.*:RCC:.*", ("rcc", "f3v3", "RCC")),
+            ("STM32F3.*:RCC:.*", ("rcc", "f3v2", "RCC")),
             ("STM32F410.*:RCC:.*", ("rcc", "f410", "RCC")),
             ("STM32F4.*:RCC:.*", ("rcc", "f4", "RCC")),
             ("STM32F7.*:RCC:.*", ("rcc", "f7", "RCC")),