From 8ae5bb5fe696a7e61fb41b8b797372aed8103a82 Mon Sep 17 00:00:00 2001 From: Dario Nieuwenhuis Date: Mon, 12 Feb 2024 02:03:25 +0100 Subject: [PATCH] rcc: more accurate f3 versions. --- .../{rcc_f3_v2.yaml => rcc_f37.yaml} | 63 +- data/registers/rcc_f3v1.yaml | 1175 ++++++++++++++++ data/registers/rcc_f3v2.yaml | 1217 +++++++++++++++++ data/registers/{rcc_f3.yaml => rcc_f3v3.yaml} | 58 +- stm32-data-gen/src/chips.rs | 8 +- 5 files changed, 2406 insertions(+), 115 deletions(-) rename data/registers/{rcc_f3_v2.yaml => rcc_f37.yaml} (95%) create mode 100644 data/registers/rcc_f3v1.yaml create mode 100644 data/registers/rcc_f3v2.yaml rename data/registers/{rcc_f3.yaml => rcc_f3v3.yaml} (95%) diff --git a/data/registers/rcc_f3_v2.yaml b/data/registers/rcc_f37.yaml similarity index 95% rename from data/registers/rcc_f3_v2.yaml rename to data/registers/rcc_f37.yaml index f6d0105..dc8b054 100644 --- a/data/registers/rcc_f3_v2.yaml +++ b/data/registers/rcc_f37.yaml @@ -495,11 +495,11 @@ fieldset/CFGR: enum: ADCPRE - name: PLLSRC description: PLL entry clock source - bit_offset: 15 - bit_size: 2 + bit_offset: 16 + bit_size: 1 enum: PLLSRC - name: PLLXTPRE - description: HSE divider for PLL entry + description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." bit_offset: 17 bit_size: 1 enum: PLLXTPRE @@ -528,16 +528,6 @@ fieldset/CFGR: bit_offset: 27 bit_size: 5 enum: SDPRE - - name: MCOPRE - description: Microcontroller Clock Output Prescaler - bit_offset: 28 - bit_size: 3 - enum: MCOPRE - - name: PLLMCODIV - description: Do not divide PLL to MCO - bit_offset: 31 - bit_size: 1 - enum: PLLMCODIV fieldset/CFGR2: description: Clock configuration register 2 fields: @@ -941,33 +931,6 @@ enum/LSEDRV: - name: High description: High driving capability value: 3 -enum/MCOPRE: - bit_size: 3 - variants: - - name: Div1 - description: MCO is divided by 1 - value: 0 - - name: Div2 - description: MCO is divided by 2 - value: 1 - - name: Div4 - description: MCO is divided by 4 - value: 2 - - name: Div8 - description: MCO is divided by 8 - value: 3 - - name: Div16 - description: MCO is divided by 16 - value: 4 - - name: Div32 - description: MCO is divided by 32 - value: 5 - - name: Div64 - description: MCO is divided by 64 - value: 6 - - name: Div128 - description: MCO is divided by 128 - value: 7 enum/MCOSEL: bit_size: 3 variants: @@ -989,18 +952,9 @@ enum/MCOSEL: - name: HSE description: External 4-32 MHz (HSE) oscillator clock selected value: 6 - - name: PLL - description: PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) + - name: PLL_DIV_2 + description: PLL clock divided by 2 value: 7 -enum/PLLMCODIV: - bit_size: 1 - variants: - - name: Div2 - description: PLL is divided by 2 for MCO - value: 0 - - name: Div1 - description: PLL is not divided for MCO - value: 1 enum/PLLMUL: bit_size: 4 variants: @@ -1050,17 +1004,14 @@ enum/PLLMUL: description: PLL input clock x16 value: 14 enum/PLLSRC: - bit_size: 2 + bit_size: 1 variants: - name: HSI_Div2 description: HSI divided by 2 selected as PLL input clock value: 0 - - name: HSI_Div_PREDIV - description: HSI divided by PREDIV selected as PLL input clock - value: 1 - name: HSE_Div_PREDIV description: HSE divided by PREDIV selected as PLL input clock - value: 2 + value: 1 enum/PLLXTPRE: bit_size: 1 variants: diff --git a/data/registers/rcc_f3v1.yaml b/data/registers/rcc_f3v1.yaml new file mode 100644 index 0000000..32a8076 --- /dev/null +++ b/data/registers/rcc_f3v1.yaml @@ -0,0 +1,1175 @@ +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: FMCEN + description: FMC clock enable + bit_offset: 5 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 16 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 21 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 23 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 + - name: ADC12EN + description: ADC1 and ADC2 clock enable + bit_offset: 28 + bit_size: 1 + - name: ADC34EN + description: ADC3 and ADC4 clock enable + bit_offset: 29 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: FMCRST + description: FMC reset + bit_offset: 5 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 16 + bit_size: 1 + - name: GPIOARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 21 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 23 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 + - name: ADC12RST + description: ADC1 and ADC2 reset + bit_offset: 28 + bit_size: 1 + - name: ADC34RST + description: ADC3 and ADC4 reset + bit_offset: 29 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: DAC2EN + description: DAC2 interface clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 14 reset + bit_offset: 2 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 30 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 Timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI4EN + description: SPI4 clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM19EN + description: TIM19 timer clock enable + bit_offset: 19 + bit_size: 1 + - name: TIM20EN + description: TIM20 timer clock enable + bit_offset: 20 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 + - name: HRTIM1EN + description: High Resolution Timer 1 clock enable + bit_offset: 29 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: SPI4RST + description: SPI4 reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM19RST + description: TIM19 timer reset + bit_offset: 19 + bit_size: 1 + - name: TIM20RST + description: TIM20 timer reset + bit_offset: 20 + bit_size: 1 + - name: DBGMCURST + description: Debug MCU reset + bit_offset: 22 + bit_size: 1 + - name: HRTIM1RST + description: High Resolution Timer1 reset + bit_offset: 29 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: I2SSRC + description: I2S external clock source selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCOSEL + - name: MCOF + description: Microcontroller Clock Output Flag. Set and reset by hardware. It is reset by hardware when MCO field is written with a new value. It is set by hardware when the switch to the new MCO source is effective. + bit_offset: 28 + bit_size: 1 +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV + - name: ADC12PRES + description: ADC1 and ADC2 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC1PRES + description: ADC1 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC34PRES + description: ADC3 and ADC4 prescaler + bit_offset: 9 + bit_size: 5 + enum: ADCPRES +fieldset/CFGR3: + description: Clock configuration register 3 + fields: + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: I2C2SW + description: I2C2 clock source selection + bit_offset: 5 + bit_size: 1 + enum: ICSW + - name: CECSW + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSW + - name: I2C3SW + description: I2C3 clock source selection + bit_offset: 6 + bit_size: 1 + enum: ICSW + - name: TIM1SW + description: Timer1 clock source selection + bit_offset: 8 + bit_size: 1 + enum: TIMSW + - name: TIM8SW + description: Timer8 clock source selection + bit_offset: 9 + bit_size: 1 + enum: TIMSW + - name: TIM15SW + description: Timer15 clock source selection + bit_offset: 10 + bit_size: 1 + enum: TIMSW + - name: TIM16SW + description: Timer16 clock source selection + bit_offset: 11 + bit_size: 1 + enum: TIMSW + - name: HRTIM1SW + description: Hrtim1 clock source selection + bit_offset: 12 + bit_size: 1 + enum: TIMSW + - name: TIM17SW + description: Timer17 clock source selection + bit_offset: 13 + bit_size: 1 + enum: TIMSW + - name: TIM20SW + description: Timer20 clock source selection + bit_offset: 15 + bit_size: 1 + enum: TIMSW + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source selection + bit_offset: 18 + bit_size: 2 + enum: USARTSW + - name: UART4SW + description: UART4 clock source selection + bit_offset: 20 + bit_size: 2 + enum: USARTSW + - name: UART5SW + description: UART5 clock source selection + bit_offset: 22 + bit_size: 2 + enum: USARTSW + - name: TIM2SW + description: Timer2 clock source selection + bit_offset: 24 + bit_size: 1 + enum: TIMSW + - name: TIM34SW + description: Timer34 clock source selection + bit_offset: 25 + bit_size: 1 + enum: TIMSW +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: V18PWRRSTF + description: Reset flag of the 1.8 V domain + bit_offset: 23 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK divided by 2 + value: 0 + - name: Div4 + description: PCLK divided by 4 + value: 1 + - name: Div6 + description: PCLK divided by 6 + value: 2 + - name: Div8 + description: PCLK divided by 8 + value: 3 +enum/ADCPRES: + bit_size: 5 + variants: + - name: Div1 + description: PLL clock not divided + value: 16 + - name: Div2 + description: PLL clock divided by 2 + value: 17 + - name: Div4 + description: PLL clock divided by 4 + value: 18 + - name: Div6 + description: PLL clock divided by 6 + value: 19 + - name: Div8 + description: PLL clock divided by 8 + value: 20 + - name: Div10 + description: PLL clock divided by 10 + value: 21 + - name: Div12 + description: PLL clock divided by 12 + value: 22 + - name: Div16 + description: PLL clock divided by 16 + value: 23 + - name: Div32 + description: PLL clock divided by 32 + value: 24 + - name: Div64 + description: PLL clock divided by 64 + value: 25 + - name: Div128 + description: PLL clock divided by 128 + value: 26 + - name: Div256 + description: PLL clock divided by 256 + value: 27 +enum/CECSW: + bit_size: 1 + variants: + - name: HSI_DIV_244 + description: HSI clock divided by 244 selected as CEC clock source + value: 0 + - name: LSE + description: LSE clock selected as CEC clock source + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/ICSW: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYS + description: SYSCLK clock selected as I2C clock source + value: 1 +enum/ISSRC: + bit_size: 1 + variants: + - name: SYS + description: System clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low driving capability + value: 0 + - name: MediumHigh + description: Medium high driving capability + value: 1 + - name: MediumLow + description: Medium low driving capability + value: 2 + - name: High + description: High driving capability + value: 3 +enum/MCOSEL: + bit_size: 3 + variants: + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYS + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL_DIV_2 + description: PLL clock divided by 2 + value: 7 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RTCSEL: + bit_size: 2 + variants: + - name: DISABLE + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL1_P + description: PLL used as system clock + value: 2 +enum/TIMSW: + bit_size: 1 + variants: + - name: PCLK2_TIM + description: PCLK2 clock (doubled frequency when prescaled) + value: 0 + - name: PLL1_P + description: PLL vco output (running up to 144 MHz) + value: 1 +enum/USARTSW: + bit_size: 2 + variants: + - name: PCLK1 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 +enum/USBPRE: + bit_size: 1 + variants: + - name: Div1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: Div1 + description: PLL clock is not divided + value: 1 diff --git a/data/registers/rcc_f3v2.yaml b/data/registers/rcc_f3v2.yaml new file mode 100644 index 0000000..68aecd4 --- /dev/null +++ b/data/registers/rcc_f3v2.yaml @@ -0,0 +1,1217 @@ +block/RCC: + description: Reset and clock control + items: + - name: CR + description: Clock control register + byte_offset: 0 + fieldset: CR + - name: CFGR + description: Clock configuration register (RCC_CFGR) + byte_offset: 4 + fieldset: CFGR + - name: CIR + description: Clock interrupt register (RCC_CIR) + byte_offset: 8 + fieldset: CIR + - name: APB2RSTR + description: APB2 peripheral reset register (RCC_APB2RSTR) + byte_offset: 12 + fieldset: APB2RSTR + - name: APB1RSTR + description: APB1 peripheral reset register (RCC_APB1RSTR) + byte_offset: 16 + fieldset: APB1RSTR + - name: AHBENR + description: AHB Peripheral Clock enable register (RCC_AHBENR) + byte_offset: 20 + fieldset: AHBENR + - name: APB2ENR + description: APB2 peripheral clock enable register (RCC_APB2ENR) + byte_offset: 24 + fieldset: APB2ENR + - name: APB1ENR + description: APB1 peripheral clock enable register (RCC_APB1ENR) + byte_offset: 28 + fieldset: APB1ENR + - name: BDCR + description: Backup domain control register (RCC_BDCR) + byte_offset: 32 + fieldset: BDCR + - name: CSR + description: Control/status register (RCC_CSR) + byte_offset: 36 + fieldset: CSR + - name: AHBRSTR + description: AHB peripheral reset register + byte_offset: 40 + fieldset: AHBRSTR + - name: CFGR2 + description: Clock configuration register 2 + byte_offset: 44 + fieldset: CFGR2 + - name: CFGR3 + description: Clock configuration register 3 + byte_offset: 48 + fieldset: CFGR3 +fieldset/AHBENR: + description: AHB Peripheral Clock enable register (RCC_AHBENR) + fields: + - name: DMA1EN + description: DMA1 clock enable + bit_offset: 0 + bit_size: 1 + - name: DMA2EN + description: DMA2 clock enable + bit_offset: 1 + bit_size: 1 + - name: SRAMEN + description: SRAM interface clock enable + bit_offset: 2 + bit_size: 1 + - name: FLASHEN + description: FLASH clock enable + bit_offset: 4 + bit_size: 1 + - name: FMCEN + description: FMC clock enable + bit_offset: 5 + bit_size: 1 + - name: CRCEN + description: CRC clock enable + bit_offset: 6 + bit_size: 1 + - name: GPIOHEN + description: IO port H clock enable + bit_offset: 16 + bit_size: 1 + - name: GPIOAEN + description: I/O port A clock enable + bit_offset: 17 + bit_size: 1 + - name: GPIOBEN + description: I/O port B clock enable + bit_offset: 18 + bit_size: 1 + - name: GPIOCEN + description: I/O port C clock enable + bit_offset: 19 + bit_size: 1 + - name: GPIODEN + description: I/O port D clock enable + bit_offset: 20 + bit_size: 1 + - name: GPIOEEN + description: I/O port E clock enable + bit_offset: 21 + bit_size: 1 + - name: GPIOFEN + description: I/O port F clock enable + bit_offset: 22 + bit_size: 1 + - name: GPIOGEN + description: IO port G clock enable + bit_offset: 23 + bit_size: 1 + - name: TSCEN + description: Touch sensing controller clock enable + bit_offset: 24 + bit_size: 1 + - name: ADC12EN + description: ADC1 and ADC2 clock enable + bit_offset: 28 + bit_size: 1 + - name: ADC34EN + description: ADC3 and ADC4 clock enable + bit_offset: 29 + bit_size: 1 +fieldset/AHBRSTR: + description: AHB peripheral reset register + fields: + - name: FMCRST + description: FMC reset + bit_offset: 5 + bit_size: 1 + - name: GPIOHRST + description: IO port H reset + bit_offset: 16 + bit_size: 1 + - name: GPIOARST + description: I/O port A reset + bit_offset: 17 + bit_size: 1 + - name: GPIOBRST + description: I/O port B reset + bit_offset: 18 + bit_size: 1 + - name: GPIOCRST + description: I/O port C reset + bit_offset: 19 + bit_size: 1 + - name: GPIODRST + description: I/O port D reset + bit_offset: 20 + bit_size: 1 + - name: GPIOERST + description: I/O port E reset + bit_offset: 21 + bit_size: 1 + - name: GPIOFRST + description: I/O port F reset + bit_offset: 22 + bit_size: 1 + - name: GPIOGRST + description: IO port G reset + bit_offset: 23 + bit_size: 1 + - name: TSCRST + description: Touch sensing controller reset + bit_offset: 24 + bit_size: 1 + - name: ADC12RST + description: ADC1 and ADC2 reset + bit_offset: 28 + bit_size: 1 + - name: ADC34RST + description: ADC3 and ADC4 reset + bit_offset: 29 + bit_size: 1 +fieldset/APB1ENR: + description: APB1 peripheral clock enable register (RCC_APB1ENR) + fields: + - name: TIM2EN + description: Timer 2 clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM3EN + description: Timer 3 clock enable + bit_offset: 1 + bit_size: 1 + - name: TIM4EN + description: Timer 4 clock enable + bit_offset: 2 + bit_size: 1 + - name: TIM6EN + description: Timer 6 clock enable + bit_offset: 4 + bit_size: 1 + - name: TIM7EN + description: Timer 7 clock enable + bit_offset: 5 + bit_size: 1 + - name: WWDGEN + description: Window watchdog clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI2EN + description: SPI 2 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI3EN + description: SPI 3 clock enable + bit_offset: 15 + bit_size: 1 + - name: USART2EN + description: USART 2 clock enable + bit_offset: 17 + bit_size: 1 + - name: USART3EN + description: USART 3 clock enable + bit_offset: 18 + bit_size: 1 + - name: UART4EN + description: UART4 clock enable + bit_offset: 19 + bit_size: 1 + - name: UART5EN + description: UART5 clock enable + bit_offset: 20 + bit_size: 1 + - name: I2C1EN + description: I2C 1 clock enable + bit_offset: 21 + bit_size: 1 + - name: I2C2EN + description: I2C 2 clock enable + bit_offset: 22 + bit_size: 1 + - name: USBEN + description: USB clock enable + bit_offset: 23 + bit_size: 1 + - name: CANEN + description: CAN clock enable + bit_offset: 25 + bit_size: 1 + - name: DAC2EN + description: DAC2 interface clock enable + bit_offset: 26 + bit_size: 1 + - name: PWREN + description: Power interface clock enable + bit_offset: 28 + bit_size: 1 + - name: DACEN + description: DAC interface clock enable + bit_offset: 29 + bit_size: 1 + - name: I2C3EN + description: I2C3 clock enable + bit_offset: 30 + bit_size: 1 +fieldset/APB1RSTR: + description: APB1 peripheral reset register (RCC_APB1RSTR) + fields: + - name: TIM2RST + description: Timer 2 reset + bit_offset: 0 + bit_size: 1 + - name: TIM3RST + description: Timer 3 reset + bit_offset: 1 + bit_size: 1 + - name: TIM4RST + description: Timer 14 reset + bit_offset: 2 + bit_size: 1 + - name: TIM6RST + description: Timer 6 reset + bit_offset: 4 + bit_size: 1 + - name: TIM7RST + description: Timer 7 reset + bit_offset: 5 + bit_size: 1 + - name: WWDGRST + description: Window watchdog reset + bit_offset: 11 + bit_size: 1 + - name: SPI2RST + description: SPI2 reset + bit_offset: 14 + bit_size: 1 + - name: SPI3RST + description: SPI3 reset + bit_offset: 15 + bit_size: 1 + - name: USART2RST + description: USART 2 reset + bit_offset: 17 + bit_size: 1 + - name: USART3RST + description: USART3 reset + bit_offset: 18 + bit_size: 1 + - name: UART4RST + description: UART 4 reset + bit_offset: 19 + bit_size: 1 + - name: UART5RST + description: UART 5 reset + bit_offset: 20 + bit_size: 1 + - name: I2C1RST + description: I2C1 reset + bit_offset: 21 + bit_size: 1 + - name: I2C2RST + description: I2C2 reset + bit_offset: 22 + bit_size: 1 + - name: USBRST + description: USB reset + bit_offset: 23 + bit_size: 1 + - name: CANRST + description: CAN reset + bit_offset: 25 + bit_size: 1 + - name: DAC2RST + description: DAC2 interface reset + bit_offset: 26 + bit_size: 1 + - name: PWRRST + description: Power interface reset + bit_offset: 28 + bit_size: 1 + - name: DACRST + description: DAC interface reset + bit_offset: 29 + bit_size: 1 + - name: I2C3RST + description: I2C3 reset + bit_offset: 30 + bit_size: 1 +fieldset/APB2ENR: + description: APB2 peripheral clock enable register (RCC_APB2ENR) + fields: + - name: SYSCFGEN + description: SYSCFG clock enable + bit_offset: 0 + bit_size: 1 + - name: TIM1EN + description: TIM1 Timer clock enable + bit_offset: 11 + bit_size: 1 + - name: SPI1EN + description: SPI 1 clock enable + bit_offset: 12 + bit_size: 1 + - name: TIM8EN + description: TIM8 Timer clock enable + bit_offset: 13 + bit_size: 1 + - name: USART1EN + description: USART1 clock enable + bit_offset: 14 + bit_size: 1 + - name: SPI4EN + description: SPI4 clock enable + bit_offset: 15 + bit_size: 1 + - name: TIM15EN + description: TIM15 timer clock enable + bit_offset: 16 + bit_size: 1 + - name: TIM16EN + description: TIM16 timer clock enable + bit_offset: 17 + bit_size: 1 + - name: TIM17EN + description: TIM17 timer clock enable + bit_offset: 18 + bit_size: 1 + - name: TIM19EN + description: TIM19 timer clock enable + bit_offset: 19 + bit_size: 1 + - name: TIM20EN + description: TIM20 timer clock enable + bit_offset: 20 + bit_size: 1 + - name: DBGMCUEN + description: MCU debug module clock enable + bit_offset: 22 + bit_size: 1 + - name: HRTIM1EN + description: High Resolution Timer 1 clock enable + bit_offset: 29 + bit_size: 1 +fieldset/APB2RSTR: + description: APB2 peripheral reset register (RCC_APB2RSTR) + fields: + - name: SYSCFGRST + description: SYSCFG and COMP reset + bit_offset: 0 + bit_size: 1 + - name: TIM1RST + description: TIM1 timer reset + bit_offset: 11 + bit_size: 1 + - name: SPI1RST + description: SPI 1 reset + bit_offset: 12 + bit_size: 1 + - name: TIM8RST + description: TIM8 timer reset + bit_offset: 13 + bit_size: 1 + - name: USART1RST + description: USART1 reset + bit_offset: 14 + bit_size: 1 + - name: SPI4RST + description: SPI4 reset + bit_offset: 15 + bit_size: 1 + - name: TIM15RST + description: TIM15 timer reset + bit_offset: 16 + bit_size: 1 + - name: TIM16RST + description: TIM16 timer reset + bit_offset: 17 + bit_size: 1 + - name: TIM17RST + description: TIM17 timer reset + bit_offset: 18 + bit_size: 1 + - name: TIM19RST + description: TIM19 timer reset + bit_offset: 19 + bit_size: 1 + - name: TIM20RST + description: TIM20 timer reset + bit_offset: 20 + bit_size: 1 + - name: DBGMCURST + description: Debug MCU reset + bit_offset: 22 + bit_size: 1 + - name: HRTIM1RST + description: High Resolution Timer1 reset + bit_offset: 29 + bit_size: 1 +fieldset/BDCR: + description: Backup domain control register (RCC_BDCR) + fields: + - name: LSEON + description: External Low Speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSERDY + description: External Low Speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: LSEBYP + description: External Low Speed oscillator bypass + bit_offset: 2 + bit_size: 1 + - name: LSEDRV + description: LSE oscillator drive capability + bit_offset: 3 + bit_size: 2 + enum: LSEDRV + - name: RTCSEL + description: RTC clock source selection + bit_offset: 8 + bit_size: 2 + enum: RTCSEL + - name: RTCEN + description: RTC clock enable + bit_offset: 15 + bit_size: 1 + - name: BDRST + description: Backup domain software reset + bit_offset: 16 + bit_size: 1 +fieldset/CFGR: + description: Clock configuration register (RCC_CFGR) + fields: + - name: SW + description: System clock Switch + bit_offset: 0 + bit_size: 2 + enum: SW + - name: SWS + description: System Clock Switch Status + bit_offset: 2 + bit_size: 2 + enum: SW + - name: HPRE + description: AHB prescaler + bit_offset: 4 + bit_size: 4 + enum: HPRE + - name: PPRE1 + description: APB Low speed prescaler (APB1) + bit_offset: 8 + bit_size: 3 + enum: PPRE + - name: PPRE2 + description: APB high speed prescaler (APB2) + bit_offset: 11 + bit_size: 3 + enum: PPRE + - name: ADCPRE + description: ADC prescaler + bit_offset: 14 + bit_size: 2 + enum: ADCPRE + - name: PLLSRC + description: PLL entry clock source + bit_offset: 16 + bit_size: 1 + enum: PLLSRC + - name: PLLXTPRE + description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." + bit_offset: 17 + bit_size: 1 + enum: PLLXTPRE + - name: PLLMUL + description: PLL Multiplication Factor + bit_offset: 18 + bit_size: 4 + enum: PLLMUL + - name: USBPRE + description: USB prescaler + bit_offset: 22 + bit_size: 1 + enum: USBPRE + - name: I2SSRC + description: I2S external clock source selection + bit_offset: 23 + bit_size: 1 + enum: ISSRC + - name: MCOSEL + description: Microcontroller clock output + bit_offset: 24 + bit_size: 3 + enum: MCOSEL + - name: MCOPRE + description: Microcontroller Clock Output Prescaler + bit_offset: 28 + bit_size: 3 + enum: MCOPRE + - name: PLLMCODIV + description: Do not divide PLL to MCO + bit_offset: 31 + bit_size: 1 + enum: PLLMCODIV +fieldset/CFGR2: + description: Clock configuration register 2 + fields: + - name: PREDIV + description: PREDIV division factor + bit_offset: 0 + bit_size: 4 + enum: PREDIV + - name: ADC12PRES + description: ADC1 and ADC2 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC1PRES + description: ADC1 prescaler + bit_offset: 4 + bit_size: 5 + enum: ADCPRES + - name: ADC34PRES + description: ADC3 and ADC4 prescaler + bit_offset: 9 + bit_size: 5 + enum: ADCPRES +fieldset/CFGR3: + description: Clock configuration register 3 + fields: + - name: USART1SW + description: USART1 clock source selection + bit_offset: 0 + bit_size: 2 + enum: USARTSW + - name: I2C1SW + description: I2C1 clock source selection + bit_offset: 4 + bit_size: 1 + enum: ICSW + - name: I2C2SW + description: I2C2 clock source selection + bit_offset: 5 + bit_size: 1 + enum: ICSW + - name: CECSW + description: HDMI CEC clock source selection + bit_offset: 6 + bit_size: 1 + enum: CECSW + - name: I2C3SW + description: I2C3 clock source selection + bit_offset: 6 + bit_size: 1 + enum: ICSW + - name: TIM1SW + description: Timer1 clock source selection + bit_offset: 8 + bit_size: 1 + enum: TIMSW + - name: TIM8SW + description: Timer8 clock source selection + bit_offset: 9 + bit_size: 1 + enum: TIMSW + - name: TIM15SW + description: Timer15 clock source selection + bit_offset: 10 + bit_size: 1 + enum: TIMSW + - name: TIM16SW + description: Timer16 clock source selection + bit_offset: 11 + bit_size: 1 + enum: TIMSW + - name: HRTIM1SW + description: Hrtim1 clock source selection + bit_offset: 12 + bit_size: 1 + enum: TIMSW + - name: TIM17SW + description: Timer17 clock source selection + bit_offset: 13 + bit_size: 1 + enum: TIMSW + - name: TIM20SW + description: Timer20 clock source selection + bit_offset: 15 + bit_size: 1 + enum: TIMSW + - name: USART2SW + description: USART2 clock source selection + bit_offset: 16 + bit_size: 2 + enum: USARTSW + - name: USART3SW + description: USART3 clock source selection + bit_offset: 18 + bit_size: 2 + enum: USARTSW + - name: UART4SW + description: UART4 clock source selection + bit_offset: 20 + bit_size: 2 + enum: USARTSW + - name: UART5SW + description: UART5 clock source selection + bit_offset: 22 + bit_size: 2 + enum: USARTSW + - name: TIM2SW + description: Timer2 clock source selection + bit_offset: 24 + bit_size: 1 + enum: TIMSW + - name: TIM34SW + description: Timer34 clock source selection + bit_offset: 25 + bit_size: 1 + enum: TIMSW +fieldset/CIR: + description: Clock interrupt register (RCC_CIR) + fields: + - name: LSIRDYF + description: LSI Ready Interrupt flag + bit_offset: 0 + bit_size: 1 + - name: LSERDYF + description: LSE Ready Interrupt flag + bit_offset: 1 + bit_size: 1 + - name: HSIRDYF + description: HSI Ready Interrupt flag + bit_offset: 2 + bit_size: 1 + - name: HSERDYF + description: HSE Ready Interrupt flag + bit_offset: 3 + bit_size: 1 + - name: PLLRDYF + description: PLL Ready Interrupt flag + bit_offset: 4 + bit_size: 1 + - name: CSSF + description: Clock Security System Interrupt flag + bit_offset: 7 + bit_size: 1 + - name: LSIRDYIE + description: LSI Ready Interrupt Enable + bit_offset: 8 + bit_size: 1 + - name: LSERDYIE + description: LSE Ready Interrupt Enable + bit_offset: 9 + bit_size: 1 + - name: HSIRDYIE + description: HSI Ready Interrupt Enable + bit_offset: 10 + bit_size: 1 + - name: HSERDYIE + description: HSE Ready Interrupt Enable + bit_offset: 11 + bit_size: 1 + - name: PLLRDYIE + description: PLL Ready Interrupt Enable + bit_offset: 12 + bit_size: 1 + - name: LSIRDYC + description: LSI Ready Interrupt Clear + bit_offset: 16 + bit_size: 1 + - name: LSERDYC + description: LSE Ready Interrupt Clear + bit_offset: 17 + bit_size: 1 + - name: HSIRDYC + description: HSI Ready Interrupt Clear + bit_offset: 18 + bit_size: 1 + - name: HSERDYC + description: HSE Ready Interrupt Clear + bit_offset: 19 + bit_size: 1 + - name: PLLRDYC + description: PLL Ready Interrupt Clear + bit_offset: 20 + bit_size: 1 + - name: CSSC + description: Clock security system interrupt clear + bit_offset: 23 + bit_size: 1 +fieldset/CR: + description: Clock control register + fields: + - name: HSION + description: Internal High Speed clock enable + bit_offset: 0 + bit_size: 1 + - name: HSIRDY + description: Internal High Speed clock ready flag + bit_offset: 1 + bit_size: 1 + - name: HSITRIM + description: Internal High Speed clock trimming + bit_offset: 3 + bit_size: 5 + - name: HSICAL + description: Internal High Speed clock Calibration + bit_offset: 8 + bit_size: 8 + - name: HSEON + description: External High Speed clock enable + bit_offset: 16 + bit_size: 1 + - name: HSERDY + description: External High Speed clock ready flag + bit_offset: 17 + bit_size: 1 + - name: HSEBYP + description: External High Speed clock Bypass + bit_offset: 18 + bit_size: 1 + - name: CSSON + description: Clock Security System enable + bit_offset: 19 + bit_size: 1 + - name: PLLON + description: PLL enable + bit_offset: 24 + bit_size: 1 + - name: PLLRDY + description: PLL clock ready flag + bit_offset: 25 + bit_size: 1 +fieldset/CSR: + description: Control/status register (RCC_CSR) + fields: + - name: LSION + description: Internal low speed oscillator enable + bit_offset: 0 + bit_size: 1 + - name: LSIRDY + description: Internal low speed oscillator ready + bit_offset: 1 + bit_size: 1 + - name: V18PWRRSTF + description: Reset flag of the 1.8 V domain + bit_offset: 23 + bit_size: 1 + - name: RMVF + description: Remove reset flag + bit_offset: 24 + bit_size: 1 + - name: OBLRSTF + description: Option byte loader reset flag + bit_offset: 25 + bit_size: 1 + - name: PINRSTF + description: PIN reset flag + bit_offset: 26 + bit_size: 1 + - name: PORRSTF + description: POR/PDR reset flag + bit_offset: 27 + bit_size: 1 + - name: SFTRSTF + description: Software reset flag + bit_offset: 28 + bit_size: 1 + - name: IWDGRSTF + description: Independent watchdog reset flag + bit_offset: 29 + bit_size: 1 + - name: WWDGRSTF + description: Window watchdog reset flag + bit_offset: 30 + bit_size: 1 + - name: LPWRRSTF + description: Low-power reset flag + bit_offset: 31 + bit_size: 1 +enum/ADCPRE: + bit_size: 2 + variants: + - name: Div2 + description: PCLK divided by 2 + value: 0 + - name: Div4 + description: PCLK divided by 4 + value: 1 + - name: Div6 + description: PCLK divided by 6 + value: 2 + - name: Div8 + description: PCLK divided by 8 + value: 3 +enum/ADCPRES: + bit_size: 5 + variants: + - name: Div1 + description: PLL clock not divided + value: 16 + - name: Div2 + description: PLL clock divided by 2 + value: 17 + - name: Div4 + description: PLL clock divided by 4 + value: 18 + - name: Div6 + description: PLL clock divided by 6 + value: 19 + - name: Div8 + description: PLL clock divided by 8 + value: 20 + - name: Div10 + description: PLL clock divided by 10 + value: 21 + - name: Div12 + description: PLL clock divided by 12 + value: 22 + - name: Div16 + description: PLL clock divided by 16 + value: 23 + - name: Div32 + description: PLL clock divided by 32 + value: 24 + - name: Div64 + description: PLL clock divided by 64 + value: 25 + - name: Div128 + description: PLL clock divided by 128 + value: 26 + - name: Div256 + description: PLL clock divided by 256 + value: 27 +enum/CECSW: + bit_size: 1 + variants: + - name: HSI_DIV_244 + description: HSI clock divided by 244 selected as CEC clock source + value: 0 + - name: LSE + description: LSE clock selected as CEC clock source + value: 1 +enum/HPRE: + bit_size: 4 + variants: + - name: Div1 + description: SYSCLK not divided + value: 0 + - name: Div2 + description: SYSCLK divided by 2 + value: 8 + - name: Div4 + description: SYSCLK divided by 4 + value: 9 + - name: Div8 + description: SYSCLK divided by 8 + value: 10 + - name: Div16 + description: SYSCLK divided by 16 + value: 11 + - name: Div64 + description: SYSCLK divided by 64 + value: 12 + - name: Div128 + description: SYSCLK divided by 128 + value: 13 + - name: Div256 + description: SYSCLK divided by 256 + value: 14 + - name: Div512 + description: SYSCLK divided by 512 + value: 15 +enum/ICSW: + bit_size: 1 + variants: + - name: HSI + description: HSI clock selected as I2C clock source + value: 0 + - name: SYS + description: SYSCLK clock selected as I2C clock source + value: 1 +enum/ISSRC: + bit_size: 1 + variants: + - name: SYS + description: System clock used as I2S clock source + value: 0 + - name: CKIN + description: External clock mapped on the I2S_CKIN pin used as I2S clock source + value: 1 +enum/LSEDRV: + bit_size: 2 + variants: + - name: Low + description: Low driving capability + value: 0 + - name: MediumHigh + description: Medium high driving capability + value: 1 + - name: MediumLow + description: Medium low driving capability + value: 2 + - name: High + description: High driving capability + value: 3 +enum/MCOPRE: + bit_size: 3 + variants: + - name: Div1 + description: MCO is divided by 1 + value: 0 + - name: Div2 + description: MCO is divided by 2 + value: 1 + - name: Div4 + description: MCO is divided by 4 + value: 2 + - name: Div8 + description: MCO is divided by 8 + value: 3 + - name: Div16 + description: MCO is divided by 16 + value: 4 + - name: Div32 + description: MCO is divided by 32 + value: 5 + - name: Div64 + description: MCO is divided by 64 + value: 6 + - name: Div128 + description: MCO is divided by 128 + value: 7 +enum/MCOSEL: + bit_size: 3 + variants: + - name: NoMCO + description: MCO output disabled, no clock on MCO + value: 0 + - name: LSI + description: Internal low speed (LSI) oscillator clock selected + value: 2 + - name: LSE + description: External low speed (LSE) oscillator clock selected + value: 3 + - name: SYS + description: System clock selected + value: 4 + - name: HSI + description: Internal RC 8 MHz (HSI) oscillator clock selected + value: 5 + - name: HSE + description: External 4-32 MHz (HSE) oscillator clock selected + value: 6 + - name: PLL + description: PLL clock selected (divided by 1 or 2, depending en PLLMCODIV) + value: 7 +enum/PLLMCODIV: + bit_size: 1 + variants: + - name: Div2 + description: PLL is divided by 2 for MCO + value: 0 + - name: Div1 + description: PLL is not divided for MCO + value: 1 +enum/PLLMUL: + bit_size: 4 + variants: + - name: Mul2 + description: PLL input clock x2 + value: 0 + - name: Mul3 + description: PLL input clock x3 + value: 1 + - name: Mul4 + description: PLL input clock x4 + value: 2 + - name: Mul5 + description: PLL input clock x5 + value: 3 + - name: Mul6 + description: PLL input clock x6 + value: 4 + - name: Mul7 + description: PLL input clock x7 + value: 5 + - name: Mul8 + description: PLL input clock x8 + value: 6 + - name: Mul9 + description: PLL input clock x9 + value: 7 + - name: Mul10 + description: PLL input clock x10 + value: 8 + - name: Mul11 + description: PLL input clock x11 + value: 9 + - name: Mul12 + description: PLL input clock x12 + value: 10 + - name: Mul13 + description: PLL input clock x13 + value: 11 + - name: Mul14 + description: PLL input clock x14 + value: 12 + - name: Mul15 + description: PLL input clock x15 + value: 13 + - name: Mul16 + description: PLL input clock x16 + value: 14 +enum/PLLSRC: + bit_size: 1 + variants: + - name: HSI_Div2 + description: HSI divided by 2 selected as PLL input clock + value: 0 + - name: HSE_Div_PREDIV + description: HSE divided by PREDIV selected as PLL input clock + value: 1 +enum/PLLXTPRE: + bit_size: 1 + variants: + - name: Div1 + description: HSE clock not divided + value: 0 + - name: Div2 + description: HSE clock divided by 2 + value: 1 +enum/PPRE: + bit_size: 3 + variants: + - name: Div1 + description: HCLK not divided + value: 0 + - name: Div2 + description: HCLK divided by 2 + value: 4 + - name: Div4 + description: HCLK divided by 4 + value: 5 + - name: Div8 + description: HCLK divided by 8 + value: 6 + - name: Div16 + description: HCLK divided by 16 + value: 7 +enum/PREDIV: + bit_size: 4 + variants: + - name: Div1 + description: PREDIV input clock not divided + value: 0 + - name: Div2 + description: PREDIV input clock divided by 2 + value: 1 + - name: Div3 + description: PREDIV input clock divided by 3 + value: 2 + - name: Div4 + description: PREDIV input clock divided by 4 + value: 3 + - name: Div5 + description: PREDIV input clock divided by 5 + value: 4 + - name: Div6 + description: PREDIV input clock divided by 6 + value: 5 + - name: Div7 + description: PREDIV input clock divided by 7 + value: 6 + - name: Div8 + description: PREDIV input clock divided by 8 + value: 7 + - name: Div9 + description: PREDIV input clock divided by 9 + value: 8 + - name: Div10 + description: PREDIV input clock divided by 10 + value: 9 + - name: Div11 + description: PREDIV input clock divided by 11 + value: 10 + - name: Div12 + description: PREDIV input clock divided by 12 + value: 11 + - name: Div13 + description: PREDIV input clock divided by 13 + value: 12 + - name: Div14 + description: PREDIV input clock divided by 14 + value: 13 + - name: Div15 + description: PREDIV input clock divided by 15 + value: 14 + - name: Div16 + description: PREDIV input clock divided by 16 + value: 15 +enum/RTCSEL: + bit_size: 2 + variants: + - name: DISABLE + description: No clock + value: 0 + - name: LSE + description: LSE oscillator clock used as RTC clock + value: 1 + - name: LSI + description: LSI oscillator clock used as RTC clock + value: 2 + - name: HSE + description: HSE oscillator clock divided by a prescaler used as RTC clock + value: 3 +enum/SW: + bit_size: 2 + variants: + - name: HSI + description: HSI oscillator used as system clock + value: 0 + - name: HSE + description: HSE oscillator used as system clock + value: 1 + - name: PLL1_P + description: PLL used as system clock + value: 2 +enum/TIMSW: + bit_size: 1 + variants: + - name: PCLK2_TIM + description: PCLK2 clock (doubled frequency when prescaled) + value: 0 + - name: PLL1_P + description: PLL vco output (running up to 144 MHz) + value: 1 +enum/USARTSW: + bit_size: 2 + variants: + - name: PCLK1 + description: PCLK selected as USART clock source + value: 0 + - name: SYS + description: SYSCLK selected as USART clock source + value: 1 + - name: LSE + description: LSE selected as USART clock source + value: 2 + - name: HSI + description: HSI selected as USART clock source + value: 3 +enum/USBPRE: + bit_size: 1 + variants: + - name: Div1_5 + description: PLL clock is divided by 1.5 + value: 0 + - name: Div1 + description: PLL clock is not divided + value: 1 diff --git a/data/registers/rcc_f3.yaml b/data/registers/rcc_f3v3.yaml similarity index 95% rename from data/registers/rcc_f3.yaml rename to data/registers/rcc_f3v3.yaml index 6a39586..211cd00 100644 --- a/data/registers/rcc_f3.yaml +++ b/data/registers/rcc_f3v3.yaml @@ -523,7 +523,7 @@ fieldset/CFGR: bit_size: 2 enum: PLLSRC - name: PLLXTPRE - description: HSE divider for PLL entry + description: "HSE divider for PLL entry. Note: This bit is the same as the LSB of PREDIV in CFGR2, for compatibility with other STM32 products." bit_offset: 17 bit_size: 1 enum: PLLXTPRE @@ -547,11 +547,6 @@ fieldset/CFGR: bit_offset: 24 bit_size: 3 enum: MCOSEL - - name: SDPRE - description: SDADC prescaler - bit_offset: 27 - bit_size: 5 - enum: SDPRE - name: MCOPRE description: Microcontroller Clock Output Prescaler bit_offset: 28 @@ -1178,57 +1173,6 @@ enum/RTCSEL: - name: HSE description: HSE oscillator clock divided by a prescaler used as RTC clock value: 3 -enum/SDPRE: - bit_size: 5 - variants: - - name: Div2 - description: SYSCLK divided by 2 - value: 0 - - name: Div4 - description: SYSCLK divided by 4 - value: 17 - - name: Div6 - description: SYSCLK divided by 6 - value: 18 - - name: Div8 - description: SYSCLK divided by 8 - value: 19 - - name: Div10 - description: SYSCLK divided by 10 - value: 20 - - name: Div12 - description: SYSCLK divided by 12 - value: 21 - - name: Div14 - description: SYSCLK divided by 14 - value: 22 - - name: Div16 - description: SYSCLK divided by 16 - value: 23 - - name: Div20 - description: SYSCLK divided by 20 - value: 24 - - name: Div24 - description: SYSCLK divided by 24 - value: 25 - - name: Div28 - description: SYSCLK divided by 28 - value: 26 - - name: Div32 - description: SYSCLK divided by 32 - value: 27 - - name: Div36 - description: SYSCLK divided by 36 - value: 28 - - name: Div40 - description: SYSCLK divided by 40 - value: 29 - - name: Div44 - description: SYSCLK divided by 44 - value: 30 - - name: Div48 - description: SYSCLK divided by 48 - value: 31 enum/SW: bit_size: 2 variants: diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index c698c2c..0dddb5c 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -301,8 +301,12 @@ impl PeriMatcher { ("STM32F10[123].*:RCC:.*", ("rcc", "f1", "RCC")), ("STM32F10[57].*:RCC:.*", ("rcc", "f1cl", "RCC")), ("STM32F2.*:RCC:.*", ("rcc", "f2", "RCC")), - ("STM32F37.*:RCC:.*", ("rcc", "f3_v2", "RCC")), - ("STM32F3.*:RCC:.*", ("rcc", "f3", "RCC")), + ("STM32F37.*:RCC:.*", ("rcc", "f37", "RCC")), + ("STM32F30[23].[BC].*:RCC:.*", ("rcc", "f3v1", "RCC")), + ("STM32F358.C.*:RCC:.*", ("rcc", "f3v1", "RCC")), + ("STM32F30[23].[DE].*:RCC:.*", ("rcc", "f3v3", "RCC")), + ("STM32F398.E.*:RCC:.*", ("rcc", "f3v3", "RCC")), + ("STM32F3.*:RCC:.*", ("rcc", "f3v2", "RCC")), ("STM32F410.*:RCC:.*", ("rcc", "f410", "RCC")), ("STM32F4.*:RCC:.*", ("rcc", "f4", "RCC")), ("STM32F7.*:RCC:.*", ("rcc", "f7", "RCC")),