Merge pull request #422 from OroArmor/patch-1

Modify TIM(2)SW Clock Selection to use the new PLL1_P_MUL_2 name

data/registers/rcc_f3v3.yaml

@@ -1191,7 +1191,7 @@ enum/TIM2SW:
   - name: PCLK1_TIM
     description: PCLK2 clock (doubled frequency when prescaled)
     value: 0
-  - name: PLL1_P
+  - name: PLL1_P_MUL_2
     description: PLL vco output (running up to 144 MHz)
     value: 1
 enum/TIMSW:
@@ -1200,7 +1200,7 @@ enum/TIMSW:
   - name: PCLK2_TIM
     description: PCLK2 clock (doubled frequency when prescaled)
     value: 0
-  - name: PLL1_P
+  - name: PLL1_P_MUL_2
     description: PLL vco output (running up to 144 MHz)
     value: 1
 enum/USART1SW:

stm32-data-gen/src/rcc.rs

@@ -82,6 +82,7 @@ impl ParsedRccs {
             "PLLSAI2_Q",
             "PLLSAI2_R",
             "PLL1_P",
+            "PLL1_P_MUL_2",
             "PLL1_Q",
             "PLL1_R",
             "PLL1_VCO", // used for L0 USB