From e3a61442754eef58eea84edaececc0478365c10f Mon Sep 17 00:00:00 2001 From: Eli Orona Date: Sun, 25 Feb 2024 16:01:15 -0800 Subject: [PATCH 1/2] Modify TIM(2)SW Clock Selection to use the new PLL1_P_MUL_2 name --- data/registers/rcc_f3v3.yaml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/data/registers/rcc_f3v3.yaml b/data/registers/rcc_f3v3.yaml index 77b1581..f3c378b 100644 --- a/data/registers/rcc_f3v3.yaml +++ b/data/registers/rcc_f3v3.yaml @@ -1191,7 +1191,7 @@ enum/TIM2SW: - name: PCLK1_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - - name: PLL1_P + - name: PLL1_P_MUL_2 description: PLL vco output (running up to 144 MHz) value: 1 enum/TIMSW: @@ -1200,7 +1200,7 @@ enum/TIMSW: - name: PCLK2_TIM description: PCLK2 clock (doubled frequency when prescaled) value: 0 - - name: PLL1_P + - name: PLL1_P_MUL_2 description: PLL vco output (running up to 144 MHz) value: 1 enum/USART1SW: From 4ed2d3f65aa01892c68ae4e8439b74927b60af7e Mon Sep 17 00:00:00 2001 From: Eli Orona Date: Sun, 25 Feb 2024 16:16:25 -0800 Subject: [PATCH 2/2] Update rcc.rs --- stm32-data-gen/src/rcc.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/stm32-data-gen/src/rcc.rs b/stm32-data-gen/src/rcc.rs index e9cc6fe..fed750f 100644 --- a/stm32-data-gen/src/rcc.rs +++ b/stm32-data-gen/src/rcc.rs @@ -82,6 +82,7 @@ impl ParsedRccs { "PLLSAI2_Q", "PLLSAI2_R", "PLL1_P", + "PLL1_P_MUL_2", "PLL1_Q", "PLL1_R", "PLL1_VCO", // used for L0 USB