guangzong/stm32-data
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge pull request #422 from OroArmor/patch-1

Browse Source 
Modify TIM(2)SW Clock Selection to use the new PLL1_P_MUL_2 name
This commit is contained in:
Dario Nieuwenhuis 2024-02-26 00:28:44 +00:00 committed by GitHub
commit 88f71cbcd2
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
data/registers/rcc_f3v3.yaml
View File

@ -1191,7 +1191,7 @@ enum/TIM2SW:
- name: PCLK1_TIM - name: PCLK1_TIM
description: PCLK2 clock (doubled frequency when prescaled) description: PCLK2 clock (doubled frequency when prescaled)
value: 0 value: 0
- name: PLL1_P - name: PLL1_P_MUL_2
description: PLL vco output (running up to 144 MHz) description: PLL vco output (running up to 144 MHz)
value: 1 value: 1
enum/TIMSW: enum/TIMSW:
@ -1200,7 +1200,7 @@ enum/TIMSW:
- name: PCLK2_TIM - name: PCLK2_TIM
description: PCLK2 clock (doubled frequency when prescaled) description: PCLK2 clock (doubled frequency when prescaled)
value: 0 value: 0
- name: PLL1_P - name: PLL1_P_MUL_2
description: PLL vco output (running up to 144 MHz) description: PLL vco output (running up to 144 MHz)
value: 1 value: 1
enum/USART1SW: enum/USART1SW:

1
stm32-data-gen/src/rcc.rs
View File

@ -82,6 +82,7 @@ impl ParsedRccs {
"PLLSAI2_Q", "PLLSAI2_Q",
"PLLSAI2_R", "PLLSAI2_R",
"PLL1_P", "PLL1_P",
"PLL1_P_MUL_2",
"PLL1_Q", "PLL1_Q",
"PLL1_R", "PLL1_R",
"PLL1_VCO", // used for L0 USB "PLL1_VCO", // used for L0 USB