Add DBGMCU for all chips
This commit is contained in:
Dario Nieuwenhuis
parent
a39cc5e6d2
commit
77d4ae203b
@ -1,186 +0,0 @@
|
||||
---
|
||||
block/DBG:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: APB Low Freeze Register
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
fieldset/APB1_FZ:
|
||||
description: APB Low Freeze Register
|
||||
fields:
|
||||
- name: DBG_TIMER2_STOP
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: DBG_TIMER_STOP
|
||||
- name: DBG_TIMER6_STOP
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
enum: DBG_TIMER_STOP
|
||||
- name: DBG_RTC_STOP
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
enum: DBG_RTC_STOP
|
||||
- name: DBG_WWDG_STOP
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
enum: DBG_WWDG_STOP
|
||||
- name: DBG_IWDG_STOP
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
enum: DBG_IWDG_STOP
|
||||
- name: DBG_I2C1_STOP
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
enum: DBG_IC_STOP
|
||||
- name: DBG_I2C2_STOP
|
||||
description: I2C2 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
enum: DBG_IC_STOP
|
||||
- name: DBG_LPTIMER_STOP
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
enum: DBG_LPTIMER_STOP
|
||||
fieldset/APB2_FZ:
|
||||
description: APB High Freeze Register
|
||||
fields:
|
||||
- name: DBG_TIMER21_STOP
|
||||
description: Debug Timer 21 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: DBG_TIMER_STOP
|
||||
- name: DBG_TIMER22_STO
|
||||
description: Debug Timer 22 stopped when Core is halted
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
enum: DBG_SLEEP
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
enum: DBG_STOP
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
enum: DBG_STANDBY
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
enum/DBG_IC_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: NormalMode
|
||||
description: Same behavior as in normal mode
|
||||
value: 0
|
||||
- name: SMBusTimeoutFrozen
|
||||
description: I2C3 SMBUS timeout is frozen
|
||||
value: 1
|
||||
enum/DBG_IWDG_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Continue
|
||||
description: The independent watchdog counter clock continues even if the core is halted
|
||||
value: 0
|
||||
- name: Stop
|
||||
description: The independent watchdog counter clock is stopped when the core is halted
|
||||
value: 1
|
||||
enum/DBG_LPTIMER_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Continue
|
||||
description: LPTIM1 counter clock is fed even if the core is halted
|
||||
value: 0
|
||||
- name: Stop
|
||||
description: LPTIM1 counter clock is stopped when the core is halted
|
||||
value: 1
|
||||
enum/DBG_RTC_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Continue
|
||||
description: The clock of the RTC counter is fed even if the core is halted
|
||||
value: 0
|
||||
- name: Stop
|
||||
description: The clock of the RTC counter is stopped when the core is halted
|
||||
value: 1
|
||||
enum/DBG_SLEEP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Debug Sleep Mode Disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Debug Sleep Mode Enabled
|
||||
value: 1
|
||||
enum/DBG_STANDBY:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Debug Standby Mode Disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Debug Standby Mode Enabled
|
||||
value: 1
|
||||
enum/DBG_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Debug Stop Mode Disabled
|
||||
value: 0
|
||||
- name: Enabled
|
||||
description: Debug Stop Mode Enabled
|
||||
value: 1
|
||||
enum/DBG_TIMER_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Continue
|
||||
description: The counter clock of TIMx is fed even if the core is halted
|
||||
value: 0
|
||||
- name: Stop
|
||||
description: The counter clock of TIMx is stopped when the core is halted
|
||||
value: 1
|
||||
enum/DBG_WWDG_STOP:
|
||||
bit_size: 1
|
||||
variants:
|
||||
- name: Continue
|
||||
description: The window watchdog counter clock continues even if the core is halted
|
||||
value: 0
|
||||
- name: Stop
|
||||
description: The window watchdog counter clock is stopped when the core is halted
|
||||
value: 1
|
||||
109
data/registers/dbgmcu_f0.yaml
Normal file
109
data/registers/dbgmcu_f0.yaml
Normal file
@ -0,0 +1,109 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB2 freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
fieldset/APB1_FZ:
|
||||
description: Debug MCU APB1 freeze register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14 counter stopped when core is halted
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug window watchdog stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug independent watchdog stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: CAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/APB2_FZ:
|
||||
description: Debug MCU APB2 freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DIV_ID
|
||||
description: Division Identifier
|
||||
bit_offset: 12
|
||||
bit_size: 4
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
127
data/registers/dbgmcu_f1.yaml
Normal file
127
data/registers/dbgmcu_f1.yaml
Normal file
@ -0,0 +1,127 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: DBGMCU_CR
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
fieldset/CR:
|
||||
description: DBGMCU_CR
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: DBG_I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: DBG_I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 19
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: DBGMCU_IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
149
data/registers/dbgmcu_f2.yaml
Normal file
149
data/registers/dbgmcu_f2.yaml
Normal file
@ -0,0 +1,149 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1_FZ
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
byte_offset: 8
|
||||
fieldset: APB1_FZ
|
||||
- name: APB2_FZ
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
byte_offset: 12
|
||||
fieldset: APB2_FZ
|
||||
fieldset/APB1_FZ:
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDEG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_J2C1_SMBUS_TIMEOUT
|
||||
description: DBG_J2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_J2C2_SMBUS_TIMEOUT
|
||||
description: DBG_J2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_J2C3SMBUS_TIMEOUT
|
||||
description: DBG_J2C3SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/APB2_FZ:
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
141
data/registers/dbgmcu_f3.yaml
Normal file
141
data/registers/dbgmcu_f3.yaml
Normal file
@ -0,0 +1,141 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: APB Low Freeze Register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: APB Low Freeze Register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: Debug Timer 3 stopped when Core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: Debug Timer 4 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: Debug Timer 5 stopped when Core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: Debug Timer 7 stopped when Core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: Debug Timer 12 stopped when Core is halted
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: Debug Timer 13 stopped when Core is halted
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: Debug Timer 14 stopped when Core is halted
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: TIM18
|
||||
description: Debug Timer 18 stopped when Core is halted
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: Debug CAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB High Freeze Register
|
||||
fields:
|
||||
- name: TIM15
|
||||
description: Debug Timer 15 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: Debug Timer 16 stopped when Core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: Debug Timer 17 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM19
|
||||
description: Debug Timer 19 stopped when Core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
153
data/registers/dbgmcu_f4.yaml
Normal file
153
data/registers/dbgmcu_f4.yaml
Normal file
@ -0,0 +1,153 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: Debug MCU APB1 Freeze registe
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDEG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1_SMBUS_TIMEOUT
|
||||
description: I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2_SMBUS_TIMEOUT
|
||||
description: I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3_SMBUS_TIMEOUT
|
||||
description: I2C3SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: I2CFMP_SMBUS_TIMEOUT
|
||||
description: SMBUS timeout mode stopped when Core is halted
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: Debug MCU APB2 Freeze registe
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
161
data/registers/dbgmcu_f7.yaml
Normal file
161
data/registers/dbgmcu_f7.yaml
Normal file
@ -0,0 +1,161 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Control Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: Debug MCU APB1 Freeze register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 Freeze register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: Debug MCU APB1 Freeze register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TIM12
|
||||
description: TIM12
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
- name: TIM13
|
||||
description: TIM13
|
||||
bit_offset: 7
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: CAN3
|
||||
description: CAN3
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_SMBUS_TIMEOUT
|
||||
description: DBG_I2C1_SMBUS_TIMEOUT
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_SMBUS_TIMEOUT
|
||||
description: DBG_I2C2_SMBUS_TIMEOUT
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_I2C3_SMBUS_TIMEOUT
|
||||
description: DBG_I2C3_SMBUS_TIMEOUT
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DBG_I2C4_SMBUS_TIMEOUT
|
||||
description: DBG_I2C4SMBUS_TIMEOUT
|
||||
bit_offset: 24
|
||||
bit_size: 1
|
||||
- name: CAN1
|
||||
description: CAN1
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: CAN2
|
||||
description: CAN2
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: Debug MCU APB2 Freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM9
|
||||
description: TIM9 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM10
|
||||
description: TIM10 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM11
|
||||
description: TIM11 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Control Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: DBG_SLEEP
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: DBG_STOP
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: DBG_STANDBY
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: TRACE_IOEN
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: TRACE_MODE
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: DEV_ID
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: REV_ID
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
109
data/registers/dbgmcu_g0.yaml
Normal file
109
data/registers/dbgmcu_g0.yaml
Normal file
@ -0,0 +1,109 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: DBG APB freeze register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: DBG APB freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: DBG APB freeze register 1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: LPTIM2
|
||||
description: Clocking of LPTIMER2 counter when the core is halted
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: Clocking of LPTIMER1 counter when the core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: DBG APB freeze register 2
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM14
|
||||
description: TIM14
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
164
data/registers/dbgmcu_g4.yaml
Normal file
164
data/registers/dbgmcu_g4.yaml
Normal file
@ -0,0 +1,164 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1LFZR
|
||||
description: APB Low Freeze Register 1
|
||||
byte_offset: 8
|
||||
fieldset: APB1LFZR
|
||||
- name: APB1HFZR
|
||||
description: APB Low Freeze Register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB1HFZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1HFZR:
|
||||
description: APB Low Freeze Register 2
|
||||
fields:
|
||||
- name: I2C4
|
||||
description: I2C4
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
fieldset/APB1LFZR:
|
||||
description: APB Low Freeze Register 1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 30
|
||||
bit_size: 1
|
||||
- name: LPTIMER
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB High Freeze Register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
- name: TIM20
|
||||
description: TIM20counter stopped when core is halted
|
||||
bit_offset: 20
|
||||
bit_size: 1
|
||||
- name: HRTIM0
|
||||
description: HRTIM0
|
||||
bit_offset: 26
|
||||
bit_size: 1
|
||||
- name: HRTIM1
|
||||
description: HRTIM0
|
||||
bit_offset: 27
|
||||
bit_size: 1
|
||||
- name: HRTIM2
|
||||
description: HRTIM0
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
- name: HRTIM3
|
||||
description: HRTIM0
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
@ -11,23 +11,23 @@ block/DBGMCU:
|
||||
description: Configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB3FZ1
|
||||
- name: APB3FZR1
|
||||
description: APB3 peripheral freeze register
|
||||
byte_offset: 52
|
||||
fieldset: APB3FZ1
|
||||
- name: APB1LFZ1
|
||||
fieldset: APB3FZR1
|
||||
- name: APB1LFZR1
|
||||
description: APB1L peripheral freeze register
|
||||
byte_offset: 60
|
||||
fieldset: APB1LFZ1
|
||||
- name: APB2FZ1
|
||||
fieldset: APB1LFZR1
|
||||
- name: APB2FZR1
|
||||
description: APB2 peripheral freeze register
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZ1
|
||||
- name: APB4FZ1
|
||||
fieldset: APB2FZR1
|
||||
- name: APB4FZR1
|
||||
description: APB4 peripheral freeze register
|
||||
byte_offset: 84
|
||||
fieldset: APB4FZ1
|
||||
fieldset/APB1LFZ1:
|
||||
fieldset: APB4FZR1
|
||||
fieldset/APB1LFZR1:
|
||||
description: APB1L peripheral freeze register
|
||||
fields:
|
||||
- name: TIM2
|
||||
@ -82,7 +82,7 @@ fieldset/APB1LFZ1:
|
||||
description: I2C3 SMBUS timeout stop in debug mode
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
fieldset/APB2FZ1:
|
||||
fieldset/APB2FZR1:
|
||||
description: APB2 peripheral freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
@ -109,14 +109,14 @@ fieldset/APB2FZ1:
|
||||
description: HRTIM stop in debug mode
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
fieldset/APB3FZ1:
|
||||
fieldset/APB3FZR1:
|
||||
description: APB3 peripheral freeze register
|
||||
fields:
|
||||
- name: WWDG1
|
||||
description: WWDG1 stop in debug mode
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/APB4FZ1:
|
||||
fieldset/APB4FZR1:
|
||||
description: APB4 peripheral freeze register
|
||||
fields:
|
||||
- name: I2C4
|
||||
|
||||
93
data/registers/dbgmcu_l0.yaml
Normal file
93
data/registers/dbgmcu_l0.yaml
Normal file
@ -0,0 +1,93 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR
|
||||
description: APB Low Freeze Register
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR
|
||||
- name: APB2FZR
|
||||
description: APB High Freeze Register
|
||||
byte_offset: 12
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR:
|
||||
description: APB Low Freeze Register
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: Debug Timer 6 stopped when Core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: Debug RTC stopped when Core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Debug Window Wachdog stopped when Core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Debug Independent Wachdog stopped when Core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout mode stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: LPTIM
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB High Freeze Register
|
||||
fields:
|
||||
- name: TIM21
|
||||
description: Debug Timer 21 stopped when Core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM22
|
||||
description: Debug Timer 22 stopped when Core is halted
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
148
data/registers/dbgmcu_l4.yaml
Normal file
148
data/registers/dbgmcu_l4.yaml
Normal file
@ -0,0 +1,148 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: MCU debug component
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: DBGMCU_IDCODE
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU configuration register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: Debug MCU APB1 freeze register1
|
||||
byte_offset: 8
|
||||
fieldset: APB1FZR1
|
||||
- name: APB1FZR2
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
byte_offset: 12
|
||||
fieldset: APB1FZR2
|
||||
- name: APB2FZR
|
||||
description: Debug MCU APB2 freeze register
|
||||
byte_offset: 16
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
description: Debug MCU APB1 freeze register1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: TIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: TIM3
|
||||
description: TIM3 counter stopped when core is halted
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: TIM4
|
||||
description: TIM4 counter stopped when core is halted
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TIM5
|
||||
description: TIM5 counter stopped when core is halted
|
||||
bit_offset: 3
|
||||
bit_size: 1
|
||||
- name: TIM6
|
||||
description: TIM6 counter stopped when core is halted
|
||||
bit_offset: 4
|
||||
bit_size: 1
|
||||
- name: TIM7
|
||||
description: TIM7 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: Window watchdog counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: Independent watchdog counter stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout counter stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: CAN
|
||||
description: bxCAN stopped when core is halted
|
||||
bit_offset: 25
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB1FZR2:
|
||||
description: Debug MCU APB1 freeze register 2
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: Debug MCU APB2 freeze register
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM8
|
||||
description: TIM8 counter stopped when core is halted
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
- name: TIM15
|
||||
description: TIM15 counter stopped when core is halted
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU configuration register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRACE_MODE
|
||||
description: Trace pin assignment control
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
fieldset/IDCODE:
|
||||
description: DBGMCU_IDCODE
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device identifier
|
||||
bit_offset: 0
|
||||
bit_size: 16
|
||||
- name: REV_ID
|
||||
description: Revision identifie
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
173
data/registers/dbgmcu_wb.yaml
Normal file
173
data/registers/dbgmcu_wb.yaml
Normal file
@ -0,0 +1,173 @@
|
||||
---
|
||||
block/DBGMCU:
|
||||
description: Debug support
|
||||
items:
|
||||
- name: IDCODE
|
||||
description: MCU Device ID Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODE
|
||||
- name: CR
|
||||
description: Debug MCU Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: APB1 Low Freeze Register CPU1
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2AP_B1FZR1
|
||||
description: APB1 Low Freeze Register CPU2
|
||||
byte_offset: 64
|
||||
fieldset: C2AP_B1FZR1
|
||||
- name: APB1FZR2
|
||||
description: APB1 High Freeze Register CPU1
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: APB1 High Freeze Register CPU2
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: C2APB2FZR
|
||||
description: APB2 Freeze Register CPU2
|
||||
byte_offset: 72
|
||||
fieldset: C2APB2FZR
|
||||
- name: APB2FZR
|
||||
description: APB2 Freeze Register CPU1
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
description: APB1 Low Freeze Register CPU1
|
||||
fields:
|
||||
- name: TIM2
|
||||
description: Debug Timer 2 stopped when Core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: WWDG
|
||||
description: WWDG counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG counter stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: Debug I2C1 SMBUS timeout stopped when Core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: Debug I2C3 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: Debug LPTIM1 stopped when Core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB1FZR2:
|
||||
description: APB1 High Freeze Register CPU1
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: APB2 Freeze Register CPU1
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR2:
|
||||
description: APB1 High Freeze Register CPU2
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
fieldset/C2APB2FZR:
|
||||
description: APB2 Freeze Register CPU2
|
||||
fields:
|
||||
- name: TIM1
|
||||
description: TIM1 counter stopped when core is halted
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: TIM16
|
||||
description: TIM16 counter stopped when core is halted
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: TIM17
|
||||
description: TIM17 counter stopped when core is halted
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2AP_B1FZR1:
|
||||
description: APB1 Low Freeze Register CPU2
|
||||
fields:
|
||||
- name: LPTIM2
|
||||
description: LPTIM2 counter stopped when core is halted
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: RTC
|
||||
description: RTC counter stopped when core is halted
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: IWDG
|
||||
description: IWDG stopped when core is halted
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stopped when core is halted
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 counter stopped when core is halted
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: Debug MCU Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Debug Sleep Mode
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_STOP
|
||||
description: Debug Stop Mode
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
- name: DBG_STANDBY
|
||||
description: Debug Standby Mode
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
- name: TRACE_IOEN
|
||||
description: Trace port and clock enable
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: TRGOEN
|
||||
description: External trigger output enable
|
||||
bit_offset: 28
|
||||
bit_size: 1
|
||||
fieldset/IDCODE:
|
||||
description: MCU Device ID Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device Identifier
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: REV_ID
|
||||
description: Revision Identifier
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
@ -3,158 +3,158 @@ block/DBGMCU:
|
||||
description: Microcontroller Debug Unit
|
||||
items:
|
||||
- name: IDCODER
|
||||
description: DBGMCU Identity Code Register
|
||||
description: Identity Code Register
|
||||
byte_offset: 0
|
||||
access: Read
|
||||
fieldset: IDCODER
|
||||
- name: CR
|
||||
description: DBGMCU Configuration Register
|
||||
description: Configuration Register
|
||||
byte_offset: 4
|
||||
fieldset: CR
|
||||
- name: APB1FZR1
|
||||
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 1
|
||||
description: CPU1 APB1 Peripheral Freeze Register 1
|
||||
byte_offset: 60
|
||||
fieldset: APB1FZR1
|
||||
- name: C2APB1FZR1
|
||||
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
byte_offset: 64
|
||||
fieldset: C2APB1FZR1
|
||||
- name: APB1FZR2
|
||||
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 2
|
||||
description: CPU1 APB1 Peripheral Freeze Register 2
|
||||
byte_offset: 68
|
||||
fieldset: APB1FZR2
|
||||
- name: C2APB1FZR2
|
||||
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
byte_offset: 72
|
||||
fieldset: C2APB1FZR2
|
||||
- name: APB2FZR
|
||||
description: DBGMCU CPU1 APB2 Peripheral Freeze Register
|
||||
description: CPU1 APB2 Peripheral Freeze Register
|
||||
byte_offset: 76
|
||||
fieldset: APB2FZR
|
||||
- name: C2APB2FZR
|
||||
description: "DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
byte_offset: 80
|
||||
fieldset: C2APB2FZR
|
||||
fieldset/APB1FZR1:
|
||||
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 1
|
||||
description: CPU1 APB1 Peripheral Freeze Register 1
|
||||
fields:
|
||||
- name: DBG_TIM2_STOP
|
||||
- name: TIM2
|
||||
description: TIM2 stop in CPU1 debug
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
- name: RTC
|
||||
description: RTC stop in CPU1 debug
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_WWDG_STOP
|
||||
- name: WWDG
|
||||
description: WWDG stop in CPU1 debug
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
- name: IWDG
|
||||
description: IWDG stop in CPU1 debug
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_STOP
|
||||
- name: I2C1
|
||||
description: I2C1 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_STOP
|
||||
- name: I2C2
|
||||
description: I2C2 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_I2C3_STOP
|
||||
- name: I2C3
|
||||
description: I2C3 SMBUS timeout stop in CPU1 debug
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM1_STOP
|
||||
- name: LPTIM1
|
||||
description: LPTIM1 stop in CPU1 debug
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/APB1FZR2:
|
||||
description: DBGMCU CPU1 APB1 Peripheral Freeze Register 2
|
||||
description: CPU1 APB1 Peripheral Freeze Register 2
|
||||
fields:
|
||||
- name: DBG_LPTIM2_STOP
|
||||
description: DBG_LPTIM2_STOP
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM3_STOP
|
||||
description: DBG_LPTIM3_STOP
|
||||
- name: LPTIM3
|
||||
description: LPTIM3
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/APB2FZR:
|
||||
description: DBGMCU CPU1 APB2 Peripheral Freeze Register
|
||||
description: CPU1 APB2 Peripheral Freeze Register
|
||||
fields:
|
||||
- name: DBG_TIM1_STOP
|
||||
description: DBG_TIM1_STOP
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_TIM16_STOP
|
||||
description: DBG_TIM16_STOP
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_TIM17_STOP
|
||||
description: DBG_TIM17_STOP
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR1:
|
||||
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 1 [dual core device"
|
||||
fields:
|
||||
- name: DBG_TIM2_STOP
|
||||
description: DBG_TIM2_STOP
|
||||
- name: TIM2
|
||||
description: TIM2
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
- name: DBG_RTC_STOP
|
||||
description: DBG_RTC_STOP
|
||||
- name: RTC
|
||||
description: RTC
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DBG_IWDG_STOP
|
||||
description: DBG_IWDG_STOP
|
||||
- name: IWDG
|
||||
description: IWDG
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: DBG_I2C1_STOP
|
||||
description: DBG_I2C1_STOP
|
||||
- name: I2C1
|
||||
description: I2C1
|
||||
bit_offset: 21
|
||||
bit_size: 1
|
||||
- name: DBG_I2C2_STOP
|
||||
description: DBG_I2C2_STOP
|
||||
- name: I2C2
|
||||
description: I2C2
|
||||
bit_offset: 22
|
||||
bit_size: 1
|
||||
- name: DBG_I2C3_STOP
|
||||
description: DBG_I2C3_STOP
|
||||
- name: I2C3
|
||||
description: I2C3
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM1_STOP
|
||||
description: DBG_LPTIM1_STOP
|
||||
- name: LPTIM1
|
||||
description: LPTIM1
|
||||
bit_offset: 31
|
||||
bit_size: 1
|
||||
fieldset/C2APB1FZR2:
|
||||
description: "DBGMCU CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
description: "CPU2 APB1 Peripheral Freeze Register 2 [dual core device"
|
||||
fields:
|
||||
- name: DBG_LPTIM2_STOP
|
||||
description: DBG_LPTIM2_STOP
|
||||
- name: LPTIM2
|
||||
description: LPTIM2
|
||||
bit_offset: 5
|
||||
bit_size: 1
|
||||
- name: DBG_LPTIM3_STOP
|
||||
description: DBG_LPTIM3_STOP
|
||||
- name: LPTIM3
|
||||
description: LPTIM3
|
||||
bit_offset: 6
|
||||
bit_size: 1
|
||||
fieldset/C2APB2FZR:
|
||||
description: "DBGMCU CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
description: "CPU2 APB2 Peripheral Freeze Register [dual core device"
|
||||
fields:
|
||||
- name: DBG_TIM1_STOP
|
||||
description: DBG_TIM1_STOP
|
||||
- name: TIM1
|
||||
description: TIM1
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
- name: DBG_TIM16_STOP
|
||||
description: DBG_TIM16_STOP
|
||||
- name: TIM16
|
||||
description: TIM16
|
||||
bit_offset: 17
|
||||
bit_size: 1
|
||||
- name: DBG_TIM17_STOP
|
||||
description: DBG_TIM17_STOP
|
||||
- name: TIM17
|
||||
description: TIM17
|
||||
bit_offset: 18
|
||||
bit_size: 1
|
||||
fieldset/CR:
|
||||
description: DBGMCU Configuration Register
|
||||
description: Configuration Register
|
||||
fields:
|
||||
- name: DBG_SLEEP
|
||||
description: Allow debug in SLEEP mode
|
||||
@ -169,7 +169,7 @@ fieldset/CR:
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
fieldset/IDCODER:
|
||||
description: DBGMCU Identity Code Register
|
||||
description: Identity Code Register
|
||||
fields:
|
||||
- name: DEV_ID
|
||||
description: Device ID
|
||||
37
parse.py
37
parse.py
@ -13,6 +13,7 @@ def removeprefix(value: str, prefix: str, /) -> str:
|
||||
else:
|
||||
return value[:]
|
||||
|
||||
|
||||
def corename(d):
|
||||
if m := re.match('.*Cortex-M(\d+)(\+?)', d):
|
||||
name = "cm" + str(m.group(1))
|
||||
@ -20,6 +21,7 @@ def corename(d):
|
||||
name += "p"
|
||||
return name
|
||||
|
||||
|
||||
def removesuffix(value: str, suffix: str, /) -> str:
|
||||
if value.endswith(suffix):
|
||||
return value[:-len(suffix)]
|
||||
@ -153,7 +155,7 @@ def parse_header(f):
|
||||
accum = ''
|
||||
|
||||
# Scoped by a single core
|
||||
if m:= re.match('.*if defined.*CORE_CM(\\d+)(PLUS)?.*', l):
|
||||
if m := re.match('.*if defined.*CORE_CM(\\d+)(PLUS)?.*', l):
|
||||
cur_core = "cm" + str(m.group(1))
|
||||
if m.group(2) != None:
|
||||
cur_core += "p"
|
||||
@ -165,9 +167,9 @@ def parse_header(f):
|
||||
if not found:
|
||||
cores.append(cur_core)
|
||||
#print("Switching to core", cur_core, "for", f)
|
||||
elif m:= re.match('.*else.*', l):
|
||||
elif m := re.match('.*else.*', l):
|
||||
cur_core = "all"
|
||||
if m:= re.match('.*else.*CORE_CM(\\d+)(PLUS)?.*', l):
|
||||
if m := re.match('.*else.*CORE_CM(\\d+)(PLUS)?.*', l):
|
||||
cur_core = "cm" + str(m.group(1))
|
||||
if m.group(2) != None:
|
||||
cur_core += "p"
|
||||
@ -183,11 +185,10 @@ def parse_header(f):
|
||||
if not found:
|
||||
cores.append(cur_core)
|
||||
#print("Switching to core", cur_core, "for", f)
|
||||
elif m:= re.match('.*endif.*', l):
|
||||
elif m := re.match('.*endif.*', l):
|
||||
#print("Switching to common core for", f)
|
||||
cur_core = "all"
|
||||
|
||||
|
||||
if cur_core not in irqs:
|
||||
#print("Registering new core", cur_core)
|
||||
irqs[cur_core] = {}
|
||||
@ -318,15 +319,26 @@ perimap = [
|
||||
('.*:STM32H7AB_rcc_v1_0', ''), # rcc_h7ab/RCC
|
||||
('.*:STM32H7_rcc_v1_0', 'rcc_h7/RCC'),
|
||||
('.*:STM32W_rcc_v1_0', 'rcc_wb55/RCC'),
|
||||
('.*:STM32L0_dbgmcu_v1_0', 'dbg_l0/DBG'),
|
||||
('.*:STM32L0_crs_v1_0', 'crs_l0/CRS'),
|
||||
('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl5x/DBGMCU'),
|
||||
('.*SDMMC:sdmmc2_v1_0', 'sdmmc_v2/SDMMC'),
|
||||
('.*:STM32H7_pwr_v1_0', 'pwr_h7/PWR'),
|
||||
('.*:STM32H7_flash_v1_0', 'flash_h7/FLASH'),
|
||||
('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'),
|
||||
('.*TIM\d.*:gptimer.*', 'timer_v1/TIM_GP16'),
|
||||
('.*ETH:ethermac110_v3_0', 'eth_v2/ETH'),
|
||||
|
||||
('.*:STM32F0_dbgmcu_v1_0', 'dbgmcu_f0/DBGMCU'),
|
||||
('.*:STM32F1_dbgmcu_v1_0', 'dbgmcu_f1/DBGMCU'),
|
||||
('.*:STM32F2_dbgmcu_v1_0', 'dbgmcu_f2/DBGMCU'),
|
||||
('.*:STM32F3_dbgmcu_v1_0', 'dbgmcu_f3/DBGMCU'),
|
||||
('.*:STM32F4_dbgmcu_v1_0', 'dbgmcu_f4/DBGMCU'),
|
||||
('.*:STM32F7_dbgmcu_v1_0', 'dbgmcu_f7/DBGMCU'),
|
||||
('.*:STM32G0_dbgmcu_v1_0', 'dbgmcu_g0/DBGMCU'),
|
||||
('.*:STM32G4_dbgmcu_v1_0', 'dbgmcu_g4/DBGMCU'),
|
||||
('.*:STM32H7_dbgmcu_v1_0', 'dbgmcu_h7/DBGMCU'),
|
||||
('.*:STM32L0_dbgmcu_v1_0', 'dbgmcu_l0/DBGMCU'),
|
||||
('.*:STM32L4_dbgmcu_v1_0', 'dbgmcu_l4/DBGMCU'),
|
||||
('.*:STM32WB_dbgmcu_v1_0', 'dbgmcu_wb/DBGMCU'),
|
||||
('.*:STM32WL_dbgmcu_v1_0', 'dbgmcu_wl/DBGMCU'),
|
||||
]
|
||||
|
||||
rng_clock_map = [
|
||||
@ -338,6 +350,7 @@ rng_clock_map = [
|
||||
('STM32WL5.*:RNG:.*', 'AHB3')
|
||||
]
|
||||
|
||||
|
||||
def match_peri(peri):
|
||||
for r, block in perimap:
|
||||
if re.match(r, peri):
|
||||
@ -450,7 +463,6 @@ def parse_chips():
|
||||
'name': corename(core),
|
||||
'peripherals': {},
|
||||
}))
|
||||
|
||||
|
||||
if chip_name not in chips:
|
||||
chips[chip_name] = OrderedDict({
|
||||
@ -474,7 +486,6 @@ def parse_chips():
|
||||
'package': r['@Package'],
|
||||
}))
|
||||
|
||||
|
||||
# Some packages have some peripehrals removed because the package had to
|
||||
# remove GPIOs useful for that peripheral. So we merge all peripherals from all packages.
|
||||
peris = chips[chip_name]['peripherals']
|
||||
@ -591,8 +602,8 @@ def parse_chips():
|
||||
|
||||
peris[pname] = p
|
||||
|
||||
family_extra = "data/extra/family/" + chip['family'] + ".yaml";
|
||||
if os.path.exists(family_extra) :
|
||||
family_extra = "data/extra/family/" + chip['family'] + ".yaml"
|
||||
if os.path.exists(family_extra):
|
||||
with open(family_extra) as extra_f:
|
||||
extra = yaml.load(extra_f, Loader=yaml.SafeLoader)
|
||||
for (extra_name, extra_p) in extra['peripherals'].items():
|
||||
@ -644,7 +655,7 @@ def parse_chips():
|
||||
peris['FLASH'] = flash_peri
|
||||
|
||||
# DBGMCU is not in the cubedb XMLs
|
||||
if addr := defines.get('DBGMCU_BASE'):
|
||||
if addr := defines.get('DBGMCU_BASE') or defines.get('DBG_BASE'):
|
||||
kind = 'DBGMCU:' + chip_name[:7] + '_dbgmcu_v1_0'
|
||||
dbg_peri = OrderedDict({
|
||||
'address': addr,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user