stm32-data/data/registers/dbgmcu_g4.yaml
2021-06-21 01:27:36 +02:00

165 lines
4.3 KiB
YAML

---
block/DBGMCU:
description: Debug support
items:
- name: IDCODE
description: MCU Device ID Code Register
byte_offset: 0
access: Read
fieldset: IDCODE
- name: CR
description: Debug MCU Configuration Register
byte_offset: 4
fieldset: CR
- name: APB1LFZR
description: APB Low Freeze Register 1
byte_offset: 8
fieldset: APB1LFZR
- name: APB1HFZR
description: APB Low Freeze Register 2
byte_offset: 12
fieldset: APB1HFZR
- name: APB2FZR
description: APB High Freeze Register
byte_offset: 16
fieldset: APB2FZR
fieldset/APB1HFZR:
description: APB Low Freeze Register 2
fields:
- name: I2C4
description: I2C4
bit_offset: 1
bit_size: 1
fieldset/APB1LFZR:
description: APB Low Freeze Register 1
fields:
- name: TIM2
description: Debug Timer 2 stopped when Core is halted
bit_offset: 0
bit_size: 1
- name: TIM3
description: TIM3 counter stopped when core is halted
bit_offset: 1
bit_size: 1
- name: TIM4
description: TIM4 counter stopped when core is halted
bit_offset: 2
bit_size: 1
- name: TIM5
description: TIM5 counter stopped when core is halted
bit_offset: 3
bit_size: 1
- name: TIM6
description: Debug Timer 6 stopped when Core is halted
bit_offset: 4
bit_size: 1
- name: TIM7
description: TIM7 counter stopped when core is halted
bit_offset: 5
bit_size: 1
- name: RTC
description: Debug RTC stopped when Core is halted
bit_offset: 10
bit_size: 1
- name: WWDG
description: Debug Window Wachdog stopped when Core is halted
bit_offset: 11
bit_size: 1
- name: IWDG
description: Debug Independent Wachdog stopped when Core is halted
bit_offset: 12
bit_size: 1
- name: I2C1
description: I2C1 SMBUS timeout mode stopped when core is halted
bit_offset: 21
bit_size: 1
- name: I2C2
description: I2C2 SMBUS timeout mode stopped when core is halted
bit_offset: 22
bit_size: 1
- name: I2C3
description: I2C3 SMBUS timeout mode stopped when core is halted
bit_offset: 30
bit_size: 1
- name: LPTIMER
description: LPTIM1 counter stopped when core is halted
bit_offset: 31
bit_size: 1
fieldset/APB2FZR:
description: APB High Freeze Register
fields:
- name: TIM1
description: TIM1 counter stopped when core is halted
bit_offset: 11
bit_size: 1
- name: TIM8
description: TIM8 counter stopped when core is halted
bit_offset: 13
bit_size: 1
- name: TIM15
description: TIM15 counter stopped when core is halted
bit_offset: 16
bit_size: 1
- name: TIM16
description: TIM16 counter stopped when core is halted
bit_offset: 17
bit_size: 1
- name: TIM17
description: TIM17 counter stopped when core is halted
bit_offset: 18
bit_size: 1
- name: TIM20
description: TIM20counter stopped when core is halted
bit_offset: 20
bit_size: 1
- name: HRTIM0
description: HRTIM0
bit_offset: 26
bit_size: 1
- name: HRTIM1
description: HRTIM0
bit_offset: 27
bit_size: 1
- name: HRTIM2
description: HRTIM0
bit_offset: 28
bit_size: 1
- name: HRTIM3
description: HRTIM0
bit_offset: 29
bit_size: 1
fieldset/CR:
description: Debug MCU Configuration Register
fields:
- name: DBG_SLEEP
description: Debug Sleep Mode
bit_offset: 0
bit_size: 1
- name: DBG_STOP
description: Debug Stop Mode
bit_offset: 1
bit_size: 1
- name: DBG_STANDBY
description: Debug Standby Mode
bit_offset: 2
bit_size: 1
- name: TRACE_IOEN
description: Trace pin assignment control
bit_offset: 5
bit_size: 1
- name: TRACE_MODE
description: Trace pin assignment control
bit_offset: 6
bit_size: 2
fieldset/IDCODE:
description: MCU Device ID Code Register
fields:
- name: DEV_ID
description: Device Identifier
bit_offset: 0
bit_size: 16
- name: REV_ID
description: Revision Identifier
bit_offset: 16
bit_size: 16