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Merge pull request #263 from embassy-rs/add-missing-peris

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pwr: add f0, f1.
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Dario Nieuwenhuis 2023-09-24 22:30:02 +00:00 committed by GitHub
commit 74025d56c0
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78
data/registers/pwr_f0.yaml Normal file
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@ -0,0 +1,78 @@
block/PWR:
description: Power control
items:
- name: CR
description: power control register
byte_offset: 0
fieldset: CR
- name: CSR
description: power control/status register
byte_offset: 4
fieldset: CSR
fieldset/CR:
description: power control register
fields:
- name: LPDS
description: Low-power deep sleep
bit_offset: 0
bit_size: 1
- name: PDDS
description: Power down deepsleep
bit_offset: 1
bit_size: 1
enum: PDDS
- name: CWUF
description: Clear wakeup flag
bit_offset: 2
bit_size: 1
- name: CSBF
description: Clear standby flag
bit_offset: 3
bit_size: 1
- name: PVDE
description: Power voltage detector enable
bit_offset: 4
bit_size: 1
- name: PLS
description: PVD level selection
bit_offset: 5
bit_size: 3
- name: DBP
description: Disable backup domain write protection
bit_offset: 8
bit_size: 1
fieldset/CSR:
description: power control/status register
fields:
- name: WUF
description: Wakeup flag
bit_offset: 0
bit_size: 1
- name: SBF
description: Standby flag
bit_offset: 1
bit_size: 1
- name: PVDO
description: PVD output
bit_offset: 2
bit_size: 1
- name: VREFINTRDY
description: VREFINT reference voltage ready
bit_offset: 3
bit_size: 1
- name: EWUP
description: Enable WKUP pin 1
bit_offset: 8
bit_size: 1
array:
len: 8
stride: 1
enum/PDDS:
bit_size: 1
variants:
- name: STOP_MODE
description: Enter Stop mode when the CPU enters deepsleep
value: 0
- name: STANDBY_MODE
description: Enter Standby mode when the CPU enters deepsleep
value: 1

62
data/registers/pwr_f0x0.yaml Normal file
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@ -0,0 +1,62 @@
block/PWR:
description: Power control
items:
- name: CR
description: power control register
byte_offset: 0
fieldset: CR
- name: CSR
description: power control/status register
byte_offset: 4
fieldset: CSR
fieldset/CR:
description: power control register
fields:
- name: LPDS
description: Low-power deep sleep
bit_offset: 0
bit_size: 1
- name: PDDS
description: Power down deepsleep
bit_offset: 1
bit_size: 1
enum: PDDS
- name: CWUF
description: Clear wakeup flag
bit_offset: 2
bit_size: 1
- name: CSBF
description: Clear standby flag
bit_offset: 3
bit_size: 1
- name: DBP
description: Disable backup domain write protection
bit_offset: 8
bit_size: 1
fieldset/CSR:
description: power control/status register
fields:
- name: WUF
description: Wakeup flag
bit_offset: 0
bit_size: 1
- name: SBF
description: Standby flag
bit_offset: 1
bit_size: 1
- name: EWUP
description: Enable WKUP pin 1
bit_offset: 8
bit_size: 1
array:
len: 8
stride: 1
enum/PDDS:
bit_size: 1
variants:
- name: STOP_MODE
description: Enter Stop mode when the CPU enters deepsleep
value: 0
- name: STANDBY_MODE
description: Enter Standby mode when the CPU enters deepsleep
value: 1

71
data/registers/pwr_f1.yaml Normal file
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@ -0,0 +1,71 @@
block/PWR:
description: Power control
items:
- name: CR
description: Power control register (PWR_CR)
byte_offset: 0
fieldset: CR
- name: CSR
description: Power control register (PWR_CR)
byte_offset: 4
fieldset: CSR
fieldset/CR:
description: Power control register (PWR_CR)
fields:
- name: LPDS
description: Low Power Deep Sleep
bit_offset: 0
bit_size: 1
- name: PDDS
description: Power Down Deep Sleep
bit_offset: 1
bit_size: 1
enum: PDDS
- name: CWUF
description: Clear Wake-up Flag
bit_offset: 2
bit_size: 1
- name: CSBF
description: Clear STANDBY Flag
bit_offset: 3
bit_size: 1
- name: PVDE
description: Power Voltage Detector Enable
bit_offset: 4
bit_size: 1
- name: PLS
description: PVD Level Selection
bit_offset: 5
bit_size: 3
- name: DBP
description: Disable Backup Domain write protection
bit_offset: 8
bit_size: 1
fieldset/CSR:
description: Power control register (PWR_CR)
fields:
- name: WUF
description: Wake-Up Flag
bit_offset: 0
bit_size: 1
- name: SBF
description: STANDBY Flag
bit_offset: 1
bit_size: 1
- name: PVDO
description: PVD Output
bit_offset: 2
bit_size: 1
- name: EWUP
description: Enable WKUP pin
bit_offset: 8
bit_size: 1
enum/PDDS:
bit_size: 1
variants:
- name: STOP_MODE
description: Enter Stop mode when the CPU enters deepsleep
value: 0
- name: STANDBY_MODE
description: Enter Standby mode when the CPU enters deepsleep
value: 1

3
stm32-data-gen/src/chips.rs
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@ -336,6 +336,9 @@ impl PeriMatcher {
("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7rm0433", "PWR")), ("STM32H7(42|43|53|50).*:PWR:.*", ("pwr", "h7rm0433", "PWR")),
("STM32H7(23|25|33|35|30).*:PWR:.*", ("pwr", "h7rm0468", "PWR")), ("STM32H7(23|25|33|35|30).*:PWR:.*", ("pwr", "h7rm0468", "PWR")),
("STM32H7(A3|B0|B3).*:PWR:.*", ("pwr", "h7rm0455", "PWR")), ("STM32H7(A3|B0|B3).*:PWR:.*", ("pwr", "h7rm0455", "PWR")),
("STM32F0.0.*:PWR:.*", ("pwr", "f0x0", "PWR")),
("STM32F0.*:PWR:.*", ("pwr", "f0", "PWR")),
("STM32F1.*:PWR:.*", ("pwr", "f1", "PWR")),
("STM32F2.*:PWR:.*", ("pwr", "f2", "PWR")), ("STM32F2.*:PWR:.*", ("pwr", "f2", "PWR")),
("STM32F3.*:PWR:.*", ("pwr", "f3", "PWR")), ("STM32F3.*:PWR:.*", ("pwr", "f3", "PWR")),
("STM32F4.*:PWR:.*", ("pwr", "f4", "PWR")), ("STM32F4.*:PWR:.*", ("pwr", "f4", "PWR")),