Merge pull request #401 from eZioPan/icache

icache
2024-02-21 17:13:03 +00:00 · 2024-02-21 17:13:03 +00:00 · 71b1db43df
commit 71b1db43df
parent 07e666fa9d 0e673ac3f1
5 changed files with 326 additions and 46 deletions
--- a/data/registers/icache_v1_0crr.yaml
+++ b/data/registers/icache_v1_0crr.yaml
@ -0,0 +1,115 @@
+block/ICACHE:
+  description: Instruction Cache Control Registers.
+  items:
+  - name: CR
+    description: ICACHE control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: ICACHE status register.
+    byte_offset: 4
+    access: Read
+    fieldset: SR
+  - name: IER
+    description: ICACHE interrupt enable register.
+    byte_offset: 8
+    fieldset: IER
+  - name: FCR
+    description: ICACHE flag clear register.
+    byte_offset: 12
+    access: Write
+    fieldset: FCR
+  - name: HMONR
+    description: ICACHE hit monitor register.
+    byte_offset: 16
+    access: Read
+  - name: MMONR
+    description: ICACHE miss monitor register.
+    byte_offset: 20
+    access: Read
+    fieldset: MMONR
+fieldset/CR:
+  description: ICACHE control register.
+  fields:
+  - name: EN
+    description: EN.
+    bit_offset: 0
+    bit_size: 1
+  - name: CACHEINV
+    description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect.
+    bit_offset: 1
+    bit_size: 1
+  - name: WAYSEL
+    description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0).
+    bit_offset: 2
+    bit_size: 1
+    enum: WAYSEL
+  - name: HITMEN
+    description: Hit monitor enable.
+    bit_offset: 16
+    bit_size: 1
+  - name: MISSMEN
+    description: Miss monitor enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: HITMRST
+    description: Hit monitor reset.
+    bit_offset: 18
+    bit_size: 1
+  - name: MISSMRST
+    description: Miss monitor reset.
+    bit_offset: 19
+    bit_size: 1
+fieldset/FCR:
+  description: ICACHE flag clear register.
+  fields:
+  - name: CBSYENDF
+    description: Clear busy end flag.
+    bit_offset: 1
+    bit_size: 1
+  - name: CERRF
+    description: Clear ERRF flag in SR.
+    bit_offset: 2
+    bit_size: 1
+fieldset/IER:
+  description: ICACHE interrupt enable register.
+  fields:
+  - name: BSYENDIE
+    description: Interrupt enable on busy end.
+    bit_offset: 1
+    bit_size: 1
+  - name: ERRIE
+    description: Error interrupt on cache error.
+    bit_offset: 2
+    bit_size: 1
+fieldset/MMONR:
+  description: ICACHE miss monitor register.
+  fields:
+  - name: MISSMON
+    description: Miss monitor register.
+    bit_offset: 0
+    bit_size: 16
+fieldset/SR:
+  description: ICACHE status register.
+  fields:
+  - name: BUSYF
+    description: cache busy executing a full invalidate CACHEINV operation.
+    bit_offset: 0
+    bit_size: 1
+  - name: BSYENDF
+    description: full invalidate CACHEINV operation finished.
+    bit_offset: 1
+    bit_size: 1
+  - name: ERRF
+    description: an error occurred during the operation.
+    bit_offset: 2
+    bit_size: 1
+enum/WAYSEL:
+  bit_size: 1
+  variants:
+  - name: DirectMapped
+    description: direct mapped cache (1-way cache)
+    value: 0
+  - name: NWaySetAssociative
+    description: n-way set associative cache (reset value)
+    value: 1
--- a/data/registers/icache_v1_3crr.yaml
+++ b/data/registers/icache_v1_3crr.yaml
@ -1,10 +1,3 @@
-block/CRR:
-  description: ICACHE region configuration register.
-  items:
-  - name: CRRX
-    description: ICACHE control register.
-    byte_offset: 0
-    fieldset: CRRX
 block/ICACHE:
  description: Instruction Cache Control Registers.
  items:
@ -30,7 +23,6 @@ block/ICACHE:
    description: ICACHE hit monitor register.
    byte_offset: 16
    access: Read
-    fieldset: HMONR
  - name: MMONR
    description: ICACHE miss monitor register.
    byte_offset: 20
@ -42,7 +34,7 @@ block/ICACHE:
      len: 3
      stride: 4
    byte_offset: 32
-    block: CRR
+    fieldset: CRR
 fieldset/CR:
  description: ICACHE control register.
  fields:
@ -54,7 +46,6 @@ fieldset/CR:
    description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect.
    bit_offset: 1
    bit_size: 1
-    enum: CACHEINV
  - name: WAYSEL
    description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0).
    bit_offset: 2
@ -72,13 +63,11 @@ fieldset/CR:
    description: Hit monitor reset.
    bit_offset: 18
    bit_size: 1
-    enum: HITMRST
  - name: MISSMRST
    description: Miss monitor reset.
    bit_offset: 19
    bit_size: 1
-    enum: MISSMRST
-fieldset/CRRX:
+fieldset/CRR:
  description: ICACHE region configuration register.
  fields:
  - name: BASEADDR
@ -119,13 +108,6 @@ fieldset/FCR:
    description: Clear ERRF flag in SR.
    bit_offset: 2
    bit_size: 1
-fieldset/HMONR:
-  description: ICACHE hit monitor register.
-  fields:
-  - name: HITMON
-    description: Hit monitor register.
-    bit_offset: 0
-    bit_size: 32
 fieldset/IER:
  description: ICACHE interrupt enable register.
  fields:
@ -159,12 +141,6 @@ fieldset/SR:
    description: an error occurred during the operation.
    bit_offset: 2
    bit_size: 1
-enum/CACHEINV:
-  bit_size: 1
-  variants:
-  - name: Invalidate
-    description: Invalidate entire cache
-    value: 1
 enum/HBURST:
  bit_size: 1
  variants:
@ -172,18 +148,6 @@ enum/HBURST:
    value: 0
  - name: Increment
    value: 1
-enum/HITMRST:
-  bit_size: 1
-  variants:
-  - name: Reset
-    description: Reset cache hit monitor
-    value: 1
-enum/MISSMRST:
-  bit_size: 1
-  variants:
-  - name: Reset
-    description: Reset cache miss monitor
-    value: 1
 enum/MSTSEL:
  bit_size: 1
  variants:
@ -194,19 +158,19 @@ enum/MSTSEL:
 enum/RSIZE:
  bit_size: 3
  variants:
-  - name: TwoMegabytes
+  - name: MegaBytes2
    value: 1
-  - name: FourMegabytes
+  - name: MegaBytes4
    value: 2
-  - name: EightMegabytes
+  - name: MegaBytes8
    value: 3
-  - name: SixteenMegabytes
+  - name: MegaBytes16
    value: 4
-  - name: ThirtyTwoMegabytes
+  - name: MegaBytes32
    value: 5
-  - name: SixtyFourMegabytes
+  - name: MegaBytes64
    value: 6
-  - name: OneTwentyEightMegabytes
+  - name: MegaBytes128
    value: 7
 enum/WAYSEL:
  bit_size: 1
--- a/data/registers/icache_v1_4crr.yaml
+++ b/data/registers/icache_v1_4crr.yaml
@ -0,0 +1,183 @@
+block/ICACHE:
+  description: Instruction Cache Control Registers.
+  items:
+  - name: CR
+    description: ICACHE control register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SR
+    description: ICACHE status register.
+    byte_offset: 4
+    access: Read
+    fieldset: SR
+  - name: IER
+    description: ICACHE interrupt enable register.
+    byte_offset: 8
+    fieldset: IER
+  - name: FCR
+    description: ICACHE flag clear register.
+    byte_offset: 12
+    access: Write
+    fieldset: FCR
+  - name: HMONR
+    description: ICACHE hit monitor register.
+    byte_offset: 16
+    access: Read
+  - name: MMONR
+    description: ICACHE miss monitor register.
+    byte_offset: 20
+    access: Read
+    fieldset: MMONR
+  - name: CRR
+    description: Cluster CRR%s, container region configuration registers.
+    array:
+      len: 4
+      stride: 4
+    byte_offset: 32
+    fieldset: CRR
+fieldset/CR:
+  description: ICACHE control register.
+  fields:
+  - name: EN
+    description: EN.
+    bit_offset: 0
+    bit_size: 1
+  - name: CACHEINV
+    description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect.
+    bit_offset: 1
+    bit_size: 1
+  - name: WAYSEL
+    description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0).
+    bit_offset: 2
+    bit_size: 1
+    enum: WAYSEL
+  - name: HITMEN
+    description: Hit monitor enable.
+    bit_offset: 16
+    bit_size: 1
+  - name: MISSMEN
+    description: Miss monitor enable.
+    bit_offset: 17
+    bit_size: 1
+  - name: HITMRST
+    description: Hit monitor reset.
+    bit_offset: 18
+    bit_size: 1
+  - name: MISSMRST
+    description: Miss monitor reset.
+    bit_offset: 19
+    bit_size: 1
+fieldset/CRR:
+  description: ICACHE region configuration register.
+  fields:
+  - name: BASEADDR
+    description: base address for region.
+    bit_offset: 0
+    bit_size: 8
+  - name: RSIZE
+    description: size for region.
+    bit_offset: 9
+    bit_size: 3
+    enum: RSIZE
+  - name: REN
+    description: enable for region.
+    bit_offset: 15
+    bit_size: 1
+  - name: REMAPADDR
+    description: remapped address for region.
+    bit_offset: 16
+    bit_size: 11
+  - name: MSTSEL
+    description: AHB cache master selection for region.
+    bit_offset: 28
+    bit_size: 1
+    enum: MSTSEL
+  - name: HBURST
+    description: output burst type for region.
+    bit_offset: 31
+    bit_size: 1
+    enum: HBURST
+fieldset/FCR:
+  description: ICACHE flag clear register.
+  fields:
+  - name: CBSYENDF
+    description: Clear busy end flag.
+    bit_offset: 1
+    bit_size: 1
+  - name: CERRF
+    description: Clear ERRF flag in SR.
+    bit_offset: 2
+    bit_size: 1
+fieldset/IER:
+  description: ICACHE interrupt enable register.
+  fields:
+  - name: BSYENDIE
+    description: Interrupt enable on busy end.
+    bit_offset: 1
+    bit_size: 1
+  - name: ERRIE
+    description: Error interrupt on cache error.
+    bit_offset: 2
+    bit_size: 1
+fieldset/MMONR:
+  description: ICACHE miss monitor register.
+  fields:
+  - name: MISSMON
+    description: Miss monitor register.
+    bit_offset: 0
+    bit_size: 16
+fieldset/SR:
+  description: ICACHE status register.
+  fields:
+  - name: BUSYF
+    description: cache busy executing a full invalidate CACHEINV operation.
+    bit_offset: 0
+    bit_size: 1
+  - name: BSYENDF
+    description: full invalidate CACHEINV operation finished.
+    bit_offset: 1
+    bit_size: 1
+  - name: ERRF
+    description: an error occurred during the operation.
+    bit_offset: 2
+    bit_size: 1
+enum/HBURST:
+  bit_size: 1
+  variants:
+  - name: Wrap
+    value: 0
+  - name: Increment
+    value: 1
+enum/MSTSEL:
+  bit_size: 1
+  variants:
+  - name: Master1Selected
+    value: 0
+  - name: Master2Selected
+    value: 1
+enum/RSIZE:
+  bit_size: 3
+  variants:
+  - name: MegaBytes2
+    value: 1
+  - name: MegaBytes4
+    value: 2
+  - name: MegaBytes8
+    value: 3
+  - name: MegaBytes16
+    value: 4
+  - name: MegaBytes32
+    value: 5
+  - name: MegaBytes64
+    value: 6
+  - name: MegaBytes128
+    value: 7
+enum/WAYSEL:
+  bit_size: 1
+  variants:
+  - name: DirectMapped
+    description: direct mapped cache (1-way cache)
+    value: 0
+  - name: NWaySetAssociative
+    description: n-way set associative cache (reset value)
+    value: 1
--- a/stm32-data-gen/src/chips.rs
+++ b/stm32-data-gen/src/chips.rs
@ -580,7 +580,9 @@ impl PeriMatcher {
            ),
            ("STM32L4.*:GFXMMU:.*", ("gfxmmu", "v1", "GFXMMU")),
            ("STM32U5.*:GFXMMU:.*", ("gfxmmu", "v2", "GFXMMU")),
-            ("STM32U5.*:ICACHE:.*", ("icache", "v1", "ICACHE")),
+            ("STM32U5.*:ICACHE:.*", ("icache", "v1_3crr", "ICACHE")),
+            ("STM32H50.*:ICACHE:.*", ("icache", "v1_0crr", "ICACHE")),
+            ("STM32(L5|H5[67]|WBA).*:ICACHE:.*", ("icache", "v1_4crr", "ICACHE")),
            (".*:CORDIC:.*", ("cordic", "v1", "CORDIC")),
            ("STM32F0x[128].*:TSC:.*", ("tsc", "v1", "TSC")),
            ("STM32F3[07][123].*:TSC:.*", ("tsc", "v1", "TSC")),
--- a/transforms/ICACHE.yaml
+++ b/transforms/ICACHE.yaml
@ -0,0 +1,16 @@
+transforms:
+
+  - !DeleteEnums
+    from: ^(CACHEINV|HITMRST|MISSMRST)$
+
+  - !DeleteFieldsets
+    from: HMONR
+
+  - !MergeFieldsets
+    from: CRR\d
+    to: CRR
+
+  - !MakeRegisterArray
+    blocks: ICACHE
+    from: CRR\d
+    to: CRR