From 9fdc197974130ef054facbe09747d8cb787ca775 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Wed, 21 Feb 2024 23:04:03 +0800 Subject: [PATCH 1/6] icache_v1 block array to fieldset array --- data/registers/icache_v1.yaml | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/data/registers/icache_v1.yaml b/data/registers/icache_v1.yaml index c0e4972..77767ad 100644 --- a/data/registers/icache_v1.yaml +++ b/data/registers/icache_v1.yaml @@ -1,10 +1,3 @@ -block/CRR: - description: ICACHE region configuration register. - items: - - name: CRRX - description: ICACHE control register. - byte_offset: 0 - fieldset: CRRX block/ICACHE: description: Instruction Cache Control Registers. items: @@ -42,7 +35,7 @@ block/ICACHE: len: 3 stride: 4 byte_offset: 32 - block: CRR + fieldset: CRR fieldset/CR: description: ICACHE control register. fields: @@ -78,7 +71,7 @@ fieldset/CR: bit_offset: 19 bit_size: 1 enum: MISSMRST -fieldset/CRRX: +fieldset/CRR: description: ICACHE region configuration register. fields: - name: BASEADDR From f88fd564fecd8e77ecedf3f80895e0a7c25fb982 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Wed, 21 Feb 2024 23:04:28 +0800 Subject: [PATCH 2/6] recreate transform file --- transforms/ICACHE.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) create mode 100644 transforms/ICACHE.yaml diff --git a/transforms/ICACHE.yaml b/transforms/ICACHE.yaml new file mode 100644 index 0000000..6d96e29 --- /dev/null +++ b/transforms/ICACHE.yaml @@ -0,0 +1,10 @@ +transforms: + + - !MergeFieldsets + from: CRR\d + to: CRR + + - !MakeRegisterArray + blocks: ICACHE + from: CRR\d + to: CRR From 4ab86cb898cc1302b36316e99aa579d703045776 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Wed, 21 Feb 2024 23:05:38 +0800 Subject: [PATCH 3/6] change CRR array length --- data/registers/icache_v1_0crr.yaml | 144 ++++++++++++ .../{icache_v1.yaml => icache_v1_3crr.yaml} | 0 data/registers/icache_v1_4crr.yaml | 212 ++++++++++++++++++ stm32-data-gen/src/chips.rs | 4 +- 4 files changed, 359 insertions(+), 1 deletion(-) create mode 100644 data/registers/icache_v1_0crr.yaml rename data/registers/{icache_v1.yaml => icache_v1_3crr.yaml} (100%) create mode 100644 data/registers/icache_v1_4crr.yaml diff --git a/data/registers/icache_v1_0crr.yaml b/data/registers/icache_v1_0crr.yaml new file mode 100644 index 0000000..37faf9a --- /dev/null +++ b/data/registers/icache_v1_0crr.yaml @@ -0,0 +1,144 @@ +block/ICACHE: + description: Instruction Cache Control Registers. + items: + - name: CR + description: ICACHE control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: ICACHE status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: IER + description: ICACHE interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: FCR + description: ICACHE flag clear register. + byte_offset: 12 + access: Write + fieldset: FCR + - name: HMONR + description: ICACHE hit monitor register. + byte_offset: 16 + access: Read + fieldset: HMONR + - name: MMONR + description: ICACHE miss monitor register. + byte_offset: 20 + access: Read + fieldset: MMONR +fieldset/CR: + description: ICACHE control register. + fields: + - name: EN + description: EN. + bit_offset: 0 + bit_size: 1 + - name: CACHEINV + description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. + bit_offset: 1 + bit_size: 1 + enum: CACHEINV + - name: WAYSEL + description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). + bit_offset: 2 + bit_size: 1 + enum: WAYSEL + - name: HITMEN + description: Hit monitor enable. + bit_offset: 16 + bit_size: 1 + - name: MISSMEN + description: Miss monitor enable. + bit_offset: 17 + bit_size: 1 + - name: HITMRST + description: Hit monitor reset. + bit_offset: 18 + bit_size: 1 + enum: HITMRST + - name: MISSMRST + description: Miss monitor reset. + bit_offset: 19 + bit_size: 1 + enum: MISSMRST +fieldset/FCR: + description: ICACHE flag clear register. + fields: + - name: CBSYENDF + description: Clear busy end flag. + bit_offset: 1 + bit_size: 1 + - name: CERRF + description: Clear ERRF flag in SR. + bit_offset: 2 + bit_size: 1 +fieldset/HMONR: + description: ICACHE hit monitor register. + fields: + - name: HITMON + description: Hit monitor register. + bit_offset: 0 + bit_size: 32 +fieldset/IER: + description: ICACHE interrupt enable register. + fields: + - name: BSYENDIE + description: Interrupt enable on busy end. + bit_offset: 1 + bit_size: 1 + - name: ERRIE + description: Error interrupt on cache error. + bit_offset: 2 + bit_size: 1 +fieldset/MMONR: + description: ICACHE miss monitor register. + fields: + - name: MISSMON + description: Miss monitor register. + bit_offset: 0 + bit_size: 16 +fieldset/SR: + description: ICACHE status register. + fields: + - name: BUSYF + description: cache busy executing a full invalidate CACHEINV operation. + bit_offset: 0 + bit_size: 1 + - name: BSYENDF + description: full invalidate CACHEINV operation finished. + bit_offset: 1 + bit_size: 1 + - name: ERRF + description: an error occurred during the operation. + bit_offset: 2 + bit_size: 1 +enum/CACHEINV: + bit_size: 1 + variants: + - name: Invalidate + description: Invalidate entire cache + value: 1 +enum/HITMRST: + bit_size: 1 + variants: + - name: Reset + description: Reset cache hit monitor + value: 1 +enum/MISSMRST: + bit_size: 1 + variants: + - name: Reset + description: Reset cache miss monitor + value: 1 +enum/WAYSEL: + bit_size: 1 + variants: + - name: DirectMapped + description: direct mapped cache (1-way cache) + value: 0 + - name: NWaySetAssociative + description: n-way set associative cache (reset value) + value: 1 diff --git a/data/registers/icache_v1.yaml b/data/registers/icache_v1_3crr.yaml similarity index 100% rename from data/registers/icache_v1.yaml rename to data/registers/icache_v1_3crr.yaml diff --git a/data/registers/icache_v1_4crr.yaml b/data/registers/icache_v1_4crr.yaml new file mode 100644 index 0000000..52c4f72 --- /dev/null +++ b/data/registers/icache_v1_4crr.yaml @@ -0,0 +1,212 @@ +block/ICACHE: + description: Instruction Cache Control Registers. + items: + - name: CR + description: ICACHE control register. + byte_offset: 0 + fieldset: CR + - name: SR + description: ICACHE status register. + byte_offset: 4 + access: Read + fieldset: SR + - name: IER + description: ICACHE interrupt enable register. + byte_offset: 8 + fieldset: IER + - name: FCR + description: ICACHE flag clear register. + byte_offset: 12 + access: Write + fieldset: FCR + - name: HMONR + description: ICACHE hit monitor register. + byte_offset: 16 + access: Read + fieldset: HMONR + - name: MMONR + description: ICACHE miss monitor register. + byte_offset: 20 + access: Read + fieldset: MMONR + - name: CRR + description: Cluster CRR%s, container region configuration registers. + array: + len: 4 + stride: 4 + byte_offset: 32 + fieldset: CRR +fieldset/CR: + description: ICACHE control register. + fields: + - name: EN + description: EN. + bit_offset: 0 + bit_size: 1 + - name: CACHEINV + description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. + bit_offset: 1 + bit_size: 1 + enum: CACHEINV + - name: WAYSEL + description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). + bit_offset: 2 + bit_size: 1 + enum: WAYSEL + - name: HITMEN + description: Hit monitor enable. + bit_offset: 16 + bit_size: 1 + - name: MISSMEN + description: Miss monitor enable. + bit_offset: 17 + bit_size: 1 + - name: HITMRST + description: Hit monitor reset. + bit_offset: 18 + bit_size: 1 + enum: HITMRST + - name: MISSMRST + description: Miss monitor reset. + bit_offset: 19 + bit_size: 1 + enum: MISSMRST +fieldset/CRR: + description: ICACHE region configuration register. + fields: + - name: BASEADDR + description: base address for region. + bit_offset: 0 + bit_size: 8 + - name: RSIZE + description: size for region. + bit_offset: 9 + bit_size: 3 + enum: RSIZE + - name: REN + description: enable for region. + bit_offset: 15 + bit_size: 1 + - name: REMAPADDR + description: remapped address for region. + bit_offset: 16 + bit_size: 11 + - name: MSTSEL + description: AHB cache master selection for region. + bit_offset: 28 + bit_size: 1 + enum: MSTSEL + - name: HBURST + description: output burst type for region. + bit_offset: 31 + bit_size: 1 + enum: HBURST +fieldset/FCR: + description: ICACHE flag clear register. + fields: + - name: CBSYENDF + description: Clear busy end flag. + bit_offset: 1 + bit_size: 1 + - name: CERRF + description: Clear ERRF flag in SR. + bit_offset: 2 + bit_size: 1 +fieldset/HMONR: + description: ICACHE hit monitor register. + fields: + - name: HITMON + description: Hit monitor register. + bit_offset: 0 + bit_size: 32 +fieldset/IER: + description: ICACHE interrupt enable register. + fields: + - name: BSYENDIE + description: Interrupt enable on busy end. + bit_offset: 1 + bit_size: 1 + - name: ERRIE + description: Error interrupt on cache error. + bit_offset: 2 + bit_size: 1 +fieldset/MMONR: + description: ICACHE miss monitor register. + fields: + - name: MISSMON + description: Miss monitor register. + bit_offset: 0 + bit_size: 16 +fieldset/SR: + description: ICACHE status register. + fields: + - name: BUSYF + description: cache busy executing a full invalidate CACHEINV operation. + bit_offset: 0 + bit_size: 1 + - name: BSYENDF + description: full invalidate CACHEINV operation finished. + bit_offset: 1 + bit_size: 1 + - name: ERRF + description: an error occurred during the operation. + bit_offset: 2 + bit_size: 1 +enum/CACHEINV: + bit_size: 1 + variants: + - name: Invalidate + description: Invalidate entire cache + value: 1 +enum/HBURST: + bit_size: 1 + variants: + - name: Wrap + value: 0 + - name: Increment + value: 1 +enum/HITMRST: + bit_size: 1 + variants: + - name: Reset + description: Reset cache hit monitor + value: 1 +enum/MISSMRST: + bit_size: 1 + variants: + - name: Reset + description: Reset cache miss monitor + value: 1 +enum/MSTSEL: + bit_size: 1 + variants: + - name: Master1Selected + value: 0 + - name: Master2Selected + value: 1 +enum/RSIZE: + bit_size: 3 + variants: + - name: TwoMegabytes + value: 1 + - name: FourMegabytes + value: 2 + - name: EightMegabytes + value: 3 + - name: SixteenMegabytes + value: 4 + - name: ThirtyTwoMegabytes + value: 5 + - name: SixtyFourMegabytes + value: 6 + - name: OneTwentyEightMegabytes + value: 7 +enum/WAYSEL: + bit_size: 1 + variants: + - name: DirectMapped + description: direct mapped cache (1-way cache) + value: 0 + - name: NWaySetAssociative + description: n-way set associative cache (reset value) + value: 1 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index b1c9b17..54e9d2a 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -580,7 +580,9 @@ impl PeriMatcher { ), ("STM32L4.*:GFXMMU:.*", ("gfxmmu", "v1", "GFXMMU")), ("STM32U5.*:GFXMMU:.*", ("gfxmmu", "v2", "GFXMMU")), - ("STM32U5.*:ICACHE:.*", ("icache", "v1", "ICACHE")), + ("STM32U5.*:ICACHE:.*", ("icache", "v1_3crr", "ICACHE")), + ("STM32H50.*:ICACHE:.*", ("icache", "v1_0crr", "ICACHE")), + ("STM32(L5|H5[67]|WBA).*:ICACHE:.*", ("icache", "v1_4crr", "ICACHE")), (".*:CORDIC:.*", ("cordic", "v1", "CORDIC")), ("STM32F0x[128].*:TSC:.*", ("tsc", "v1", "TSC")), ("STM32F3[07][123].*:TSC:.*", ("tsc", "v1", "TSC")), From 66e0a73f3819d9d7e067a514243dfff80760e751 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Wed, 21 Feb 2024 23:30:56 +0800 Subject: [PATCH 4/6] remove 32bit HMONR fieldset --- data/registers/icache_v1_0crr.yaml | 8 -------- data/registers/icache_v1_3crr.yaml | 8 -------- data/registers/icache_v1_4crr.yaml | 8 -------- transforms/ICACHE.yaml | 3 +++ 4 files changed, 3 insertions(+), 24 deletions(-) diff --git a/data/registers/icache_v1_0crr.yaml b/data/registers/icache_v1_0crr.yaml index 37faf9a..589e529 100644 --- a/data/registers/icache_v1_0crr.yaml +++ b/data/registers/icache_v1_0crr.yaml @@ -23,7 +23,6 @@ block/ICACHE: description: ICACHE hit monitor register. byte_offset: 16 access: Read - fieldset: HMONR - name: MMONR description: ICACHE miss monitor register. byte_offset: 20 @@ -75,13 +74,6 @@ fieldset/FCR: description: Clear ERRF flag in SR. bit_offset: 2 bit_size: 1 -fieldset/HMONR: - description: ICACHE hit monitor register. - fields: - - name: HITMON - description: Hit monitor register. - bit_offset: 0 - bit_size: 32 fieldset/IER: description: ICACHE interrupt enable register. fields: diff --git a/data/registers/icache_v1_3crr.yaml b/data/registers/icache_v1_3crr.yaml index 77767ad..35e9081 100644 --- a/data/registers/icache_v1_3crr.yaml +++ b/data/registers/icache_v1_3crr.yaml @@ -23,7 +23,6 @@ block/ICACHE: description: ICACHE hit monitor register. byte_offset: 16 access: Read - fieldset: HMONR - name: MMONR description: ICACHE miss monitor register. byte_offset: 20 @@ -112,13 +111,6 @@ fieldset/FCR: description: Clear ERRF flag in SR. bit_offset: 2 bit_size: 1 -fieldset/HMONR: - description: ICACHE hit monitor register. - fields: - - name: HITMON - description: Hit monitor register. - bit_offset: 0 - bit_size: 32 fieldset/IER: description: ICACHE interrupt enable register. fields: diff --git a/data/registers/icache_v1_4crr.yaml b/data/registers/icache_v1_4crr.yaml index 52c4f72..d495b13 100644 --- a/data/registers/icache_v1_4crr.yaml +++ b/data/registers/icache_v1_4crr.yaml @@ -23,7 +23,6 @@ block/ICACHE: description: ICACHE hit monitor register. byte_offset: 16 access: Read - fieldset: HMONR - name: MMONR description: ICACHE miss monitor register. byte_offset: 20 @@ -112,13 +111,6 @@ fieldset/FCR: description: Clear ERRF flag in SR. bit_offset: 2 bit_size: 1 -fieldset/HMONR: - description: ICACHE hit monitor register. - fields: - - name: HITMON - description: Hit monitor register. - bit_offset: 0 - bit_size: 32 fieldset/IER: description: ICACHE interrupt enable register. fields: diff --git a/transforms/ICACHE.yaml b/transforms/ICACHE.yaml index 6d96e29..7e6e634 100644 --- a/transforms/ICACHE.yaml +++ b/transforms/ICACHE.yaml @@ -1,5 +1,8 @@ transforms: + - !DeleteFieldsets + from: HMONR + - !MergeFieldsets from: CRR\d to: CRR From 6b0d1a937b2e1ea4c7dae1233f4f3443837bbd80 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 22 Feb 2024 00:33:42 +0800 Subject: [PATCH 5/6] remove unneeded enum --- data/registers/icache_v1_0crr.yaml | 21 --------------------- data/registers/icache_v1_3crr.yaml | 21 --------------------- data/registers/icache_v1_4crr.yaml | 21 --------------------- transforms/ICACHE.yaml | 3 +++ 4 files changed, 3 insertions(+), 63 deletions(-) diff --git a/data/registers/icache_v1_0crr.yaml b/data/registers/icache_v1_0crr.yaml index 589e529..d97ac61 100644 --- a/data/registers/icache_v1_0crr.yaml +++ b/data/registers/icache_v1_0crr.yaml @@ -39,7 +39,6 @@ fieldset/CR: description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. bit_offset: 1 bit_size: 1 - enum: CACHEINV - name: WAYSEL description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). bit_offset: 2 @@ -57,12 +56,10 @@ fieldset/CR: description: Hit monitor reset. bit_offset: 18 bit_size: 1 - enum: HITMRST - name: MISSMRST description: Miss monitor reset. bit_offset: 19 bit_size: 1 - enum: MISSMRST fieldset/FCR: description: ICACHE flag clear register. fields: @@ -107,24 +104,6 @@ fieldset/SR: description: an error occurred during the operation. bit_offset: 2 bit_size: 1 -enum/CACHEINV: - bit_size: 1 - variants: - - name: Invalidate - description: Invalidate entire cache - value: 1 -enum/HITMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache hit monitor - value: 1 -enum/MISSMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache miss monitor - value: 1 enum/WAYSEL: bit_size: 1 variants: diff --git a/data/registers/icache_v1_3crr.yaml b/data/registers/icache_v1_3crr.yaml index 35e9081..940b6ac 100644 --- a/data/registers/icache_v1_3crr.yaml +++ b/data/registers/icache_v1_3crr.yaml @@ -46,7 +46,6 @@ fieldset/CR: description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. bit_offset: 1 bit_size: 1 - enum: CACHEINV - name: WAYSEL description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). bit_offset: 2 @@ -64,12 +63,10 @@ fieldset/CR: description: Hit monitor reset. bit_offset: 18 bit_size: 1 - enum: HITMRST - name: MISSMRST description: Miss monitor reset. bit_offset: 19 bit_size: 1 - enum: MISSMRST fieldset/CRR: description: ICACHE region configuration register. fields: @@ -144,12 +141,6 @@ fieldset/SR: description: an error occurred during the operation. bit_offset: 2 bit_size: 1 -enum/CACHEINV: - bit_size: 1 - variants: - - name: Invalidate - description: Invalidate entire cache - value: 1 enum/HBURST: bit_size: 1 variants: @@ -157,18 +148,6 @@ enum/HBURST: value: 0 - name: Increment value: 1 -enum/HITMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache hit monitor - value: 1 -enum/MISSMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache miss monitor - value: 1 enum/MSTSEL: bit_size: 1 variants: diff --git a/data/registers/icache_v1_4crr.yaml b/data/registers/icache_v1_4crr.yaml index d495b13..629fd77 100644 --- a/data/registers/icache_v1_4crr.yaml +++ b/data/registers/icache_v1_4crr.yaml @@ -46,7 +46,6 @@ fieldset/CR: description: Set by software and cleared by hardware when the BUSYF flag is set (during cache maintenance operation). Writing 0 has no effect. bit_offset: 1 bit_size: 1 - enum: CACHEINV - name: WAYSEL description: This bit allows user to choose ICACHE set-associativity. It can be written by software only when cache is disabled (EN = 0). bit_offset: 2 @@ -64,12 +63,10 @@ fieldset/CR: description: Hit monitor reset. bit_offset: 18 bit_size: 1 - enum: HITMRST - name: MISSMRST description: Miss monitor reset. bit_offset: 19 bit_size: 1 - enum: MISSMRST fieldset/CRR: description: ICACHE region configuration register. fields: @@ -144,12 +141,6 @@ fieldset/SR: description: an error occurred during the operation. bit_offset: 2 bit_size: 1 -enum/CACHEINV: - bit_size: 1 - variants: - - name: Invalidate - description: Invalidate entire cache - value: 1 enum/HBURST: bit_size: 1 variants: @@ -157,18 +148,6 @@ enum/HBURST: value: 0 - name: Increment value: 1 -enum/HITMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache hit monitor - value: 1 -enum/MISSMRST: - bit_size: 1 - variants: - - name: Reset - description: Reset cache miss monitor - value: 1 enum/MSTSEL: bit_size: 1 variants: diff --git a/transforms/ICACHE.yaml b/transforms/ICACHE.yaml index 7e6e634..3b9a87c 100644 --- a/transforms/ICACHE.yaml +++ b/transforms/ICACHE.yaml @@ -1,5 +1,8 @@ transforms: + - !DeleteEnums + from: ^(CACHEINV|HITMRST|MISSMRST)$ + - !DeleteFieldsets from: HMONR From 0e673ac3f19126ef792adb752cae4c403c1c62c4 Mon Sep 17 00:00:00 2001 From: eZio Pan Date: Thu, 22 Feb 2024 00:36:40 +0800 Subject: [PATCH 6/6] type less --- data/registers/icache_v1_3crr.yaml | 14 +++++++------- data/registers/icache_v1_4crr.yaml | 14 +++++++------- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/data/registers/icache_v1_3crr.yaml b/data/registers/icache_v1_3crr.yaml index 940b6ac..4c7fb5a 100644 --- a/data/registers/icache_v1_3crr.yaml +++ b/data/registers/icache_v1_3crr.yaml @@ -158,19 +158,19 @@ enum/MSTSEL: enum/RSIZE: bit_size: 3 variants: - - name: TwoMegabytes + - name: MegaBytes2 value: 1 - - name: FourMegabytes + - name: MegaBytes4 value: 2 - - name: EightMegabytes + - name: MegaBytes8 value: 3 - - name: SixteenMegabytes + - name: MegaBytes16 value: 4 - - name: ThirtyTwoMegabytes + - name: MegaBytes32 value: 5 - - name: SixtyFourMegabytes + - name: MegaBytes64 value: 6 - - name: OneTwentyEightMegabytes + - name: MegaBytes128 value: 7 enum/WAYSEL: bit_size: 1 diff --git a/data/registers/icache_v1_4crr.yaml b/data/registers/icache_v1_4crr.yaml index 629fd77..8b835f0 100644 --- a/data/registers/icache_v1_4crr.yaml +++ b/data/registers/icache_v1_4crr.yaml @@ -158,19 +158,19 @@ enum/MSTSEL: enum/RSIZE: bit_size: 3 variants: - - name: TwoMegabytes + - name: MegaBytes2 value: 1 - - name: FourMegabytes + - name: MegaBytes4 value: 2 - - name: EightMegabytes + - name: MegaBytes8 value: 3 - - name: SixteenMegabytes + - name: MegaBytes16 value: 4 - - name: ThirtyTwoMegabytes + - name: MegaBytes32 value: 5 - - name: SixtyFourMegabytes + - name: MegaBytes64 value: 6 - - name: OneTwentyEightMegabytes + - name: MegaBytes128 value: 7 enum/WAYSEL: bit_size: 1