Merge pull request #306 from adamgreig/g4-dac
Rework DAC support for all STM32s
This commit is contained in:
Dario Nieuwenhuis
GitHub
commit
7117ad49c0
@ -1,3 +1,5 @@
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# DAC v1, only used in RM0008 STM32F101/102/103/105/107.
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block/DAC:
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description: Digital-to-analog converter
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items:
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@ -32,15 +34,15 @@ block/DAC:
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byte_offset: 16
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fieldset: DHR8R
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- name: DHR12RD
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description: Dual DAC 12-bit right-aligned data holding register
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description: dual 12-bit right-aligned data holding register
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byte_offset: 32
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fieldset: DHR12RD
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- name: DHR12LD
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description: DUAL DAC 12-bit left aligned data holding register
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description: dual 12-bit left aligned data holding register
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byte_offset: 36
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fieldset: DHR12LD
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- name: DHR8RD
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description: DUAL DAC 8-bit right aligned data holding register
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description: dual 8-bit right aligned data holding register
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byte_offset: 40
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fieldset: DHR8RD
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- name: DOR
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@ -51,41 +53,39 @@ block/DAC:
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byte_offset: 44
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access: Read
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fieldset: DOR
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- name: SR
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description: status register
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byte_offset: 52
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fieldset: SR
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fieldset/CR:
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description: control register
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fields:
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- name: EN
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description: DAC channel enable
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description: channel enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: BOFF
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description: DAC channel output buffer disable
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description: channel output buffer disable
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TEN
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description: DAC channel trigger enable
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description: channel trigger enable
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bit_offset: 2
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TSEL1
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description: DAC channel 1 trigger selection
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- name: TSEL
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description: channel trigger selection
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bit_offset: 3
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bit_size: 3
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enum: TSEL1
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array:
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len: 2
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stride: 16
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- name: WAVE
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description: DAC channel noise/triangle wave generation enable
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description: channel noise/triangle wave generation enable
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bit_offset: 6
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bit_size: 2
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array:
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@ -93,43 +93,31 @@ fieldset/CR:
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stride: 16
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enum: WAVE
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- name: MAMP
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description: DAC channel mask/amplitude selector
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description: channel mask/amplitude selector
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bit_offset: 8
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bit_size: 4
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array:
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len: 2
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stride: 16
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- name: DMAEN
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description: DAC channel DMA enable
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description: channel DMA enable
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bit_offset: 12
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: DMAUDRIE
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description: DAC channel DMA Underrun Interrupt enable
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bit_offset: 13
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TSEL2
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description: DAC channel 2 trigger selection
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bit_offset: 19
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bit_size: 3
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enum: TSEL2
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fieldset/DHR12L:
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description: channel 12-bit left-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit left-aligned data
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description: channel 12-bit left-aligned data
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bit_offset: 4
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bit_size: 12
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fieldset/DHR12LD:
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description: DUAL DAC 12-bit left aligned data holding register
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description: dual 12-bit left aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit left-aligned data
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description: channel 12-bit left-aligned data
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bit_offset: 4
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bit_size: 12
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array:
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@ -139,14 +127,14 @@ fieldset/DHR12R:
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description: channel 12-bit right-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit right-aligned data
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description: channel 12-bit right-aligned data
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bit_offset: 0
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bit_size: 12
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fieldset/DHR12RD:
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description: Dual DAC 12-bit right-aligned data holding register
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description: dual 12-bit right-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit right-aligned data
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description: channel 12-bit right-aligned data
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bit_offset: 0
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bit_size: 12
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array:
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@ -156,14 +144,14 @@ fieldset/DHR8R:
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description: channel 8-bit right-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 8-bit right-aligned data
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description: channel 8-bit right-aligned data
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bit_offset: 0
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bit_size: 8
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fieldset/DHR8RD:
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description: DUAL DAC 8-bit right aligned data holding register
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description: dual 8-bit right aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 8-bit right-aligned data
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description: channel 8-bit right-aligned data
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bit_offset: 0
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bit_size: 8
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array:
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@ -173,80 +161,19 @@ fieldset/DOR:
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description: channel data output register
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fields:
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- name: DOR
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description: DAC channel data output
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description: channel data output
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bit_offset: 0
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bit_size: 12
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fieldset/SR:
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description: status register
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fields:
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- name: DMAUDR
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description: DAC channel DMA underrun flag
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bit_offset: 13
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bit_size: 1
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array:
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len: 2
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stride: 16
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fieldset/SWTRIGR:
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description: software trigger register
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fields:
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- name: SWTRIG
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description: DAC channel software trigger
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description: channel software trigger
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 1
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enum/TSEL1:
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bit_size: 3
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variants:
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- name: TIM6_TRGO
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description: Timer 6 TRGO event
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value: 0
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- name: TIM3_TRGO
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description: Timer 3 TRGO event
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value: 1
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- name: TIM7_TRGO
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description: Timer 7 TRGO event
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value: 2
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- name: TIM15_TRGO
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description: Timer 15 TRGO event
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value: 3
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- name: TIM2_TRGO
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description: Timer 2 TRGO event
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value: 4
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- name: EXTI9
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description: EXTI line9
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value: 6
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- name: SOFTWARE
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description: Software trigger
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value: 7
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enum/TSEL2:
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bit_size: 3
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variants:
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- name: TIM6_TRGO
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description: Timer 6 TRGO event
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value: 0
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- name: TIM8_TRGO
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description: Timer 8 TRGO event
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value: 1
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- name: TIM7_TRGO
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description: Timer 7 TRGO event
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value: 2
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- name: TIM5_TRGO
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description: Timer 5 TRGO event
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value: 3
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- name: TIM2_TRGO
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description: Timer 2 TRGO event
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value: 4
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- name: TIM4_TRGO
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description: Timer 4 TRGO event
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value: 5
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- name: EXTI9
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description: EXTI line9
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value: 6
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- name: SOFTWARE
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description: Software trigger
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value: 7
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enum/WAVE:
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bit_size: 2
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variants:
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@ -1,3 +1,6 @@
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# DAC v2, used in F100, F0, F2, F4, F7, L0, L1.
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# Adds SR with DMAUDR1/2 fields, and adds DMAUDRIE1/2 fields to CR.
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block/DAC:
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description: Digital-to-analog converter
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items:
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@ -32,15 +35,15 @@ block/DAC:
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byte_offset: 16
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fieldset: DHR8R
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- name: DHR12RD
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description: Dual DAC 12-bit right-aligned data holding register
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description: dual 12-bit right-aligned data holding register
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byte_offset: 32
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fieldset: DHR12RD
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- name: DHR12LD
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description: DUAL DAC 12-bit left aligned data holding register
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description: dual 12-bit left aligned data holding register
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byte_offset: 36
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fieldset: DHR12LD
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- name: DHR8RD
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description: DUAL DAC 8-bit right aligned data holding register
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description: dual 8-bit right aligned data holding register
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byte_offset: 40
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fieldset: DHR8RD
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- name: DOR
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@ -55,64 +58,39 @@ block/DAC:
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description: status register
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byte_offset: 52
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fieldset: SR
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- name: CCR
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description: calibration control register
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byte_offset: 56
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fieldset: CCR
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- name: MCR
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description: mode control register
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byte_offset: 60
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fieldset: MCR
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- name: SHSR1
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description: Sample and Hold sample time register
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array:
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len: 2
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stride: 4
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byte_offset: 64
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fieldset: SHSR
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- name: SHHR
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description: Sample and Hold hold time register
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byte_offset: 72
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fieldset: SHHR
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- name: SHRR
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description: Sample and Hold refresh time register
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byte_offset: 76
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fieldset: SHRR
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fieldset/CCR:
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description: calibration control register
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fields:
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- name: OTRIM1
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description: DAC Channel 1 offset trimming value
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bit_offset: 0
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bit_size: 5
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- name: OTRIM2
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description: DAC Channel 2 offset trimming value
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bit_offset: 16
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bit_size: 5
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fieldset/CR:
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description: control register
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fields:
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- name: EN
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description: DAC channel enable
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description: channel enable
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bit_offset: 0
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: BOFF
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description: channel output buffer disable
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bit_offset: 1
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TEN
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description: DAC channel trigger enable
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description: channel trigger enable
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bit_offset: 2
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TSEL1
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description: DAC channel 1 trigger selection
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- name: TSEL
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description: channel trigger selection
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bit_offset: 3
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bit_size: 3
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enum: TSEL1
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array:
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len: 2
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stride: 16
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- name: WAVE
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description: DAC channel noise/triangle wave generation enable
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description: channel noise/triangle wave generation enable
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bit_offset: 6
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bit_size: 2
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array:
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@ -120,50 +98,38 @@ fieldset/CR:
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stride: 16
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enum: WAVE
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- name: MAMP
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description: DAC channel mask/amplitude selector
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description: channel mask/amplitude selector
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bit_offset: 8
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bit_size: 4
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array:
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len: 2
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stride: 16
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- name: DMAEN
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description: DAC channel DMA enable
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description: channel DMA enable
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bit_offset: 12
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: DMAUDRIE
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description: DAC channel DMA Underrun Interrupt enable
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description: channel DMA Underrun Interrupt enable
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bit_offset: 13
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: CEN
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description: DAC channel calibration enable
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bit_offset: 14
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bit_size: 1
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array:
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len: 2
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stride: 16
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- name: TSEL2
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description: DAC channel 2 trigger selection
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bit_offset: 19
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bit_size: 3
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enum: TSEL2
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fieldset/DHR12L:
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description: channel 12-bit left-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit left-aligned data
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description: channel 12-bit left-aligned data
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bit_offset: 4
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bit_size: 12
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fieldset/DHR12LD:
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description: DUAL DAC 12-bit left aligned data holding register
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description: dual 12-bit left aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit left-aligned data
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description: channel 12-bit left-aligned data
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bit_offset: 4
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bit_size: 12
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array:
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@ -173,14 +139,14 @@ fieldset/DHR12R:
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description: channel 12-bit right-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit right-aligned data
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description: channel 12-bit right-aligned data
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bit_offset: 0
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bit_size: 12
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fieldset/DHR12RD:
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description: Dual DAC 12-bit right-aligned data holding register
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description: dual 12-bit right-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 12-bit right-aligned data
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description: channel 12-bit right-aligned data
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bit_offset: 0
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bit_size: 12
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array:
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@ -190,14 +156,14 @@ fieldset/DHR8R:
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description: channel 8-bit right-aligned data holding register
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fields:
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- name: DHR
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description: DAC channel 8-bit right-aligned data
|
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description: channel 8-bit right-aligned data
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bit_offset: 0
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bit_size: 8
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fieldset/DHR8RD:
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description: DUAL DAC 8-bit right aligned data holding register
|
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description: dual 8-bit right aligned data holding register
|
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fields:
|
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- name: DHR
|
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description: DAC channel 8-bit right-aligned data
|
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description: channel 8-bit right-aligned data
|
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bit_offset: 0
|
||||
bit_size: 8
|
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array:
|
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@ -207,131 +173,29 @@ fieldset/DOR:
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description: channel data output register
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fields:
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- name: DOR
|
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description: DAC channel data output
|
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description: channel data output
|
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bit_offset: 0
|
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bit_size: 12
|
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fieldset/MCR:
|
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description: mode control register
|
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fields:
|
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- name: MODE
|
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description: DAC channel mode
|
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bit_offset: 0
|
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bit_size: 3
|
||||
array:
|
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len: 2
|
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stride: 16
|
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fieldset/SHHR:
|
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description: Sample and Hold hold time register
|
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fields:
|
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- name: THOLD
|
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description: DAC channel hold Time
|
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bit_offset: 0
|
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bit_size: 10
|
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array:
|
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len: 2
|
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stride: 16
|
||||
fieldset/SHRR:
|
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description: Sample and Hold refresh time register
|
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fields:
|
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- name: TREFRESH
|
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description: DAC channel refresh Time
|
||||
bit_offset: 0
|
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bit_size: 8
|
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array:
|
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len: 2
|
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stride: 16
|
||||
fieldset/SHSR:
|
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description: Sample and Hold sample time register
|
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fields:
|
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- name: TSAMPLE
|
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description: DAC channel sample Time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
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description: status register
|
||||
fields:
|
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- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
description: channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: DAC channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
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len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: DAC channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SWTRIGR:
|
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description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
description: channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/TSEL1:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM3_TRGO
|
||||
description: Timer 3 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
enum/TSEL2:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 0
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 1
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 2
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 3
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 4
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 5
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 6
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 7
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
|
||||
@ -1,3 +1,8 @@
|
||||
# DAC v3, only used in L4.
|
||||
# Adds CCR, MCR, SHSR, SHHR, SHRR registers.
|
||||
# Adds CEN fields to CR and BWST and CAL_FLAG fields to SR.
|
||||
# Deletes BOFF fields from CR.
|
||||
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
@ -32,15 +37,15 @@ block/DAC:
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
description: dual 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
description: dual 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
@ -63,56 +68,57 @@ block/DAC:
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR1
|
||||
description: Sample and Hold sample time register
|
||||
- name: SHSR
|
||||
description: sample and hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: Sample and Hold hold time register
|
||||
description: sample and hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: Sample and Hold refresh time register
|
||||
description: sample and hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
fieldset/CCR:
|
||||
description: calibration control register
|
||||
fields:
|
||||
- name: OTRIM1
|
||||
description: DAC Channel 1 offset trimming value
|
||||
- name: OTRIM
|
||||
description: channel offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
- name: OTRIM2
|
||||
description: DAC Channel 2 offset trimming value
|
||||
bit_offset: 16
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: DAC channel enable
|
||||
description: channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: DAC channel trigger enable
|
||||
bit_offset: 1
|
||||
description: channel trigger enable
|
||||
bit_offset: 2
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL1
|
||||
description: DAC channel 1 trigger selection
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
enum: TSEL1
|
||||
- name: TSEL
|
||||
description: channel trigger selection
|
||||
bit_offset: 3
|
||||
bit_size: 3
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: WAVE
|
||||
description: DAC channel noise/triangle wave generation enable
|
||||
description: channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
@ -120,21 +126,21 @@ fieldset/CR:
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: DAC channel mask/amplitude selector
|
||||
description: channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: DAC channel DMA enable
|
||||
description: channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: DAC channel DMA Underrun Interrupt enable
|
||||
description: channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
@ -147,23 +153,18 @@ fieldset/CR:
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL2
|
||||
description: DAC channel 2 trigger selection
|
||||
bit_offset: 18
|
||||
bit_size: 4
|
||||
enum: TSEL2
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: DUAL DAC 12-bit left aligned data holding register
|
||||
description: dual 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit left-aligned data
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
@ -173,14 +174,14 @@ fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: Dual DAC 12-bit right-aligned data holding register
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 12-bit right-aligned data
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
@ -190,14 +191,14 @@ fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: DUAL DAC 8-bit right aligned data holding register
|
||||
description: dual 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: DAC channel 8-bit right-aligned data
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
@ -207,7 +208,7 @@ fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: DAC channel data output
|
||||
description: channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/MCR:
|
||||
@ -217,55 +218,56 @@ fieldset/MCR:
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: MODE
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHHR:
|
||||
description: Sample and Hold hold time register
|
||||
description: sample and hold hold time register
|
||||
fields:
|
||||
- name: THOLD
|
||||
description: DAC channel hold Time
|
||||
description: channel hold time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHRR:
|
||||
description: Sample and Hold refresh time register
|
||||
description: sample and hold refresh time register
|
||||
fields:
|
||||
- name: TREFRESH
|
||||
description: DAC channel refresh Time
|
||||
description: channel refresh time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHSR:
|
||||
description: Sample and Hold sample time register
|
||||
description: sample and hold sample time register
|
||||
fields:
|
||||
- name: TSAMPLE
|
||||
description: DAC channel sample Time
|
||||
description: channel sample time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DMAUDR
|
||||
description: DAC channel DMA underrun flag
|
||||
description: channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: DAC channel calibration offset status
|
||||
description: channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: DAC channel busy writing sample time flag
|
||||
description: channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
@ -275,108 +277,39 @@ fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: DAC channel software trigger
|
||||
description: channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/TSEL1:
|
||||
bit_size: 4
|
||||
enum/MODE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
- name: NORMAL_EXT_BUFEN
|
||||
description: Normal mode, external pin only, buffer enabled
|
||||
value: 0
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
- name: NORMAL_EXT_INT_BUFEN
|
||||
description: Normal mode, external pin and internal peripherals, buffer enabled
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
- name: NORMAL_EXT_BUFDIS
|
||||
description: Normal mode, external pin only, buffer disabled
|
||||
value: 2
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
- name: NORMAL_INT_BUFDIS
|
||||
description: Normal mode, internal peripherals only, buffer disabled
|
||||
value: 3
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
- name: SAMPHOLD_EXT_BUFEN
|
||||
description: Sample and hold mode, external pin only, buffer enabled
|
||||
value: 4
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
- name: SAMPHOLD_EXT_INT_BUFEN
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer enabled
|
||||
value: 5
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
- name: SAMPHOLD_EXT_INT_BUFDIS
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer disabled
|
||||
value: 6
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
- name: SAMPHOLD_INT_BUFDIS
|
||||
description: Sample and hold mode, internal peripherals only, buffer disabled
|
||||
value: 7
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 8
|
||||
- name: HRTIM1_DACTRG1
|
||||
description: High resolution timer 1 DACTRG1 event
|
||||
value: 9
|
||||
- name: HRTIM1_DACTRG2
|
||||
description: High resolution timer 1 DACTRG2 event
|
||||
value: 10
|
||||
- name: LPTIM1_OUT
|
||||
description: Low-power timer 1 OUT event
|
||||
value: 11
|
||||
- name: LPTIM2_OUT
|
||||
description: Low-power timer 2 OUT event
|
||||
value: 12
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 13
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
enum/TSEL2:
|
||||
bit_size: 4
|
||||
variants:
|
||||
- name: SOFTWARE
|
||||
description: Software trigger
|
||||
value: 0
|
||||
- name: TIM1_TRGO
|
||||
description: Timer 1 TRGO event
|
||||
value: 1
|
||||
- name: TIM2_TRGO
|
||||
description: Timer 2 TRGO event
|
||||
value: 2
|
||||
- name: TIM4_TRGO
|
||||
description: Timer 4 TRGO event
|
||||
value: 3
|
||||
- name: TIM5_TRGO
|
||||
description: Timer 5 TRGO event
|
||||
value: 4
|
||||
- name: TIM6_TRGO
|
||||
description: Timer 6 TRGO event
|
||||
value: 5
|
||||
- name: TIM7_TRGO
|
||||
description: Timer 7 TRGO event
|
||||
value: 6
|
||||
- name: TIM8_TRGO
|
||||
description: Timer 8 TRGO event
|
||||
value: 7
|
||||
- name: TIM15_TRGO
|
||||
description: Timer 15 TRGO event
|
||||
value: 8
|
||||
- name: HRTIM1_DACTRG1
|
||||
description: High resolution timer 1 DACTRG1 event
|
||||
value: 9
|
||||
- name: HRTIM1_DACTRG2
|
||||
description: High resolution timer 1 DACTRG2 event
|
||||
value: 10
|
||||
- name: LPTIM1_OUT
|
||||
description: Low-power timer 1 OUT event
|
||||
value: 11
|
||||
- name: LPTIM2_OUT
|
||||
description: Low-power timer 2 OUT event
|
||||
value: 12
|
||||
- name: EXTI9
|
||||
description: EXTI line9
|
||||
value: 13
|
||||
- name: LPTIM3_OUT
|
||||
description: Low-power timer 3 OUT event
|
||||
value: 14
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
|
||||
322
data/registers/dac_v4.yaml
Normal file
322
data/registers/dac_v4.yaml
Normal file
@ -0,0 +1,322 @@
|
||||
# DAC v4, used in G0, H7, WL.
|
||||
# Moves CR.TEN to bit 1, extends CR.TSEL to be 4 bits (2 to 5).
|
||||
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: dual 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: dual 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR
|
||||
description: sample and hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: sample and hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: sample and hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
fieldset/CCR:
|
||||
description: calibration control register
|
||||
fields:
|
||||
- name: OTRIM
|
||||
description: channel offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: channel trigger enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL
|
||||
description: channel trigger selection
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: WAVE
|
||||
description: channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: dual 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: dual 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/MCR:
|
||||
description: mode control register
|
||||
fields:
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: MODE
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHHR:
|
||||
description: sample and hold hold time register
|
||||
fields:
|
||||
- name: THOLD
|
||||
description: channel hold time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHRR:
|
||||
description: sample and hold refresh time register
|
||||
fields:
|
||||
- name: TREFRESH
|
||||
description: channel refresh time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHSR:
|
||||
description: sample and hold sample time register
|
||||
fields:
|
||||
- name: TSAMPLE
|
||||
description: channel sample time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DMAUDR
|
||||
description: channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/MODE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NORMAL_EXT_BUFEN
|
||||
description: Normal mode, external pin only, buffer enabled
|
||||
value: 0
|
||||
- name: NORMAL_EXT_INT_BUFEN
|
||||
description: Normal mode, external pin and internal peripherals, buffer enabled
|
||||
value: 1
|
||||
- name: NORMAL_EXT_BUFDIS
|
||||
description: Normal mode, external pin only, buffer disabled
|
||||
value: 2
|
||||
- name: NORMAL_INT_BUFDIS
|
||||
description: Normal mode, internal peripherals only, buffer disabled
|
||||
value: 3
|
||||
- name: SAMPHOLD_EXT_BUFEN
|
||||
description: Sample and hold mode, external pin only, buffer enabled
|
||||
value: 4
|
||||
- name: SAMPHOLD_EXT_INT_BUFEN
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer enabled
|
||||
value: 5
|
||||
- name: SAMPHOLD_EXT_INT_BUFDIS
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer disabled
|
||||
value: 6
|
||||
- name: SAMPHOLD_INT_BUFDIS
|
||||
description: Sample and hold mode, internal peripherals only, buffer disabled
|
||||
value: 7
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
326
data/registers/dac_v5.yaml
Normal file
326
data/registers/dac_v5.yaml
Normal file
@ -0,0 +1,326 @@
|
||||
# DAC v5, used in L4+ and L5.
|
||||
# Adds HFSEL field to CR.
|
||||
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: dual 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: dual 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR
|
||||
description: sample and hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: sample and hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: sample and hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
fieldset/CCR:
|
||||
description: calibration control register
|
||||
fields:
|
||||
- name: OTRIM
|
||||
description: channel offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: channel trigger enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL
|
||||
description: channel trigger selection
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: WAVE
|
||||
description: channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: HFSEL
|
||||
description: high frequency interface mode enable
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: dual 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: dual 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
fieldset/MCR:
|
||||
description: mode control register
|
||||
fields:
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: MODE
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHHR:
|
||||
description: sample and hold hold time register
|
||||
fields:
|
||||
- name: THOLD
|
||||
description: channel hold time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHRR:
|
||||
description: sample and hold refresh time register
|
||||
fields:
|
||||
- name: TREFRESH
|
||||
description: channel refresh time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHSR:
|
||||
description: sample and hold sample time register
|
||||
fields:
|
||||
- name: TSAMPLE
|
||||
description: channel sample time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DMAUDR
|
||||
description: channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/MODE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NORMAL_EXT_BUFEN
|
||||
description: Normal mode, external pin only, buffer enabled
|
||||
value: 0
|
||||
- name: NORMAL_EXT_INT_BUFEN
|
||||
description: Normal mode, external pin and internal peripherals, buffer enabled
|
||||
value: 1
|
||||
- name: NORMAL_EXT_BUFDIS
|
||||
description: Normal mode, external pin only, buffer disabled
|
||||
value: 2
|
||||
- name: NORMAL_INT_BUFDIS
|
||||
description: Normal mode, internal peripherals only, buffer disabled
|
||||
value: 3
|
||||
- name: SAMPHOLD_EXT_BUFEN
|
||||
description: Sample and hold mode, external pin only, buffer enabled
|
||||
value: 4
|
||||
- name: SAMPHOLD_EXT_INT_BUFEN
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer enabled
|
||||
value: 5
|
||||
- name: SAMPHOLD_EXT_INT_BUFDIS
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer disabled
|
||||
value: 6
|
||||
- name: SAMPHOLD_INT_BUFDIS
|
||||
description: Sample and hold mode, internal peripherals only, buffer disabled
|
||||
value: 7
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
379
data/registers/dac_v6.yaml
Normal file
379
data/registers/dac_v6.yaml
Normal file
@ -0,0 +1,379 @@
|
||||
# DAC v6, used in H5 and U5.
|
||||
# Adds DMADOUBLE and SINFORMAT fields to MCR, DACRDY and DORSTAT fields to SR
|
||||
# Adds B data fields to data holding registers
|
||||
# Moves HFSEL from CR to MCR and makes it 2 bits.
|
||||
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: dual 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: dual 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR
|
||||
description: sample and hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: sample and hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: sample and hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
fieldset/CCR:
|
||||
description: calibration control register
|
||||
fields:
|
||||
- name: OTRIM
|
||||
description: channel offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: channel trigger enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL
|
||||
description: channel trigger selection
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: WAVE
|
||||
description: channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
- name: DHRB
|
||||
description: channel 12-bit left-aligned data B
|
||||
bit_offset: 20
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: dual 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DHRB
|
||||
description: channel 12-bit right-aligned data B
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: DHRB
|
||||
description: channel 8-bit right-aligned data B
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: dual 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DORB
|
||||
description: channel data output B
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
fieldset/MCR:
|
||||
description: mode control register
|
||||
fields:
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: MODE
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMADOUBLE
|
||||
description: channel DMA double data mode.
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: SINFORMAT
|
||||
description: enable signed format for DAC channel
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: HFSEL
|
||||
description: high frequency interface mode selection
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
fieldset/SHHR:
|
||||
description: sample and hold hold time register
|
||||
fields:
|
||||
- name: THOLD
|
||||
description: channel hold time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHRR:
|
||||
description: sample and hold refresh time register
|
||||
fields:
|
||||
- name: TREFRESH
|
||||
description: channel refresh time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHSR:
|
||||
description: sample and hold sample time register
|
||||
fields:
|
||||
- name: TSAMPLE
|
||||
description: channel sample time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DACRDY
|
||||
description: channel ready status bit
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DORSTAT
|
||||
description: channel output register status bit
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDR
|
||||
description: channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: SWTRIGB
|
||||
description: channel software trigger B
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/MODE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NORMAL_EXT_BUFEN
|
||||
description: Normal mode, external pin only, buffer enabled
|
||||
value: 0
|
||||
- name: NORMAL_EXT_INT_BUFEN
|
||||
description: Normal mode, external pin and internal peripherals, buffer enabled
|
||||
value: 1
|
||||
- name: NORMAL_EXT_BUFDIS
|
||||
description: Normal mode, external pin only, buffer disabled
|
||||
value: 2
|
||||
- name: NORMAL_INT_BUFDIS
|
||||
description: Normal mode, internal peripherals only, buffer disabled
|
||||
value: 3
|
||||
- name: SAMPHOLD_EXT_BUFEN
|
||||
description: Sample and hold mode, external pin only, buffer enabled
|
||||
value: 4
|
||||
- name: SAMPHOLD_EXT_INT_BUFEN
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer enabled
|
||||
value: 5
|
||||
- name: SAMPHOLD_EXT_INT_BUFDIS
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer disabled
|
||||
value: 6
|
||||
- name: SAMPHOLD_INT_BUFDIS
|
||||
description: Sample and hold mode, internal peripherals only, buffer disabled
|
||||
value: 7
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
423
data/registers/dac_v7.yaml
Normal file
423
data/registers/dac_v7.yaml
Normal file
@ -0,0 +1,423 @@
|
||||
# DAC v7, used in G4.
|
||||
# Adds STR, STMODR for sawtooth control.
|
||||
|
||||
block/DAC:
|
||||
description: Digital-to-analog converter
|
||||
items:
|
||||
- name: CR
|
||||
description: control register
|
||||
byte_offset: 0
|
||||
fieldset: CR
|
||||
- name: SWTRIGR
|
||||
description: software trigger register
|
||||
byte_offset: 4
|
||||
access: Write
|
||||
fieldset: SWTRIGR
|
||||
- name: DHR12R
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 8
|
||||
fieldset: DHR12R
|
||||
- name: DHR12L
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 12
|
||||
fieldset: DHR12L
|
||||
- name: DHR8R
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
array:
|
||||
len: 2
|
||||
stride: 12
|
||||
byte_offset: 16
|
||||
fieldset: DHR8R
|
||||
- name: DHR12RD
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
byte_offset: 32
|
||||
fieldset: DHR12RD
|
||||
- name: DHR12LD
|
||||
description: dual 12-bit left aligned data holding register
|
||||
byte_offset: 36
|
||||
fieldset: DHR12LD
|
||||
- name: DHR8RD
|
||||
description: dual 8-bit right aligned data holding register
|
||||
byte_offset: 40
|
||||
fieldset: DHR8RD
|
||||
- name: DOR
|
||||
description: channel data output register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 44
|
||||
access: Read
|
||||
fieldset: DOR
|
||||
- name: SR
|
||||
description: status register
|
||||
byte_offset: 52
|
||||
fieldset: SR
|
||||
- name: CCR
|
||||
description: calibration control register
|
||||
byte_offset: 56
|
||||
fieldset: CCR
|
||||
- name: MCR
|
||||
description: mode control register
|
||||
byte_offset: 60
|
||||
fieldset: MCR
|
||||
- name: SHSR
|
||||
description: sample and hold sample time register
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
byte_offset: 64
|
||||
fieldset: SHSR
|
||||
- name: SHHR
|
||||
description: sample and hold hold time register
|
||||
byte_offset: 72
|
||||
fieldset: SHHR
|
||||
- name: SHRR
|
||||
description: sample and hold refresh time register
|
||||
byte_offset: 76
|
||||
fieldset: SHRR
|
||||
- name: STR
|
||||
description: Sawtooth register
|
||||
byte_offset: 88
|
||||
fieldset: STR
|
||||
array:
|
||||
len: 2
|
||||
stride: 4
|
||||
- name: STMODR
|
||||
description: Sawtooth Mode register
|
||||
byte_offset: 96
|
||||
fieldset: STMODR
|
||||
fieldset/CCR:
|
||||
description: calibration control register
|
||||
fields:
|
||||
- name: OTRIM
|
||||
description: channel offset trimming value
|
||||
bit_offset: 0
|
||||
bit_size: 5
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/CR:
|
||||
description: control register
|
||||
fields:
|
||||
- name: EN
|
||||
description: channel enable
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TEN
|
||||
description: channel trigger enable
|
||||
bit_offset: 1
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: TSEL
|
||||
description: channel trigger selection
|
||||
bit_offset: 2
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: WAVE
|
||||
description: channel noise/triangle wave generation enable
|
||||
bit_offset: 6
|
||||
bit_size: 2
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
enum: WAVE
|
||||
- name: MAMP
|
||||
description: channel mask/amplitude selector
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAEN
|
||||
description: channel DMA enable
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDRIE
|
||||
description: channel DMA Underrun Interrupt enable
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CEN
|
||||
description: DAC channel calibration enable
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12L:
|
||||
description: channel 12-bit left-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
- name: DHRB
|
||||
description: channel 12-bit left-aligned data B
|
||||
bit_offset: 20
|
||||
bit_size: 12
|
||||
fieldset/DHR12LD:
|
||||
description: dual 12-bit left aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit left-aligned data
|
||||
bit_offset: 4
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR12R:
|
||||
description: channel 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DHRB
|
||||
description: channel 12-bit right-aligned data B
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
fieldset/DHR12RD:
|
||||
description: dual 12-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 12-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/DHR8R:
|
||||
description: channel 8-bit right-aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
- name: DHRB
|
||||
description: channel 8-bit right-aligned data B
|
||||
bit_offset: 8
|
||||
bit_size: 8
|
||||
fieldset/DHR8RD:
|
||||
description: dual 8-bit right aligned data holding register
|
||||
fields:
|
||||
- name: DHR
|
||||
description: channel 8-bit right-aligned data
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 8
|
||||
fieldset/DOR:
|
||||
description: channel data output register
|
||||
fields:
|
||||
- name: DOR
|
||||
description: channel data output
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DORB
|
||||
description: channel data output B
|
||||
bit_offset: 16
|
||||
bit_size: 12
|
||||
fieldset/MCR:
|
||||
description: mode control register
|
||||
fields:
|
||||
- name: MODE
|
||||
description: DAC channel mode
|
||||
bit_offset: 0
|
||||
bit_size: 3
|
||||
enum: MODE
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMADOUBLE
|
||||
description: channel DMA double data mode.
|
||||
bit_offset: 8
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: SINFORMAT
|
||||
description: enable signed format for DAC channel
|
||||
bit_offset: 9
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: HFSEL
|
||||
description: high frequency interface mode selection
|
||||
bit_offset: 14
|
||||
bit_size: 2
|
||||
fieldset/SHHR:
|
||||
description: sample and hold hold time register
|
||||
fields:
|
||||
- name: THOLD
|
||||
description: channel hold time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHRR:
|
||||
description: sample and hold refresh time register
|
||||
fields:
|
||||
- name: TREFRESH
|
||||
description: channel refresh time
|
||||
bit_offset: 0
|
||||
bit_size: 8
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/SHSR:
|
||||
description: sample and hold sample time register
|
||||
fields:
|
||||
- name: TSAMPLE
|
||||
description: channel sample time
|
||||
bit_offset: 0
|
||||
bit_size: 10
|
||||
fieldset/SR:
|
||||
description: status register
|
||||
fields:
|
||||
- name: DACRDY
|
||||
description: channel ready status bit
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DORSTAT
|
||||
description: channel output register status bit
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: DMAUDR
|
||||
description: channel DMA underrun flag
|
||||
bit_offset: 13
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: CAL_FLAG
|
||||
description: channel calibration offset status
|
||||
bit_offset: 14
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: BWST
|
||||
description: channel busy writing sample time flag
|
||||
bit_offset: 15
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/STMODR:
|
||||
description: sawtooth mode register
|
||||
fields:
|
||||
- name: STRSTTRIGSEL
|
||||
description: channel sawtooth reset trigger selection
|
||||
bit_offset: 0
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
- name: STINCTRIGSEL
|
||||
description: channel sawtooth increment trigger selection
|
||||
bit_offset: 8
|
||||
bit_size: 4
|
||||
array:
|
||||
len: 2
|
||||
stride: 16
|
||||
fieldset/STR:
|
||||
description: sawtooth register
|
||||
fields:
|
||||
- name: RSTDATA
|
||||
description: channel sawtooth reset value.
|
||||
bit_offset: 0
|
||||
bit_size: 12
|
||||
- name: DIR
|
||||
description: channel sawtooth direction setting
|
||||
bit_offset: 12
|
||||
bit_size: 1
|
||||
- name: INCDATA
|
||||
description: channel sawtooth increment value (12.4 bit format)
|
||||
bit_offset: 16
|
||||
bit_size: 16
|
||||
fieldset/SWTRIGR:
|
||||
description: software trigger register
|
||||
fields:
|
||||
- name: SWTRIG
|
||||
description: channel software trigger
|
||||
bit_offset: 0
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
- name: SWTRIGB
|
||||
description: channel software trigger B
|
||||
bit_offset: 16
|
||||
bit_size: 1
|
||||
array:
|
||||
len: 2
|
||||
stride: 1
|
||||
enum/MODE:
|
||||
bit_size: 3
|
||||
variants:
|
||||
- name: NORMAL_EXT_BUFEN
|
||||
description: Normal mode, external pin only, buffer enabled
|
||||
value: 0
|
||||
- name: NORMAL_EXT_INT_BUFEN
|
||||
description: Normal mode, external pin and internal peripherals, buffer enabled
|
||||
value: 1
|
||||
- name: NORMAL_EXT_BUFDIS
|
||||
description: Normal mode, external pin only, buffer disabled
|
||||
value: 2
|
||||
- name: NORMAL_INT_BUFDIS
|
||||
description: Normal mode, internal peripherals only, buffer disabled
|
||||
value: 3
|
||||
- name: SAMPHOLD_EXT_BUFEN
|
||||
description: Sample and hold mode, external pin only, buffer enabled
|
||||
value: 4
|
||||
- name: SAMPHOLD_EXT_INT_BUFEN
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer enabled
|
||||
value: 5
|
||||
- name: SAMPHOLD_EXT_INT_BUFDIS
|
||||
description: Sample and hold mode, external pin and internal peripherals, buffer disabled
|
||||
value: 6
|
||||
- name: SAMPHOLD_INT_BUFDIS
|
||||
description: Sample and hold mode, internal peripherals only, buffer disabled
|
||||
value: 7
|
||||
enum/WAVE:
|
||||
bit_size: 2
|
||||
variants:
|
||||
- name: Disabled
|
||||
description: Wave generation disabled
|
||||
value: 0
|
||||
- name: Noise
|
||||
description: Noise wave generation enabled
|
||||
value: 1
|
||||
- name: Triangle
|
||||
description: Triangle wave generation enabled
|
||||
value: 2
|
||||
- name: Sawtooth
|
||||
description: Sawtooth wave generation enabled
|
||||
value: 3
|
||||
@ -378,7 +378,7 @@ fieldset/AHB2ENR:
|
||||
description: "ADC1 and 2 peripherals clock enabled\r Set and reset by software."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DAC12EN
|
||||
- name: DAC1EN
|
||||
description: "DAC clock enable\r Set and reset by software."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
@ -457,7 +457,7 @@ fieldset/AHB2LPENR:
|
||||
description: "ADC1 and 2 peripherals clock enable during sleep mode\r Set and reset by software."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DAC12LPEN
|
||||
- name: DAC1LPEN
|
||||
description: "DAC clock enable during sleep mode\r Set and reset by software."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
@ -536,7 +536,7 @@ fieldset/AHB2RSTR:
|
||||
description: "ADC1 and 2 blocks reset\r Set and reset by software."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DAC12RST
|
||||
- name: DAC1RST
|
||||
description: "DAC block reset\r Set and reset by software."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
|
||||
@ -270,7 +270,7 @@ fieldset/AHB2ENR:
|
||||
description: "ADC1 peripherals clock enabled\r Set and reset by software."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DAC12EN
|
||||
- name: DAC1EN
|
||||
description: "DAC clock enable\r Set and reset by software."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
@ -313,7 +313,7 @@ fieldset/AHB2LPENR:
|
||||
description: "ADC1 peripherals clock enable during sleep mode\r Set and reset by software."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DAC12LPEN
|
||||
- name: DAC1LPEN
|
||||
description: "DAC clock enable during sleep mode\r Set and reset by software."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
@ -356,7 +356,7 @@ fieldset/AHB2RSTR:
|
||||
description: "ADC1 block reset\r Set and reset by software."
|
||||
bit_offset: 10
|
||||
bit_size: 1
|
||||
- name: DAC12RST
|
||||
- name: DAC1RST
|
||||
description: "DAC block reset\r Set and reset by software."
|
||||
bit_offset: 11
|
||||
bit_size: 1
|
||||
|
||||
@ -417,8 +417,8 @@ fieldset/APB1ENR1:
|
||||
description: CPU1 I2C3 clocks enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DAC1EN
|
||||
description: CPU1 DAC1 clock enable
|
||||
- name: DACEN
|
||||
description: CPU1 DAC clock enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LPTIM1EN
|
||||
@ -468,7 +468,7 @@ fieldset/APB1RSTR1:
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DACRST
|
||||
description: DAC1 reset
|
||||
description: DAC reset
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LPTIM1RST
|
||||
@ -526,7 +526,7 @@ fieldset/APB1SMENR1:
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DACSMEN
|
||||
description: DAC1 clock enable during CPU1 CSleep mode.
|
||||
description: DAC clock enable during CPU1 CSleep mode.
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LPTIM1SMEN
|
||||
@ -868,8 +868,8 @@ fieldset/C2APB1ENR1:
|
||||
description: CPU2 I2C3 clocks enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DAC1EN
|
||||
description: CPU2 DAC1 clock enable
|
||||
- name: DACEN
|
||||
description: CPU2 DAC clock enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LPTIM1EN
|
||||
@ -922,8 +922,8 @@ fieldset/C2APB1SMENR1:
|
||||
description: I2C3 clock enable during CPU2 CSleep and CStop modes
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DAC1SMEN
|
||||
description: DAC1 clock enable during CPU2 CSleep mode.
|
||||
- name: DACSMEN
|
||||
description: DAC clock enable during CPU2 CSleep mode.
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LPTIM1SMEN
|
||||
|
||||
@ -353,8 +353,8 @@ fieldset/APB1ENR1:
|
||||
description: CPU1 I2C3 clocks enable
|
||||
bit_offset: 23
|
||||
bit_size: 1
|
||||
- name: DAC1EN
|
||||
description: CPU1 DAC1 clock enable
|
||||
- name: DACEN
|
||||
description: CPU1 DAC clock enable
|
||||
bit_offset: 29
|
||||
bit_size: 1
|
||||
- name: LPTIM1EN
|
||||
|
||||
@ -176,12 +176,19 @@ impl PeriMatcher {
|
||||
(".*:I2C:F0-i2c2_v1_1", ("i2c", "v2", "I2C")),
|
||||
(".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")),
|
||||
(".*:I2C:i2c2_v1_1U5", ("i2c", "v2", "I2C")),
|
||||
(".*:DAC:dacif_v1_1", ("dac", "v1", "DAC")),
|
||||
(".*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")),
|
||||
(".*:DAC:F0dacif_v1_1", ("dac", "v1", "DAC")),
|
||||
(".*:DAC:dacif_v2_0", ("dac", "v2", "DAC")),
|
||||
(".*:DAC:dacif_v3_0", ("dac", "v3", "DAC")),
|
||||
(".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")),
|
||||
("STM32F10[1357].*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")), // Original F1 are v1
|
||||
(".*:DAC:dacif_v1_1F1", ("dac", "v2", "DAC")),
|
||||
(".*:DAC:F0dacif_v1_1", ("dac", "v2", "DAC")),
|
||||
(".*:DAC:F3_dacif_v1_1", ("dac", "v2", "DAC")),
|
||||
(".*:DAC:dacif_v1_1", ("dac", "v2", "DAC")),
|
||||
(".*:DAC:dacif_v1_2", ("dac", "v2", "DAC")),
|
||||
("STM32L4[1-9A].*:DAC:dacif_v2_0", ("dac", "v3", "DAC")), // L4 non-plus are v3
|
||||
(".*:DAC:dacif_v2_0", ("dac", "v5", "DAC")),
|
||||
(".*:DAC:dacif_v2_0_U5", ("dac", "v6", "DAC")),
|
||||
(".*:DAC:dacif_v3_0", ("dac", "v4", "DAC")),
|
||||
(".*:DAC:WL_dacif_v3_0", ("dac", "v4", "DAC")),
|
||||
(".*:DAC:G4_dacif_v4_0", ("dac", "v7", "DAC")),
|
||||
(".*:DAC:dacif_v5_0", ("dac", "v6", "DAC")),
|
||||
(".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")),
|
||||
(".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")),
|
||||
(".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")),
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user