From 7ce7dc901f7cd5e05823a39160166ecdb83943a9 Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Mon, 6 Nov 2023 03:00:36 +0000 Subject: [PATCH 1/5] Add DACv4 support for STM32G4 --- data/registers/dac_v4.yaml | 475 ++++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 1 + 2 files changed, 476 insertions(+) create mode 100644 data/registers/dac_v4.yaml diff --git a/data/registers/dac_v4.yaml b/data/registers/dac_v4.yaml new file mode 100644 index 0000000..e7c7576 --- /dev/null +++ b/data/registers/dac_v4.yaml @@ -0,0 +1,475 @@ +block/DAC: + description: Digital-to-analog converter + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SWTRIGR + description: software trigger register + byte_offset: 4 + access: Write + fieldset: SWTRIGR + - name: DHR12R + description: channel 12-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 8 + fieldset: DHR12R + - name: DHR12L + description: channel 12-bit left-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 12 + fieldset: DHR12L + - name: DHR8R + description: channel 8-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 16 + fieldset: DHR8R + - name: DHR12RD + description: Dual DAC 12-bit right-aligned data holding register + byte_offset: 32 + fieldset: DHR12RD + - name: DHR12LD + description: DUAL DAC 12-bit left aligned data holding register + byte_offset: 36 + fieldset: DHR12LD + - name: DHR8RD + description: DUAL DAC 8-bit right aligned data holding register + byte_offset: 40 + fieldset: DHR8RD + - name: DOR + description: channel data output register + array: + len: 2 + stride: 4 + byte_offset: 44 + access: Read + fieldset: DOR + - name: SR + description: status register + byte_offset: 52 + fieldset: SR + - name: CCR + description: calibration control register + byte_offset: 56 + fieldset: CCR + - name: MCR + description: mode control register + byte_offset: 60 + fieldset: MCR + - name: SHSR1 + description: Sample and Hold sample time register + array: + len: 2 + stride: 4 + byte_offset: 64 + fieldset: SHSR + - name: SHHR + description: Sample and Hold hold time register + byte_offset: 72 + fieldset: SHHR + - name: SHRR + description: Sample and Hold refresh time register + byte_offset: 76 + fieldset: SHRR + - name: STR + description: Sawtooth register + byte_offset: 88 + fieldset: STR + array: + len: 2 + stride: 4 + - name: STMODR + description: Sawtooth Mode register + byte_offset: 96 + fieldset: STMODR +fieldset/CCR: + description: calibration control register + fields: + - name: OTRIM1 + description: DAC Channel 1 offset trimming value + bit_offset: 0 + bit_size: 5 + - name: OTRIM2 + description: DAC Channel 2 offset trimming value + bit_offset: 16 + bit_size: 5 +fieldset/CR: + description: control register + fields: + - name: EN + description: DAC channel enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TEN + description: DAC channel trigger enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TSEL + description: DAC channel 1 trigger selection + bit_offset: 2 + bit_size: 4 + enum: TSEL + array: + len: 2 + stride: 16 + - name: WAVE + description: DAC channel noise/triangle wave generation enable + bit_offset: 6 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: WAVE + - name: MAMP + description: DAC channel mask/amplitude selector + bit_offset: 8 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: DMAEN + description: DAC channel DMA enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DMAUDRIE + description: DAC channel DMA Underrun Interrupt enable + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CEN + description: DAC channel calibration enable + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/DHR12L: + description: channel 12-bit left-aligned data holding register + fields: + - name: DHR + description: DAC channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + - name: DHRB + description: DAC channel 12-bit left-aligned data B. + bit_offset: 20 + bit_size: 12 +fieldset/DHR12LD: + description: DUAL DAC 12-bit left aligned data holding register + fields: + - name: DHR + description: DAC channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR12R: + description: channel 12-bit right-aligned data holding register + fields: + - name: DHR + description: DAC channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + - name: DHRB + description: channel 12-bit right-aligned data B + bit_offset: 16 + bit_size: 12 +fieldset/DHR12RD: + description: Dual DAC 12-bit right-aligned data holding register + fields: + - name: DHR + description: DAC channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR8R: + description: channel 8-bit right-aligned data holding register + fields: + - name: DHR + description: DAC channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + - name: DHRB + description: DAC channel 8-bit right-aligned data B + bit_offset: 8 + bit_size: 8 +fieldset/DHR8RD: + description: DUAL DAC 8-bit right aligned data holding register + fields: + - name: DHR + description: DAC channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 8 +fieldset/DOR: + description: channel data output register + fields: + - name: DOR + description: DAC channel data output + bit_offset: 0 + bit_size: 12 + - name: DORB + description: DAC channel data output B + bit_offset: 16 + bit_size: 12 +fieldset/MCR: + description: mode control register + fields: + - name: MODE + description: DAC channel mode + bit_offset: 0 + bit_size: 3 + enum: MODE + array: + len: 2 + stride: 16 + - name: DMADOUBLE + description: DAC Channel1 DMA double data mode. + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: SINFORMAT + description: Enable signed format for DAC channel1. + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: HFSEL + description: High frequency interface mode selection. + bit_offset: 14 + bit_size: 2 +fieldset/SHHR: + description: Sample and Hold hold time register + fields: + - name: THOLD + description: DAC channel hold Time + bit_offset: 0 + bit_size: 10 + array: + len: 2 + stride: 16 +fieldset/SHRR: + description: Sample and Hold refresh time register + fields: + - name: TREFRESH + description: DAC channel refresh Time + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 16 +fieldset/SHSR: + description: Sample and Hold sample time register + fields: + - name: TSAMPLE + description: DAC channel sample Time + bit_offset: 0 + bit_size: 10 +fieldset/SR: + description: status register + fields: + - name: DACRDY + description: DAC channel ready status bit. + bit_offset: 11 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DORSTAT + description: DAC channel output register status bit. + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DMAUDR + description: DAC channel DMA underrun flag + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CAL_FLAG + description: DAC channel calibration offset status + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: BWST + description: DAC channel busy writing sample time flag + bit_offset: 15 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/STMODR: + description: Sawtooth Mode register. + fields: + - name: STRSTTRIGSEL1 + description: DAC Channel 1 Sawtooth Reset trigger selection. + bit_offset: 0 + bit_size: 4 + - name: STINCTRIGSEL1 + description: DAC Channel 1 Sawtooth Increment trigger selection. + bit_offset: 8 + bit_size: 4 + - name: STRSTTRIGSEL2 + description: DAC Channel 1 Sawtooth Reset trigger selection. + bit_offset: 16 + bit_size: 4 + - name: STINCTRIGSEL2 + description: DAC Channel 2 Sawtooth Increment trigger selection. + bit_offset: 24 + bit_size: 4 +fieldset/STR: + description: Sawtooth register. + fields: + - name: RSTDATA + description: DAC Channel Sawtooth reset value. + bit_offset: 0 + bit_size: 12 + - name: DIR + description: DAC Channel Sawtooth direction setting. + bit_offset: 12 + bit_size: 1 + - name: INCDATA + description: DAC Sawtooth increment value (12.4 bit format) + bit_offset: 16 + bit_size: 16 +fieldset/SWTRIGR: + description: DAC software trigger register. + fields: + - name: SWTRIG + description: 'DAC channel software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DHR1 register value has been loaded into the DOR1 register.' + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SWTRIGB + description: DAC channel software trigger B. + bit_offset: 16 + bit_size: 1 + array: + len: 2 + stride: 1 +enum/MODE: + bit_size: 3 + variants: + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 +enum/TSEL: + bit_size: 4 + variants: + - name: SOFTWARE + description: Software trigger + value: 0 + - name: TIM8_TIM1_TRGO + description: TIM8 (DAC1/2/4) or TIM1 (DAC3) trigger output + value: 1 + - name: TIM7_TRGO + description: TIM7 trigger output + value: 2 + - name: TIM15_TRGO + description: TIM15 trigger output + value: 3 + - name: TIM2_TRGO + description: TIM2 trigger otuput + value: 4 + - name: TIM4_TRGO + description: TIM4 trigger output + value: 5 + - name: EXTI9 + description: external pin + value: 6 + - name: TIM6_TRGO + description: TIM6 trigger output + value: 7 + - name: TIM3_TRGO + description: TIM3 trigger output + value: 8 + - name: HRTIM_DAC_RESET_TRG1 + description: HRTIM dual channel DAC trigger 1 + value: 9 + - name: HRTIM_DAC_RESET_TRG2 + description: HRTIM dual channel DAC trigger 2 + value: 10 + - name: HRTIM_DAC_RESET_TRG3 + description: HRTIM dual channel DAC trigger 3 + value: 11 + - name: HRTIM_DAC_RESET_TRG4 + description: HRTIM dual channel DAC trigger 4 + value: 12 + - name: HRTIM_DAC_RESET_TRG5 + description: HRTIM dual channel DAC trigger 5 + value: 13 + - name: HRTIM_DAC_RESET_TRG6 + description: HRTIM dual channel DAC trigger 6 + value: 14 + - name: HRTIM_DAC_TRG1_2_3 + description: HRTIM DAC trigger 1 (DAC1/DAC4), 2 (DAC2), 3 (DAC3) + value: 15 +enum/WAVE: + bit_size: 2 + variants: + - name: Disabled + description: Wave generation disabled + value: 0 + - name: Noise + description: Noise wave generation enabled + value: 1 + - name: Triangle + description: Triangle wave generation enabled + value: 2 + - name: Sawtooth + description: Sawtooth wave generation enabled + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index 82bb4e7..bf977ad 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -182,6 +182,7 @@ impl PeriMatcher { (".*:DAC:dacif_v2_0", ("dac", "v2", "DAC")), (".*:DAC:dacif_v3_0", ("dac", "v3", "DAC")), (".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")), + (".*:DAC:G4_dacif_v4_0", ("dac", "v4", "DAC")), (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")), (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")), (".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")), From 82101c985cb957b3de12d99b0ffc0a92850d6575 Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Sun, 12 Nov 2023 22:49:11 +0000 Subject: [PATCH 2/5] DAC v1-4: Remove TSEL enum from TSEL fields, arrayify TSEL fields --- data/registers/dac_v1.yaml | 62 ++--------------- data/registers/dac_v2.yaml | 86 +++++++++--------------- data/registers/dac_v3.yaml | 133 +++++++++---------------------------- data/registers/dac_v4.yaml | 56 +--------------- 4 files changed, 67 insertions(+), 270 deletions(-) diff --git a/data/registers/dac_v1.yaml b/data/registers/dac_v1.yaml index 1ef1857..8944f2a 100644 --- a/data/registers/dac_v1.yaml +++ b/data/registers/dac_v1.yaml @@ -79,11 +79,13 @@ fieldset/CR: array: len: 2 stride: 16 - - name: TSEL1 + - name: TSEL description: DAC channel 1 trigger selection bit_offset: 3 bit_size: 3 - enum: TSEL1 + array: + len: 2 + stride: 16 - name: WAVE description: DAC channel noise/triangle wave generation enable bit_offset: 6 @@ -113,11 +115,6 @@ fieldset/CR: array: len: 2 stride: 16 - - name: TSEL2 - description: DAC channel 2 trigger selection - bit_offset: 19 - bit_size: 3 - enum: TSEL2 fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: @@ -196,57 +193,6 @@ fieldset/SWTRIGR: array: len: 2 stride: 1 -enum/TSEL1: - bit_size: 3 - variants: - - name: TIM6_TRGO - description: Timer 6 TRGO event - value: 0 - - name: TIM3_TRGO - description: Timer 3 TRGO event - value: 1 - - name: TIM7_TRGO - description: Timer 7 TRGO event - value: 2 - - name: TIM15_TRGO - description: Timer 15 TRGO event - value: 3 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 4 - - name: EXTI9 - description: EXTI line9 - value: 6 - - name: SOFTWARE - description: Software trigger - value: 7 -enum/TSEL2: - bit_size: 3 - variants: - - name: TIM6_TRGO - description: Timer 6 TRGO event - value: 0 - - name: TIM8_TRGO - description: Timer 8 TRGO event - value: 1 - - name: TIM7_TRGO - description: Timer 7 TRGO event - value: 2 - - name: TIM5_TRGO - description: Timer 5 TRGO event - value: 3 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 4 - - name: TIM4_TRGO - description: Timer 4 TRGO event - value: 5 - - name: EXTI9 - description: EXTI line9 - value: 6 - - name: SOFTWARE - description: Software trigger - value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v2.yaml b/data/registers/dac_v2.yaml index 348e410..05e4b23 100644 --- a/data/registers/dac_v2.yaml +++ b/data/registers/dac_v2.yaml @@ -106,11 +106,13 @@ fieldset/CR: array: len: 2 stride: 16 - - name: TSEL1 + - name: TSEL description: DAC channel 1 trigger selection bit_offset: 3 bit_size: 3 - enum: TSEL1 + array: + len: 2 + stride: 16 - name: WAVE description: DAC channel noise/triangle wave generation enable bit_offset: 6 @@ -147,11 +149,6 @@ fieldset/CR: array: len: 2 stride: 16 - - name: TSEL2 - description: DAC channel 2 trigger selection - bit_offset: 19 - bit_size: 3 - enum: TSEL2 fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: @@ -217,6 +214,7 @@ fieldset/MCR: description: DAC channel mode bit_offset: 0 bit_size: 3 + enum: MODE array: len: 2 stride: 16 @@ -281,57 +279,33 @@ fieldset/SWTRIGR: array: len: 2 stride: 1 -enum/TSEL1: +enum/MODE: bit_size: 3 variants: - - name: TIM6_TRGO - description: Timer 6 TRGO event - value: 0 - - name: TIM3_TRGO - description: Timer 3 TRGO event - value: 1 - - name: TIM7_TRGO - description: Timer 7 TRGO event - value: 2 - - name: TIM15_TRGO - description: Timer 15 TRGO event - value: 3 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 4 - - name: EXTI9 - description: EXTI line9 - value: 6 - - name: SOFTWARE - description: Software trigger - value: 7 -enum/TSEL2: - bit_size: 3 - variants: - - name: TIM6_TRGO - description: Timer 6 TRGO event - value: 0 - - name: TIM8_TRGO - description: Timer 8 TRGO event - value: 1 - - name: TIM7_TRGO - description: Timer 7 TRGO event - value: 2 - - name: TIM5_TRGO - description: Timer 5 TRGO event - value: 3 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 4 - - name: TIM4_TRGO - description: Timer 4 TRGO event - value: 5 - - name: EXTI9 - description: EXTI line9 - value: 6 - - name: SOFTWARE - description: Software trigger - value: 7 + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v3.yaml b/data/registers/dac_v3.yaml index e15ab44..85de74f 100644 --- a/data/registers/dac_v3.yaml +++ b/data/registers/dac_v3.yaml @@ -106,11 +106,13 @@ fieldset/CR: array: len: 2 stride: 16 - - name: TSEL1 + - name: TSEL description: DAC channel 1 trigger selection bit_offset: 2 bit_size: 4 - enum: TSEL1 + array: + len: 2 + stride: 16 - name: WAVE description: DAC channel noise/triangle wave generation enable bit_offset: 6 @@ -147,11 +149,6 @@ fieldset/CR: array: len: 2 stride: 16 - - name: TSEL2 - description: DAC channel 2 trigger selection - bit_offset: 18 - bit_size: 4 - enum: TSEL2 fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: @@ -217,6 +214,7 @@ fieldset/MCR: description: DAC channel mode bit_offset: 0 bit_size: 3 + enum: MODE array: len: 2 stride: 16 @@ -281,102 +279,33 @@ fieldset/SWTRIGR: array: len: 2 stride: 1 -enum/TSEL1: - bit_size: 4 +enum/MODE: + bit_size: 3 variants: - - name: SOFTWARE - description: Software trigger - value: 0 - - name: TIM1_TRGO - description: Timer 1 TRGO event - value: 1 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 2 - - name: TIM4_TRGO - description: Timer 4 TRGO event - value: 3 - - name: TIM5_TRGO - description: Timer 5 TRGO event - value: 4 - - name: TIM6_TRGO - description: Timer 6 TRGO event - value: 5 - - name: TIM7_TRGO - description: Timer 7 TRGO event - value: 6 - - name: TIM8_TRGO - description: Timer 8 TRGO event - value: 7 - - name: TIM15_TRGO - description: Timer 15 TRGO event - value: 8 - - name: HRTIM1_DACTRG1 - description: High resolution timer 1 DACTRG1 event - value: 9 - - name: HRTIM1_DACTRG2 - description: High resolution timer 1 DACTRG2 event - value: 10 - - name: LPTIM1_OUT - description: Low-power timer 1 OUT event - value: 11 - - name: LPTIM2_OUT - description: Low-power timer 2 OUT event - value: 12 - - name: EXTI9 - description: EXTI line9 - value: 13 - - name: LPTIM3_OUT - description: Low-power timer 3 OUT event - value: 14 -enum/TSEL2: - bit_size: 4 - variants: - - name: SOFTWARE - description: Software trigger - value: 0 - - name: TIM1_TRGO - description: Timer 1 TRGO event - value: 1 - - name: TIM2_TRGO - description: Timer 2 TRGO event - value: 2 - - name: TIM4_TRGO - description: Timer 4 TRGO event - value: 3 - - name: TIM5_TRGO - description: Timer 5 TRGO event - value: 4 - - name: TIM6_TRGO - description: Timer 6 TRGO event - value: 5 - - name: TIM7_TRGO - description: Timer 7 TRGO event - value: 6 - - name: TIM8_TRGO - description: Timer 8 TRGO event - value: 7 - - name: TIM15_TRGO - description: Timer 15 TRGO event - value: 8 - - name: HRTIM1_DACTRG1 - description: High resolution timer 1 DACTRG1 event - value: 9 - - name: HRTIM1_DACTRG2 - description: High resolution timer 1 DACTRG2 event - value: 10 - - name: LPTIM1_OUT - description: Low-power timer 1 OUT event - value: 11 - - name: LPTIM2_OUT - description: Low-power timer 2 OUT event - value: 12 - - name: EXTI9 - description: EXTI line9 - value: 13 - - name: LPTIM3_OUT - description: Low-power timer 3 OUT event - value: 14 + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v4.yaml b/data/registers/dac_v4.yaml index e7c7576..070de38 100644 --- a/data/registers/dac_v4.yaml +++ b/data/registers/dac_v4.yaml @@ -121,7 +121,6 @@ fieldset/CR: description: DAC channel 1 trigger selection bit_offset: 2 bit_size: 4 - enum: TSEL array: len: 2 stride: 16 @@ -364,10 +363,10 @@ fieldset/STR: bit_offset: 16 bit_size: 16 fieldset/SWTRIGR: - description: DAC software trigger register. + description: software trigger register fields: - name: SWTRIG - description: 'DAC channel software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DHR1 register value has been loaded into the DOR1 register.' + description: DAC channel software trigger bit_offset: 0 bit_size: 1 array: @@ -407,57 +406,6 @@ enum/MODE: - name: SAMPHOLD_INT_BUFDIS description: Sample and hold mode, internal peripherals only, buffer disabled value: 7 -enum/TSEL: - bit_size: 4 - variants: - - name: SOFTWARE - description: Software trigger - value: 0 - - name: TIM8_TIM1_TRGO - description: TIM8 (DAC1/2/4) or TIM1 (DAC3) trigger output - value: 1 - - name: TIM7_TRGO - description: TIM7 trigger output - value: 2 - - name: TIM15_TRGO - description: TIM15 trigger output - value: 3 - - name: TIM2_TRGO - description: TIM2 trigger otuput - value: 4 - - name: TIM4_TRGO - description: TIM4 trigger output - value: 5 - - name: EXTI9 - description: external pin - value: 6 - - name: TIM6_TRGO - description: TIM6 trigger output - value: 7 - - name: TIM3_TRGO - description: TIM3 trigger output - value: 8 - - name: HRTIM_DAC_RESET_TRG1 - description: HRTIM dual channel DAC trigger 1 - value: 9 - - name: HRTIM_DAC_RESET_TRG2 - description: HRTIM dual channel DAC trigger 2 - value: 10 - - name: HRTIM_DAC_RESET_TRG3 - description: HRTIM dual channel DAC trigger 3 - value: 11 - - name: HRTIM_DAC_RESET_TRG4 - description: HRTIM dual channel DAC trigger 4 - value: 12 - - name: HRTIM_DAC_RESET_TRG5 - description: HRTIM dual channel DAC trigger 5 - value: 13 - - name: HRTIM_DAC_RESET_TRG6 - description: HRTIM dual channel DAC trigger 6 - value: 14 - - name: HRTIM_DAC_TRG1_2_3 - description: HRTIM DAC trigger 1 (DAC1/DAC4), 2 (DAC2), 3 (DAC3) - value: 15 enum/WAVE: bit_size: 2 variants: From 78232c013ec540b744e9641d9195520ff9dd14d2 Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Wed, 15 Nov 2023 02:54:39 +0000 Subject: [PATCH 3/5] Rework DACs for all STM32 --- data/registers/dac_v1.yaml | 65 ++---- data/registers/dac_v2.yaml | 174 +++------------ data/registers/dac_v3.yaml | 90 ++++---- data/registers/dac_v4.yaml | 185 ++++------------ data/registers/dac_v5.yaml | 326 +++++++++++++++++++++++++++ data/registers/dac_v6.yaml | 379 ++++++++++++++++++++++++++++++++ data/registers/dac_v7.yaml | 423 ++++++++++++++++++++++++++++++++++++ stm32-data-gen/src/chips.rs | 20 +- 8 files changed, 1285 insertions(+), 377 deletions(-) create mode 100644 data/registers/dac_v5.yaml create mode 100644 data/registers/dac_v6.yaml create mode 100644 data/registers/dac_v7.yaml diff --git a/data/registers/dac_v1.yaml b/data/registers/dac_v1.yaml index 8944f2a..517625f 100644 --- a/data/registers/dac_v1.yaml +++ b/data/registers/dac_v1.yaml @@ -1,3 +1,5 @@ +# DAC v1, only used in RM0008 STM32F101/102/103/105/107. + block/DAC: description: Digital-to-analog converter items: @@ -32,15 +34,15 @@ block/DAC: byte_offset: 16 fieldset: DHR8R - name: DHR12RD - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register byte_offset: 32 fieldset: DHR12RD - name: DHR12LD - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register byte_offset: 36 fieldset: DHR12LD - name: DHR8RD - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register byte_offset: 40 fieldset: DHR8RD - name: DOR @@ -51,43 +53,39 @@ block/DAC: byte_offset: 44 access: Read fieldset: DOR - - name: SR - description: status register - byte_offset: 52 - fieldset: SR fieldset/CR: description: control register fields: - name: EN - description: DAC channel enable + description: channel enable bit_offset: 0 bit_size: 1 array: len: 2 stride: 16 - name: BOFF - description: DAC channel output buffer disable + description: channel output buffer disable bit_offset: 1 bit_size: 1 array: len: 2 stride: 16 - name: TEN - description: DAC channel trigger enable + description: channel trigger enable bit_offset: 2 bit_size: 1 array: len: 2 stride: 16 - name: TSEL - description: DAC channel 1 trigger selection + description: channel trigger selection bit_offset: 3 bit_size: 3 array: len: 2 stride: 16 - name: WAVE - description: DAC channel noise/triangle wave generation enable + description: channel noise/triangle wave generation enable bit_offset: 6 bit_size: 2 array: @@ -95,38 +93,31 @@ fieldset/CR: stride: 16 enum: WAVE - name: MAMP - description: DAC channel mask/amplitude selector + description: channel mask/amplitude selector bit_offset: 8 bit_size: 4 array: len: 2 stride: 16 - name: DMAEN - description: DAC channel DMA enable + description: channel DMA enable bit_offset: 12 bit_size: 1 array: len: 2 stride: 16 - - name: DMAUDRIE - description: DAC channel DMA Underrun Interrupt enable - bit_offset: 13 - bit_size: 1 - array: - len: 2 - stride: 16 fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 fieldset/DHR12LD: - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 array: @@ -136,14 +127,14 @@ fieldset/DHR12R: description: channel 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 fieldset/DHR12RD: - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 array: @@ -153,14 +144,14 @@ fieldset/DHR8R: description: channel 8-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 fieldset/DHR8RD: - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 array: @@ -170,24 +161,14 @@ fieldset/DOR: description: channel data output register fields: - name: DOR - description: DAC channel data output + description: channel data output bit_offset: 0 bit_size: 12 -fieldset/SR: - description: status register - fields: - - name: DMAUDR - description: DAC channel DMA underrun flag - bit_offset: 13 - bit_size: 1 - array: - len: 2 - stride: 16 fieldset/SWTRIGR: description: software trigger register fields: - name: SWTRIG - description: DAC channel software trigger + description: channel software trigger bit_offset: 0 bit_size: 1 array: diff --git a/data/registers/dac_v2.yaml b/data/registers/dac_v2.yaml index 05e4b23..94c369b 100644 --- a/data/registers/dac_v2.yaml +++ b/data/registers/dac_v2.yaml @@ -1,3 +1,6 @@ +# DAC v2, used in F100, F0, F2, F4, F7, L0, L1. +# Adds SR with DMAUDR1/2 fields, and adds DMAUDRIE1/2 fields to CR. + block/DAC: description: Digital-to-analog converter items: @@ -32,15 +35,15 @@ block/DAC: byte_offset: 16 fieldset: DHR8R - name: DHR12RD - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register byte_offset: 32 fieldset: DHR12RD - name: DHR12LD - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register byte_offset: 36 fieldset: DHR12LD - name: DHR8RD - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register byte_offset: 40 fieldset: DHR8RD - name: DOR @@ -55,66 +58,39 @@ block/DAC: description: status register byte_offset: 52 fieldset: SR - - name: CCR - description: calibration control register - byte_offset: 56 - fieldset: CCR - - name: MCR - description: mode control register - byte_offset: 60 - fieldset: MCR - - name: SHSR1 - description: Sample and Hold sample time register - array: - len: 2 - stride: 4 - byte_offset: 64 - fieldset: SHSR - - name: SHHR - description: Sample and Hold hold time register - byte_offset: 72 - fieldset: SHHR - - name: SHRR - description: Sample and Hold refresh time register - byte_offset: 76 - fieldset: SHRR -fieldset/CCR: - description: calibration control register - fields: - - name: OTRIM1 - description: DAC Channel 1 offset trimming value - bit_offset: 0 - bit_size: 5 - - name: OTRIM2 - description: DAC Channel 2 offset trimming value - bit_offset: 16 - bit_size: 5 fieldset/CR: description: control register fields: - name: EN - description: DAC channel enable + description: channel enable bit_offset: 0 bit_size: 1 array: len: 2 stride: 16 + - name: BOFF + description: channel output buffer disable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 - name: TEN - description: DAC channel trigger enable + description: channel trigger enable bit_offset: 2 bit_size: 1 array: len: 2 stride: 16 - name: TSEL - description: DAC channel 1 trigger selection + description: channel trigger selection bit_offset: 3 bit_size: 3 array: len: 2 stride: 16 - name: WAVE - description: DAC channel noise/triangle wave generation enable + description: channel noise/triangle wave generation enable bit_offset: 6 bit_size: 2 array: @@ -122,45 +98,38 @@ fieldset/CR: stride: 16 enum: WAVE - name: MAMP - description: DAC channel mask/amplitude selector + description: channel mask/amplitude selector bit_offset: 8 bit_size: 4 array: len: 2 stride: 16 - name: DMAEN - description: DAC channel DMA enable + description: channel DMA enable bit_offset: 12 bit_size: 1 array: len: 2 stride: 16 - name: DMAUDRIE - description: DAC channel DMA Underrun Interrupt enable + description: channel DMA Underrun Interrupt enable bit_offset: 13 bit_size: 1 array: len: 2 stride: 16 - - name: CEN - description: DAC channel calibration enable - bit_offset: 14 - bit_size: 1 - array: - len: 2 - stride: 16 fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 fieldset/DHR12LD: - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 array: @@ -170,14 +139,14 @@ fieldset/DHR12R: description: channel 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 fieldset/DHR12RD: - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 array: @@ -187,14 +156,14 @@ fieldset/DHR8R: description: channel 8-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 fieldset/DHR8RD: - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 array: @@ -204,108 +173,29 @@ fieldset/DOR: description: channel data output register fields: - name: DOR - description: DAC channel data output + description: channel data output bit_offset: 0 bit_size: 12 -fieldset/MCR: - description: mode control register - fields: - - name: MODE - description: DAC channel mode - bit_offset: 0 - bit_size: 3 - enum: MODE - array: - len: 2 - stride: 16 -fieldset/SHHR: - description: Sample and Hold hold time register - fields: - - name: THOLD - description: DAC channel hold Time - bit_offset: 0 - bit_size: 10 - array: - len: 2 - stride: 16 -fieldset/SHRR: - description: Sample and Hold refresh time register - fields: - - name: TREFRESH - description: DAC channel refresh Time - bit_offset: 0 - bit_size: 8 - array: - len: 2 - stride: 16 -fieldset/SHSR: - description: Sample and Hold sample time register - fields: - - name: TSAMPLE - description: DAC channel sample Time - bit_offset: 0 - bit_size: 10 fieldset/SR: description: status register fields: - name: DMAUDR - description: DAC channel DMA underrun flag + description: channel DMA underrun flag bit_offset: 13 bit_size: 1 array: len: 2 stride: 16 - - name: CAL_FLAG - description: DAC channel calibration offset status - bit_offset: 14 - bit_size: 1 - array: - len: 2 - stride: 16 - - name: BWST - description: DAC channel busy writing sample time flag - bit_offset: 15 - bit_size: 1 - array: - len: 2 - stride: 16 fieldset/SWTRIGR: description: software trigger register fields: - name: SWTRIG - description: DAC channel software trigger + description: channel software trigger bit_offset: 0 bit_size: 1 array: len: 2 stride: 1 -enum/MODE: - bit_size: 3 - variants: - - name: NORMAL_EXT_BUFEN - description: Normal mode, external pin only, buffer enabled - value: 0 - - name: NORMAL_EXT_INT_BUFEN - description: Normal mode, external pin and internal peripherals, buffer enabled - value: 1 - - name: NORMAL_EXT_BUFDIS - description: Normal mode, external pin only, buffer disabled - value: 2 - - name: NORMAL_INT_BUFDIS - description: Normal mode, internal peripherals only, buffer disabled - value: 3 - - name: SAMPHOLD_EXT_BUFEN - description: Sample and hold mode, external pin only, buffer enabled - value: 4 - - name: SAMPHOLD_EXT_INT_BUFEN - description: Sample and hold mode, external pin and internal peripherals, buffer enabled - value: 5 - - name: SAMPHOLD_EXT_INT_BUFDIS - description: Sample and hold mode, external pin and internal peripherals, buffer disabled - value: 6 - - name: SAMPHOLD_INT_BUFDIS - description: Sample and hold mode, internal peripherals only, buffer disabled - value: 7 enum/WAVE: bit_size: 2 variants: diff --git a/data/registers/dac_v3.yaml b/data/registers/dac_v3.yaml index 85de74f..3f30955 100644 --- a/data/registers/dac_v3.yaml +++ b/data/registers/dac_v3.yaml @@ -1,3 +1,8 @@ +# DAC v3, only used in L4. +# Adds CCR, MCR, SHSR, SHHR, SHRR registers. +# Adds CEN fields to CR and BWST and CAL_FLAG fields to SR. +# Deletes BOFF fields from CR. + block/DAC: description: Digital-to-analog converter items: @@ -32,15 +37,15 @@ block/DAC: byte_offset: 16 fieldset: DHR8R - name: DHR12RD - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register byte_offset: 32 fieldset: DHR12RD - name: DHR12LD - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register byte_offset: 36 fieldset: DHR12LD - name: DHR8RD - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register byte_offset: 40 fieldset: DHR8RD - name: DOR @@ -63,58 +68,57 @@ block/DAC: description: mode control register byte_offset: 60 fieldset: MCR - - name: SHSR1 - description: Sample and Hold sample time register + - name: SHSR + description: sample and hold sample time register array: len: 2 stride: 4 byte_offset: 64 fieldset: SHSR - name: SHHR - description: Sample and Hold hold time register + description: sample and hold hold time register byte_offset: 72 fieldset: SHHR - name: SHRR - description: Sample and Hold refresh time register + description: sample and hold refresh time register byte_offset: 76 fieldset: SHRR fieldset/CCR: description: calibration control register fields: - - name: OTRIM1 - description: DAC Channel 1 offset trimming value + - name: OTRIM + description: channel offset trimming value bit_offset: 0 bit_size: 5 - - name: OTRIM2 - description: DAC Channel 2 offset trimming value - bit_offset: 16 - bit_size: 5 + array: + len: 2 + stride: 16 fieldset/CR: description: control register fields: - name: EN - description: DAC channel enable + description: channel enable bit_offset: 0 bit_size: 1 array: len: 2 stride: 16 - name: TEN - description: DAC channel trigger enable - bit_offset: 1 + description: channel trigger enable + bit_offset: 2 bit_size: 1 array: len: 2 stride: 16 - name: TSEL - description: DAC channel 1 trigger selection - bit_offset: 2 - bit_size: 4 + description: channel trigger selection + bit_offset: 3 + bit_size: 3 array: len: 2 stride: 16 - name: WAVE - description: DAC channel noise/triangle wave generation enable + description: channel noise/triangle wave generation enable bit_offset: 6 bit_size: 2 array: @@ -122,21 +126,21 @@ fieldset/CR: stride: 16 enum: WAVE - name: MAMP - description: DAC channel mask/amplitude selector + description: channel mask/amplitude selector bit_offset: 8 bit_size: 4 array: len: 2 stride: 16 - name: DMAEN - description: DAC channel DMA enable + description: channel DMA enable bit_offset: 12 bit_size: 1 array: len: 2 stride: 16 - name: DMAUDRIE - description: DAC channel DMA Underrun Interrupt enable + description: channel DMA Underrun Interrupt enable bit_offset: 13 bit_size: 1 array: @@ -153,14 +157,14 @@ fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 fieldset/DHR12LD: - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 array: @@ -170,14 +174,14 @@ fieldset/DHR12R: description: channel 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 fieldset/DHR12RD: - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 array: @@ -187,14 +191,14 @@ fieldset/DHR8R: description: channel 8-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 fieldset/DHR8RD: - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 array: @@ -204,7 +208,7 @@ fieldset/DOR: description: channel data output register fields: - name: DOR - description: DAC channel data output + description: channel data output bit_offset: 0 bit_size: 12 fieldset/MCR: @@ -219,51 +223,51 @@ fieldset/MCR: len: 2 stride: 16 fieldset/SHHR: - description: Sample and Hold hold time register + description: sample and hold hold time register fields: - name: THOLD - description: DAC channel hold Time + description: channel hold time bit_offset: 0 bit_size: 10 array: len: 2 stride: 16 fieldset/SHRR: - description: Sample and Hold refresh time register + description: sample and hold refresh time register fields: - name: TREFRESH - description: DAC channel refresh Time + description: channel refresh time bit_offset: 0 bit_size: 8 array: len: 2 stride: 16 fieldset/SHSR: - description: Sample and Hold sample time register + description: sample and hold sample time register fields: - name: TSAMPLE - description: DAC channel sample Time + description: channel sample time bit_offset: 0 bit_size: 10 fieldset/SR: description: status register fields: - name: DMAUDR - description: DAC channel DMA underrun flag + description: channel DMA underrun flag bit_offset: 13 bit_size: 1 array: len: 2 stride: 16 - name: CAL_FLAG - description: DAC channel calibration offset status + description: channel calibration offset status bit_offset: 14 bit_size: 1 array: len: 2 stride: 16 - name: BWST - description: DAC channel busy writing sample time flag + description: channel busy writing sample time flag bit_offset: 15 bit_size: 1 array: @@ -273,7 +277,7 @@ fieldset/SWTRIGR: description: software trigger register fields: - name: SWTRIG - description: DAC channel software trigger + description: channel software trigger bit_offset: 0 bit_size: 1 array: diff --git a/data/registers/dac_v4.yaml b/data/registers/dac_v4.yaml index 070de38..9a42d0c 100644 --- a/data/registers/dac_v4.yaml +++ b/data/registers/dac_v4.yaml @@ -1,3 +1,6 @@ +# DAC v4, used in G0, H7, WL. +# Moves CR.TEN to bit 1, extends CR.TSEL to be 4 bits (2 to 5). + block/DAC: description: Digital-to-analog converter items: @@ -32,15 +35,15 @@ block/DAC: byte_offset: 16 fieldset: DHR8R - name: DHR12RD - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register byte_offset: 32 fieldset: DHR12RD - name: DHR12LD - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register byte_offset: 36 fieldset: DHR12LD - name: DHR8RD - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register byte_offset: 40 fieldset: DHR8RD - name: DOR @@ -63,69 +66,57 @@ block/DAC: description: mode control register byte_offset: 60 fieldset: MCR - - name: SHSR1 - description: Sample and Hold sample time register + - name: SHSR + description: sample and hold sample time register array: len: 2 stride: 4 byte_offset: 64 fieldset: SHSR - name: SHHR - description: Sample and Hold hold time register + description: sample and hold hold time register byte_offset: 72 fieldset: SHHR - name: SHRR - description: Sample and Hold refresh time register + description: sample and hold refresh time register byte_offset: 76 fieldset: SHRR - - name: STR - description: Sawtooth register - byte_offset: 88 - fieldset: STR - array: - len: 2 - stride: 4 - - name: STMODR - description: Sawtooth Mode register - byte_offset: 96 - fieldset: STMODR fieldset/CCR: description: calibration control register fields: - - name: OTRIM1 - description: DAC Channel 1 offset trimming value + - name: OTRIM + description: channel offset trimming value bit_offset: 0 bit_size: 5 - - name: OTRIM2 - description: DAC Channel 2 offset trimming value - bit_offset: 16 - bit_size: 5 + array: + len: 2 + stride: 16 fieldset/CR: description: control register fields: - name: EN - description: DAC channel enable + description: channel enable bit_offset: 0 bit_size: 1 array: len: 2 stride: 16 - name: TEN - description: DAC channel trigger enable + description: channel trigger enable bit_offset: 1 bit_size: 1 array: len: 2 stride: 16 - name: TSEL - description: DAC channel 1 trigger selection + description: channel trigger selection bit_offset: 2 bit_size: 4 array: len: 2 stride: 16 - name: WAVE - description: DAC channel noise/triangle wave generation enable + description: channel noise/triangle wave generation enable bit_offset: 6 bit_size: 2 array: @@ -133,21 +124,21 @@ fieldset/CR: stride: 16 enum: WAVE - name: MAMP - description: DAC channel mask/amplitude selector + description: channel mask/amplitude selector bit_offset: 8 bit_size: 4 array: len: 2 stride: 16 - name: DMAEN - description: DAC channel DMA enable + description: channel DMA enable bit_offset: 12 bit_size: 1 array: len: 2 stride: 16 - name: DMAUDRIE - description: DAC channel DMA Underrun Interrupt enable + description: channel DMA Underrun Interrupt enable bit_offset: 13 bit_size: 1 array: @@ -164,18 +155,14 @@ fieldset/DHR12L: description: channel 12-bit left-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 - - name: DHRB - description: DAC channel 12-bit left-aligned data B. - bit_offset: 20 - bit_size: 12 fieldset/DHR12LD: - description: DUAL DAC 12-bit left aligned data holding register + description: dual 12-bit left aligned data holding register fields: - name: DHR - description: DAC channel 12-bit left-aligned data + description: channel 12-bit left-aligned data bit_offset: 4 bit_size: 12 array: @@ -185,18 +172,14 @@ fieldset/DHR12R: description: channel 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 - - name: DHRB - description: channel 12-bit right-aligned data B - bit_offset: 16 - bit_size: 12 fieldset/DHR12RD: - description: Dual DAC 12-bit right-aligned data holding register + description: dual 12-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 12-bit right-aligned data + description: channel 12-bit right-aligned data bit_offset: 0 bit_size: 12 array: @@ -206,18 +189,14 @@ fieldset/DHR8R: description: channel 8-bit right-aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 - - name: DHRB - description: DAC channel 8-bit right-aligned data B - bit_offset: 8 - bit_size: 8 fieldset/DHR8RD: - description: DUAL DAC 8-bit right aligned data holding register + description: dual 8-bit right aligned data holding register fields: - name: DHR - description: DAC channel 8-bit right-aligned data + description: channel 8-bit right-aligned data bit_offset: 0 bit_size: 8 array: @@ -227,13 +206,9 @@ fieldset/DOR: description: channel data output register fields: - name: DOR - description: DAC channel data output + description: channel data output bit_offset: 0 bit_size: 12 - - name: DORB - description: DAC channel data output B - bit_offset: 16 - bit_size: 12 fieldset/MCR: description: mode control register fields: @@ -245,140 +220,67 @@ fieldset/MCR: array: len: 2 stride: 16 - - name: DMADOUBLE - description: DAC Channel1 DMA double data mode. - bit_offset: 8 - bit_size: 1 - array: - len: 2 - stride: 16 - - name: SINFORMAT - description: Enable signed format for DAC channel1. - bit_offset: 9 - bit_size: 1 - array: - len: 2 - stride: 16 - - name: HFSEL - description: High frequency interface mode selection. - bit_offset: 14 - bit_size: 2 fieldset/SHHR: - description: Sample and Hold hold time register + description: sample and hold hold time register fields: - name: THOLD - description: DAC channel hold Time + description: channel hold time bit_offset: 0 bit_size: 10 array: len: 2 stride: 16 fieldset/SHRR: - description: Sample and Hold refresh time register + description: sample and hold refresh time register fields: - name: TREFRESH - description: DAC channel refresh Time + description: channel refresh time bit_offset: 0 bit_size: 8 array: len: 2 stride: 16 fieldset/SHSR: - description: Sample and Hold sample time register + description: sample and hold sample time register fields: - name: TSAMPLE - description: DAC channel sample Time + description: channel sample time bit_offset: 0 bit_size: 10 fieldset/SR: description: status register fields: - - name: DACRDY - description: DAC channel ready status bit. - bit_offset: 11 - bit_size: 1 - array: - len: 2 - stride: 16 - - name: DORSTAT - description: DAC channel output register status bit. - bit_offset: 12 - bit_size: 1 - array: - len: 2 - stride: 16 - name: DMAUDR - description: DAC channel DMA underrun flag + description: channel DMA underrun flag bit_offset: 13 bit_size: 1 array: len: 2 stride: 16 - name: CAL_FLAG - description: DAC channel calibration offset status + description: channel calibration offset status bit_offset: 14 bit_size: 1 array: len: 2 stride: 16 - name: BWST - description: DAC channel busy writing sample time flag + description: channel busy writing sample time flag bit_offset: 15 bit_size: 1 array: len: 2 stride: 16 -fieldset/STMODR: - description: Sawtooth Mode register. - fields: - - name: STRSTTRIGSEL1 - description: DAC Channel 1 Sawtooth Reset trigger selection. - bit_offset: 0 - bit_size: 4 - - name: STINCTRIGSEL1 - description: DAC Channel 1 Sawtooth Increment trigger selection. - bit_offset: 8 - bit_size: 4 - - name: STRSTTRIGSEL2 - description: DAC Channel 1 Sawtooth Reset trigger selection. - bit_offset: 16 - bit_size: 4 - - name: STINCTRIGSEL2 - description: DAC Channel 2 Sawtooth Increment trigger selection. - bit_offset: 24 - bit_size: 4 -fieldset/STR: - description: Sawtooth register. - fields: - - name: RSTDATA - description: DAC Channel Sawtooth reset value. - bit_offset: 0 - bit_size: 12 - - name: DIR - description: DAC Channel Sawtooth direction setting. - bit_offset: 12 - bit_size: 1 - - name: INCDATA - description: DAC Sawtooth increment value (12.4 bit format) - bit_offset: 16 - bit_size: 16 fieldset/SWTRIGR: description: software trigger register fields: - name: SWTRIG - description: DAC channel software trigger + description: channel software trigger bit_offset: 0 bit_size: 1 array: len: 2 stride: 1 - - name: SWTRIGB - description: DAC channel software trigger B. - bit_offset: 16 - bit_size: 1 - array: - len: 2 - stride: 1 enum/MODE: bit_size: 3 variants: @@ -418,6 +320,3 @@ enum/WAVE: - name: Triangle description: Triangle wave generation enabled value: 2 - - name: Sawtooth - description: Sawtooth wave generation enabled - value: 3 diff --git a/data/registers/dac_v5.yaml b/data/registers/dac_v5.yaml new file mode 100644 index 0000000..1a74a29 --- /dev/null +++ b/data/registers/dac_v5.yaml @@ -0,0 +1,326 @@ +# DAC v5, used in L4+ and L5. +# Adds HFSEL field to CR. + +block/DAC: + description: Digital-to-analog converter + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SWTRIGR + description: software trigger register + byte_offset: 4 + access: Write + fieldset: SWTRIGR + - name: DHR12R + description: channel 12-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 8 + fieldset: DHR12R + - name: DHR12L + description: channel 12-bit left-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 12 + fieldset: DHR12L + - name: DHR8R + description: channel 8-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 16 + fieldset: DHR8R + - name: DHR12RD + description: dual 12-bit right-aligned data holding register + byte_offset: 32 + fieldset: DHR12RD + - name: DHR12LD + description: dual 12-bit left aligned data holding register + byte_offset: 36 + fieldset: DHR12LD + - name: DHR8RD + description: dual 8-bit right aligned data holding register + byte_offset: 40 + fieldset: DHR8RD + - name: DOR + description: channel data output register + array: + len: 2 + stride: 4 + byte_offset: 44 + access: Read + fieldset: DOR + - name: SR + description: status register + byte_offset: 52 + fieldset: SR + - name: CCR + description: calibration control register + byte_offset: 56 + fieldset: CCR + - name: MCR + description: mode control register + byte_offset: 60 + fieldset: MCR + - name: SHSR + description: sample and hold sample time register + array: + len: 2 + stride: 4 + byte_offset: 64 + fieldset: SHSR + - name: SHHR + description: sample and hold hold time register + byte_offset: 72 + fieldset: SHHR + - name: SHRR + description: sample and hold refresh time register + byte_offset: 76 + fieldset: SHRR +fieldset/CCR: + description: calibration control register + fields: + - name: OTRIM + description: channel offset trimming value + bit_offset: 0 + bit_size: 5 + array: + len: 2 + stride: 16 +fieldset/CR: + description: control register + fields: + - name: EN + description: channel enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TEN + description: channel trigger enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TSEL + description: channel trigger selection + bit_offset: 2 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: WAVE + description: channel noise/triangle wave generation enable + bit_offset: 6 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: WAVE + - name: MAMP + description: channel mask/amplitude selector + bit_offset: 8 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: DMAEN + description: channel DMA enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DMAUDRIE + description: channel DMA Underrun Interrupt enable + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CEN + description: DAC channel calibration enable + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: HFSEL + description: high frequency interface mode enable + bit_offset: 15 + bit_size: 1 +fieldset/DHR12L: + description: channel 12-bit left-aligned data holding register + fields: + - name: DHR + description: channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 +fieldset/DHR12LD: + description: dual 12-bit left aligned data holding register + fields: + - name: DHR + description: channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR12R: + description: channel 12-bit right-aligned data holding register + fields: + - name: DHR + description: channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 +fieldset/DHR12RD: + description: dual 12-bit right-aligned data holding register + fields: + - name: DHR + description: channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR8R: + description: channel 8-bit right-aligned data holding register + fields: + - name: DHR + description: channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 +fieldset/DHR8RD: + description: dual 8-bit right aligned data holding register + fields: + - name: DHR + description: channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 8 +fieldset/DOR: + description: channel data output register + fields: + - name: DOR + description: channel data output + bit_offset: 0 + bit_size: 12 +fieldset/MCR: + description: mode control register + fields: + - name: MODE + description: DAC channel mode + bit_offset: 0 + bit_size: 3 + enum: MODE + array: + len: 2 + stride: 16 +fieldset/SHHR: + description: sample and hold hold time register + fields: + - name: THOLD + description: channel hold time + bit_offset: 0 + bit_size: 10 + array: + len: 2 + stride: 16 +fieldset/SHRR: + description: sample and hold refresh time register + fields: + - name: TREFRESH + description: channel refresh time + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 16 +fieldset/SHSR: + description: sample and hold sample time register + fields: + - name: TSAMPLE + description: channel sample time + bit_offset: 0 + bit_size: 10 +fieldset/SR: + description: status register + fields: + - name: DMAUDR + description: channel DMA underrun flag + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CAL_FLAG + description: channel calibration offset status + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: BWST + description: channel busy writing sample time flag + bit_offset: 15 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/SWTRIGR: + description: software trigger register + fields: + - name: SWTRIG + description: channel software trigger + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 +enum/MODE: + bit_size: 3 + variants: + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 +enum/WAVE: + bit_size: 2 + variants: + - name: Disabled + description: Wave generation disabled + value: 0 + - name: Noise + description: Noise wave generation enabled + value: 1 + - name: Triangle + description: Triangle wave generation enabled + value: 2 diff --git a/data/registers/dac_v6.yaml b/data/registers/dac_v6.yaml new file mode 100644 index 0000000..a4c748f --- /dev/null +++ b/data/registers/dac_v6.yaml @@ -0,0 +1,379 @@ +# DAC v6, used in H5 and U5. +# Adds DMADOUBLE and SINFORMAT fields to MCR, DACRDY and DORSTAT fields to SR +# Adds B data fields to data holding registers +# Moves HFSEL from CR to MCR and makes it 2 bits. + +block/DAC: + description: Digital-to-analog converter + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SWTRIGR + description: software trigger register + byte_offset: 4 + access: Write + fieldset: SWTRIGR + - name: DHR12R + description: channel 12-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 8 + fieldset: DHR12R + - name: DHR12L + description: channel 12-bit left-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 12 + fieldset: DHR12L + - name: DHR8R + description: channel 8-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 16 + fieldset: DHR8R + - name: DHR12RD + description: dual 12-bit right-aligned data holding register + byte_offset: 32 + fieldset: DHR12RD + - name: DHR12LD + description: dual 12-bit left aligned data holding register + byte_offset: 36 + fieldset: DHR12LD + - name: DHR8RD + description: dual 8-bit right aligned data holding register + byte_offset: 40 + fieldset: DHR8RD + - name: DOR + description: channel data output register + array: + len: 2 + stride: 4 + byte_offset: 44 + access: Read + fieldset: DOR + - name: SR + description: status register + byte_offset: 52 + fieldset: SR + - name: CCR + description: calibration control register + byte_offset: 56 + fieldset: CCR + - name: MCR + description: mode control register + byte_offset: 60 + fieldset: MCR + - name: SHSR + description: sample and hold sample time register + array: + len: 2 + stride: 4 + byte_offset: 64 + fieldset: SHSR + - name: SHHR + description: sample and hold hold time register + byte_offset: 72 + fieldset: SHHR + - name: SHRR + description: sample and hold refresh time register + byte_offset: 76 + fieldset: SHRR +fieldset/CCR: + description: calibration control register + fields: + - name: OTRIM + description: channel offset trimming value + bit_offset: 0 + bit_size: 5 + array: + len: 2 + stride: 16 +fieldset/CR: + description: control register + fields: + - name: EN + description: channel enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TEN + description: channel trigger enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TSEL + description: channel trigger selection + bit_offset: 2 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: WAVE + description: channel noise/triangle wave generation enable + bit_offset: 6 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: WAVE + - name: MAMP + description: channel mask/amplitude selector + bit_offset: 8 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: DMAEN + description: channel DMA enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DMAUDRIE + description: channel DMA Underrun Interrupt enable + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CEN + description: DAC channel calibration enable + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/DHR12L: + description: channel 12-bit left-aligned data holding register + fields: + - name: DHR + description: channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + - name: DHRB + description: channel 12-bit left-aligned data B + bit_offset: 20 + bit_size: 12 +fieldset/DHR12LD: + description: dual 12-bit left aligned data holding register + fields: + - name: DHR + description: channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR12R: + description: channel 12-bit right-aligned data holding register + fields: + - name: DHR + description: channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + - name: DHRB + description: channel 12-bit right-aligned data B + bit_offset: 16 + bit_size: 12 +fieldset/DHR12RD: + description: dual 12-bit right-aligned data holding register + fields: + - name: DHR + description: channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR8R: + description: channel 8-bit right-aligned data holding register + fields: + - name: DHR + description: channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + - name: DHRB + description: channel 8-bit right-aligned data B + bit_offset: 8 + bit_size: 8 +fieldset/DHR8RD: + description: dual 8-bit right aligned data holding register + fields: + - name: DHR + description: channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 8 +fieldset/DOR: + description: channel data output register + fields: + - name: DOR + description: channel data output + bit_offset: 0 + bit_size: 12 + - name: DORB + description: channel data output B + bit_offset: 16 + bit_size: 12 +fieldset/MCR: + description: mode control register + fields: + - name: MODE + description: DAC channel mode + bit_offset: 0 + bit_size: 3 + enum: MODE + array: + len: 2 + stride: 16 + - name: DMADOUBLE + description: channel DMA double data mode. + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: SINFORMAT + description: enable signed format for DAC channel + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: HFSEL + description: high frequency interface mode selection + bit_offset: 14 + bit_size: 2 +fieldset/SHHR: + description: sample and hold hold time register + fields: + - name: THOLD + description: channel hold time + bit_offset: 0 + bit_size: 10 + array: + len: 2 + stride: 16 +fieldset/SHRR: + description: sample and hold refresh time register + fields: + - name: TREFRESH + description: channel refresh time + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 16 +fieldset/SHSR: + description: sample and hold sample time register + fields: + - name: TSAMPLE + description: channel sample time + bit_offset: 0 + bit_size: 10 +fieldset/SR: + description: status register + fields: + - name: DACRDY + description: channel ready status bit + bit_offset: 11 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DORSTAT + description: channel output register status bit + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DMAUDR + description: channel DMA underrun flag + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CAL_FLAG + description: channel calibration offset status + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: BWST + description: channel busy writing sample time flag + bit_offset: 15 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/SWTRIGR: + description: software trigger register + fields: + - name: SWTRIG + description: channel software trigger + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SWTRIGB + description: channel software trigger B + bit_offset: 16 + bit_size: 1 + array: + len: 2 + stride: 1 +enum/MODE: + bit_size: 3 + variants: + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 +enum/WAVE: + bit_size: 2 + variants: + - name: Disabled + description: Wave generation disabled + value: 0 + - name: Noise + description: Noise wave generation enabled + value: 1 + - name: Triangle + description: Triangle wave generation enabled + value: 2 diff --git a/data/registers/dac_v7.yaml b/data/registers/dac_v7.yaml new file mode 100644 index 0000000..4733672 --- /dev/null +++ b/data/registers/dac_v7.yaml @@ -0,0 +1,423 @@ +# DAC v7, used in G4. +# Adds STR, STMODR for sawtooth control. + +block/DAC: + description: Digital-to-analog converter + items: + - name: CR + description: control register + byte_offset: 0 + fieldset: CR + - name: SWTRIGR + description: software trigger register + byte_offset: 4 + access: Write + fieldset: SWTRIGR + - name: DHR12R + description: channel 12-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 8 + fieldset: DHR12R + - name: DHR12L + description: channel 12-bit left-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 12 + fieldset: DHR12L + - name: DHR8R + description: channel 8-bit right-aligned data holding register + array: + len: 2 + stride: 12 + byte_offset: 16 + fieldset: DHR8R + - name: DHR12RD + description: dual 12-bit right-aligned data holding register + byte_offset: 32 + fieldset: DHR12RD + - name: DHR12LD + description: dual 12-bit left aligned data holding register + byte_offset: 36 + fieldset: DHR12LD + - name: DHR8RD + description: dual 8-bit right aligned data holding register + byte_offset: 40 + fieldset: DHR8RD + - name: DOR + description: channel data output register + array: + len: 2 + stride: 4 + byte_offset: 44 + access: Read + fieldset: DOR + - name: SR + description: status register + byte_offset: 52 + fieldset: SR + - name: CCR + description: calibration control register + byte_offset: 56 + fieldset: CCR + - name: MCR + description: mode control register + byte_offset: 60 + fieldset: MCR + - name: SHSR + description: sample and hold sample time register + array: + len: 2 + stride: 4 + byte_offset: 64 + fieldset: SHSR + - name: SHHR + description: sample and hold hold time register + byte_offset: 72 + fieldset: SHHR + - name: SHRR + description: sample and hold refresh time register + byte_offset: 76 + fieldset: SHRR + - name: STR + description: Sawtooth register + byte_offset: 88 + fieldset: STR + array: + len: 2 + stride: 4 + - name: STMODR + description: Sawtooth Mode register + byte_offset: 96 + fieldset: STMODR +fieldset/CCR: + description: calibration control register + fields: + - name: OTRIM + description: channel offset trimming value + bit_offset: 0 + bit_size: 5 + array: + len: 2 + stride: 16 +fieldset/CR: + description: control register + fields: + - name: EN + description: channel enable + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TEN + description: channel trigger enable + bit_offset: 1 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: TSEL + description: channel trigger selection + bit_offset: 2 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: WAVE + description: channel noise/triangle wave generation enable + bit_offset: 6 + bit_size: 2 + array: + len: 2 + stride: 16 + enum: WAVE + - name: MAMP + description: channel mask/amplitude selector + bit_offset: 8 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: DMAEN + description: channel DMA enable + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DMAUDRIE + description: channel DMA Underrun Interrupt enable + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CEN + description: DAC channel calibration enable + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/DHR12L: + description: channel 12-bit left-aligned data holding register + fields: + - name: DHR + description: channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + - name: DHRB + description: channel 12-bit left-aligned data B + bit_offset: 20 + bit_size: 12 +fieldset/DHR12LD: + description: dual 12-bit left aligned data holding register + fields: + - name: DHR + description: channel 12-bit left-aligned data + bit_offset: 4 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR12R: + description: channel 12-bit right-aligned data holding register + fields: + - name: DHR + description: channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + - name: DHRB + description: channel 12-bit right-aligned data B + bit_offset: 16 + bit_size: 12 +fieldset/DHR12RD: + description: dual 12-bit right-aligned data holding register + fields: + - name: DHR + description: channel 12-bit right-aligned data + bit_offset: 0 + bit_size: 12 + array: + len: 2 + stride: 16 +fieldset/DHR8R: + description: channel 8-bit right-aligned data holding register + fields: + - name: DHR + description: channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + - name: DHRB + description: channel 8-bit right-aligned data B + bit_offset: 8 + bit_size: 8 +fieldset/DHR8RD: + description: dual 8-bit right aligned data holding register + fields: + - name: DHR + description: channel 8-bit right-aligned data + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 8 +fieldset/DOR: + description: channel data output register + fields: + - name: DOR + description: channel data output + bit_offset: 0 + bit_size: 12 + - name: DORB + description: channel data output B + bit_offset: 16 + bit_size: 12 +fieldset/MCR: + description: mode control register + fields: + - name: MODE + description: DAC channel mode + bit_offset: 0 + bit_size: 3 + enum: MODE + array: + len: 2 + stride: 16 + - name: DMADOUBLE + description: channel DMA double data mode. + bit_offset: 8 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: SINFORMAT + description: enable signed format for DAC channel + bit_offset: 9 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: HFSEL + description: high frequency interface mode selection + bit_offset: 14 + bit_size: 2 +fieldset/SHHR: + description: sample and hold hold time register + fields: + - name: THOLD + description: channel hold time + bit_offset: 0 + bit_size: 10 + array: + len: 2 + stride: 16 +fieldset/SHRR: + description: sample and hold refresh time register + fields: + - name: TREFRESH + description: channel refresh time + bit_offset: 0 + bit_size: 8 + array: + len: 2 + stride: 16 +fieldset/SHSR: + description: sample and hold sample time register + fields: + - name: TSAMPLE + description: channel sample time + bit_offset: 0 + bit_size: 10 +fieldset/SR: + description: status register + fields: + - name: DACRDY + description: channel ready status bit + bit_offset: 11 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DORSTAT + description: channel output register status bit + bit_offset: 12 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: DMAUDR + description: channel DMA underrun flag + bit_offset: 13 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: CAL_FLAG + description: channel calibration offset status + bit_offset: 14 + bit_size: 1 + array: + len: 2 + stride: 16 + - name: BWST + description: channel busy writing sample time flag + bit_offset: 15 + bit_size: 1 + array: + len: 2 + stride: 16 +fieldset/STMODR: + description: sawtooth mode register + fields: + - name: STRSTTRIGSEL + description: channel sawtooth reset trigger selection + bit_offset: 0 + bit_size: 4 + array: + len: 2 + stride: 16 + - name: STINCTRIGSEL + description: channel sawtooth increment trigger selection + bit_offset: 8 + bit_size: 4 + array: + len: 2 + stride: 16 +fieldset/STR: + description: sawtooth register + fields: + - name: RSTDATA + description: channel sawtooth reset value. + bit_offset: 0 + bit_size: 12 + - name: DIR + description: channel sawtooth direction setting + bit_offset: 12 + bit_size: 1 + - name: INCDATA + description: channel sawtooth increment value (12.4 bit format) + bit_offset: 16 + bit_size: 16 +fieldset/SWTRIGR: + description: software trigger register + fields: + - name: SWTRIG + description: channel software trigger + bit_offset: 0 + bit_size: 1 + array: + len: 2 + stride: 1 + - name: SWTRIGB + description: channel software trigger B + bit_offset: 16 + bit_size: 1 + array: + len: 2 + stride: 1 +enum/MODE: + bit_size: 3 + variants: + - name: NORMAL_EXT_BUFEN + description: Normal mode, external pin only, buffer enabled + value: 0 + - name: NORMAL_EXT_INT_BUFEN + description: Normal mode, external pin and internal peripherals, buffer enabled + value: 1 + - name: NORMAL_EXT_BUFDIS + description: Normal mode, external pin only, buffer disabled + value: 2 + - name: NORMAL_INT_BUFDIS + description: Normal mode, internal peripherals only, buffer disabled + value: 3 + - name: SAMPHOLD_EXT_BUFEN + description: Sample and hold mode, external pin only, buffer enabled + value: 4 + - name: SAMPHOLD_EXT_INT_BUFEN + description: Sample and hold mode, external pin and internal peripherals, buffer enabled + value: 5 + - name: SAMPHOLD_EXT_INT_BUFDIS + description: Sample and hold mode, external pin and internal peripherals, buffer disabled + value: 6 + - name: SAMPHOLD_INT_BUFDIS + description: Sample and hold mode, internal peripherals only, buffer disabled + value: 7 +enum/WAVE: + bit_size: 2 + variants: + - name: Disabled + description: Wave generation disabled + value: 0 + - name: Noise + description: Noise wave generation enabled + value: 1 + - name: Triangle + description: Triangle wave generation enabled + value: 2 + - name: Sawtooth + description: Sawtooth wave generation enabled + value: 3 diff --git a/stm32-data-gen/src/chips.rs b/stm32-data-gen/src/chips.rs index bf977ad..d947c41 100644 --- a/stm32-data-gen/src/chips.rs +++ b/stm32-data-gen/src/chips.rs @@ -176,13 +176,19 @@ impl PeriMatcher { (".*:I2C:F0-i2c2_v1_1", ("i2c", "v2", "I2C")), (".*:I2C:i2c2_v1_1F7", ("i2c", "v2", "I2C")), (".*:I2C:i2c2_v1_1U5", ("i2c", "v2", "I2C")), - (".*:DAC:dacif_v1_1", ("dac", "v1", "DAC")), - (".*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")), - (".*:DAC:F0dacif_v1_1", ("dac", "v1", "DAC")), - (".*:DAC:dacif_v2_0", ("dac", "v2", "DAC")), - (".*:DAC:dacif_v3_0", ("dac", "v3", "DAC")), - (".*:DAC:F3_dacif_v1_1", ("dac", "v1", "DAC")), - (".*:DAC:G4_dacif_v4_0", ("dac", "v4", "DAC")), + ("STM32F10[1357].*:DAC:dacif_v1_1F1", ("dac", "v1", "DAC")), // Original F1 are v1 + (".*:DAC:dacif_v1_1F1", ("dac", "v2", "DAC")), + (".*:DAC:F0dacif_v1_1", ("dac", "v2", "DAC")), + (".*:DAC:F3_dacif_v1_1", ("dac", "v2", "DAC")), + (".*:DAC:dacif_v1_1", ("dac", "v2", "DAC")), + (".*:DAC:dacif_v1_2", ("dac", "v2", "DAC")), + ("STM32L4[1-9A].*:DAC:dacif_v2_0", ("dac", "v3", "DAC")), // L4 non-plus are v3 + (".*:DAC:dacif_v2_0", ("dac", "v5", "DAC")), + (".*:DAC:dacif_v2_0_U5", ("dac", "v6", "DAC")), + (".*:DAC:dacif_v3_0", ("dac", "v4", "DAC")), + (".*:DAC:WL_dacif_v3_0", ("dac", "v4", "DAC")), + (".*:DAC:G4_dacif_v4_0", ("dac", "v7", "DAC")), + (".*:DAC:dacif_v5_0", ("dac", "v6", "DAC")), (".*:ADC:aditf_v2_5F1", ("adc", "f1", "ADC")), (".*:ADC:aditf5_v1_1", ("adc", "f3", "ADC")), (".*:ADC:aditf_v2_5", ("adc", "f3_v2", "ADC")), From a0f7bc881afa0ef6fd2d101ff5d6055bafecd1c3 Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Sun, 19 Nov 2023 13:29:43 +0000 Subject: [PATCH 4/5] WL5/WLE: rename DAC1EN to DACEN in RCC, per reference manual and peripheral name --- data/registers/rcc_wl5.yaml | 16 ++++++++-------- data/registers/rcc_wle.yaml | 4 ++-- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/data/registers/rcc_wl5.yaml b/data/registers/rcc_wl5.yaml index f04ffe1..e4ce570 100644 --- a/data/registers/rcc_wl5.yaml +++ b/data/registers/rcc_wl5.yaml @@ -417,8 +417,8 @@ fieldset/APB1ENR1: description: CPU1 I2C3 clocks enable bit_offset: 23 bit_size: 1 - - name: DAC1EN - description: CPU1 DAC1 clock enable + - name: DACEN + description: CPU1 DAC clock enable bit_offset: 29 bit_size: 1 - name: LPTIM1EN @@ -468,7 +468,7 @@ fieldset/APB1RSTR1: bit_offset: 23 bit_size: 1 - name: DACRST - description: DAC1 reset + description: DAC reset bit_offset: 29 bit_size: 1 - name: LPTIM1RST @@ -526,7 +526,7 @@ fieldset/APB1SMENR1: bit_offset: 23 bit_size: 1 - name: DACSMEN - description: DAC1 clock enable during CPU1 CSleep mode. + description: DAC clock enable during CPU1 CSleep mode. bit_offset: 29 bit_size: 1 - name: LPTIM1SMEN @@ -868,8 +868,8 @@ fieldset/C2APB1ENR1: description: CPU2 I2C3 clocks enable bit_offset: 23 bit_size: 1 - - name: DAC1EN - description: CPU2 DAC1 clock enable + - name: DACEN + description: CPU2 DAC clock enable bit_offset: 29 bit_size: 1 - name: LPTIM1EN @@ -922,8 +922,8 @@ fieldset/C2APB1SMENR1: description: I2C3 clock enable during CPU2 CSleep and CStop modes bit_offset: 23 bit_size: 1 - - name: DAC1SMEN - description: DAC1 clock enable during CPU2 CSleep mode. + - name: DACSMEN + description: DAC clock enable during CPU2 CSleep mode. bit_offset: 29 bit_size: 1 - name: LPTIM1SMEN diff --git a/data/registers/rcc_wle.yaml b/data/registers/rcc_wle.yaml index a02e7a7..f0c5748 100644 --- a/data/registers/rcc_wle.yaml +++ b/data/registers/rcc_wle.yaml @@ -353,8 +353,8 @@ fieldset/APB1ENR1: description: CPU1 I2C3 clocks enable bit_offset: 23 bit_size: 1 - - name: DAC1EN - description: CPU1 DAC1 clock enable + - name: DACEN + description: CPU1 DAC clock enable bit_offset: 29 bit_size: 1 - name: LPTIM1EN From be9d7fd58465672802d6521a1cc06ccc26578028 Mon Sep 17 00:00:00 2001 From: Adam Greig Date: Sun, 19 Nov 2023 13:47:13 +0000 Subject: [PATCH 5/5] H5: rename DAC12EN to DAC1EN to match peripheral name --- data/registers/rcc_h5.yaml | 6 +++--- data/registers/rcc_h50.yaml | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/data/registers/rcc_h5.yaml b/data/registers/rcc_h5.yaml index 3ddf959..cd17b59 100644 --- a/data/registers/rcc_h5.yaml +++ b/data/registers/rcc_h5.yaml @@ -378,7 +378,7 @@ fieldset/AHB2ENR: description: "ADC1 and 2 peripherals clock enabled\r Set and reset by software." bit_offset: 10 bit_size: 1 - - name: DAC12EN + - name: DAC1EN description: "DAC clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 @@ -457,7 +457,7 @@ fieldset/AHB2LPENR: description: "ADC1 and 2 peripherals clock enable during sleep mode\r Set and reset by software." bit_offset: 10 bit_size: 1 - - name: DAC12LPEN + - name: DAC1LPEN description: "DAC clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 @@ -536,7 +536,7 @@ fieldset/AHB2RSTR: description: "ADC1 and 2 blocks reset\r Set and reset by software." bit_offset: 10 bit_size: 1 - - name: DAC12RST + - name: DAC1RST description: "DAC block reset\r Set and reset by software." bit_offset: 11 bit_size: 1 diff --git a/data/registers/rcc_h50.yaml b/data/registers/rcc_h50.yaml index 1376225..ae5d726 100644 --- a/data/registers/rcc_h50.yaml +++ b/data/registers/rcc_h50.yaml @@ -270,7 +270,7 @@ fieldset/AHB2ENR: description: "ADC1 peripherals clock enabled\r Set and reset by software." bit_offset: 10 bit_size: 1 - - name: DAC12EN + - name: DAC1EN description: "DAC clock enable\r Set and reset by software." bit_offset: 11 bit_size: 1 @@ -313,7 +313,7 @@ fieldset/AHB2LPENR: description: "ADC1 peripherals clock enable during sleep mode\r Set and reset by software." bit_offset: 10 bit_size: 1 - - name: DAC12LPEN + - name: DAC1LPEN description: "DAC clock enable during sleep mode\r Set and reset by software." bit_offset: 11 bit_size: 1 @@ -356,7 +356,7 @@ fieldset/AHB2RSTR: description: "ADC1 block reset\r Set and reset by software." bit_offset: 10 bit_size: 1 - - name: DAC12RST + - name: DAC1RST description: "DAC block reset\r Set and reset by software." bit_offset: 11 bit_size: 1