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rtc/bd fixes.

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This commit is contained in:
Dario Nieuwenhuis 2023-10-11 03:41:10 +02:00
parent 9f45b0c48c
commit 6bfa5a0dce
3 changed files with 7 additions and 16 deletions
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16
data/registers/pwr_u5.yaml
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@ -41,10 +41,10 @@ block/PWR:
description: Backup domain control register 2 description: Backup domain control register 2
byte_offset: 36 byte_offset: 36
fieldset: BDCR2 fieldset: BDCR2
- name: DBPR - name: DBPCR
description: disable Backup domain register description: disable Backup domain register
byte_offset: 40 byte_offset: 40
fieldset: DBPR fieldset: DBPCR
- name: UCPDR - name: UCPDR
description: USB Type-C™ and Power Delivery register description: USB Type-C™ and Power Delivery register
byte_offset: 44 byte_offset: 44
@ -309,14 +309,13 @@ fieldset/CR3:
description: Fast soft start description: Fast soft start
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
fieldset/DBPR: fieldset/DBPCR:
description: disable Backup domain register description: disable Backup domain register
fields: fields:
- name: DBP - name: DBP
description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers." description: "Disable Backup domain write protection\r In reset state, all registers and SRAM in Backup domain are protected against parasitic write access. This bit must be set to enable the write access to these registers."
bit_offset: 0 bit_offset: 0
bit_size: 1 bit_size: 1
enum: DBP
fieldset/PCR: fieldset/PCR:
description: Power Port pull control register description: Power Port pull control register
fields: fields:
@ -643,15 +642,6 @@ enum/ACTVOS:
- name: Range1 - name: Range1
description: Range 1 (highest frequency) description: Range 1 (highest frequency)
value: 3 value: 3
enum/DBP:
bit_size: 1
variants:
- name: Disabled
description: Write access to Backup domain disabled
value: 0
- name: Enabled
description: Write access to Backup domain enabled
value: 1
enum/FLASHFWU: enum/FLASHFWU:
bit_size: 1 bit_size: 1
variants: variants:

6
data/registers/pwr_wba.yaml
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@ -33,10 +33,10 @@ block/PWR:
description: wakeup control register 3 description: wakeup control register 3
byte_offset: 28 byte_offset: 28
fieldset: WUCR3 fieldset: WUCR3
- name: DBPR - name: DBPCR
description: disable Backup domain register description: disable Backup domain register
byte_offset: 40 byte_offset: 40
fieldset: DBPR fieldset: DBPCR
- name: SECCFGR - name: SECCFGR
description: security configuration register description: security configuration register
byte_offset: 48 byte_offset: 48
@ -136,7 +136,7 @@ fieldset/CR3:
description: Fast soft start description: Fast soft start
bit_offset: 2 bit_offset: 2
bit_size: 1 bit_size: 1
fieldset/DBPR: fieldset/DBPCR:
description: disable Backup domain register description: disable Backup domain register
fields: fields:
- name: DBP - name: DBP

1
stm32-data-gen/src/chips.rs
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@ -254,6 +254,7 @@ impl PeriMatcher {
("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")), ("STM32L4.*:RTC:rtc2_.*", ("rtc", "v2l4", "RTC")),
("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), ("STM32WBA.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")), ("STM32WB.*:RTC:rtc2_.*", ("rtc", "v2wb", "RTC")),
("STM32H5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")),
("STM32U5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), // Cube says v2, but it's v3 with security stuff ("STM32U5.*:RTC:rtc2_.*", ("rtc", "v3u5", "RTC")), // Cube says v2, but it's v3 with security stuff
(".*:RTC:rtc3_v1_0", ("rtc", "v3", "RTC")), (".*:RTC:rtc3_v1_0", ("rtc", "v3", "RTC")),
(".*:RTC:rtc3_v1_1", ("rtc", "v3", "RTC")), (".*:RTC:rtc3_v1_1", ("rtc", "v3", "RTC")),